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* drivers/i2c/ptn3460: Add early init optionJan Samek2022-09-222-0/+52
| | | | | | | | | | | | | | | | | | | | Create Kconfig options and boot state machine callback in ramstage for an early initialization of the PTN3460 DP-to-LVDS bridge. This allows showing the bootsplash screen on mainboards utilizing this chip during the PCI device enumeration. BUG=none TEST=Select PTN3460_EARLY_INIT config switch in mainboard Kconfig and check the log for "Attempting PTN3460 early init" message. If the board (e.g. siemens/mc_apl7 in this case) is also configured for showing the bootsplash logo, it should be now visible. Change-Id: I5424d062b3fb63c78cfced3971376353be11c504 Signed-off-by: Jan Samek <jan.samek@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67681 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Uwe Poeche <uwe.poeche@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* drivers/smbus: add smbus console driverHusni Faiz2022-09-162-0/+17
| | | | | | | | | | | This patch adds a new smbus console driver and Kconfig options to enable the driver. Change-Id: Ife77fb2c3e1cc77678a4972701317d50624ceb95 Signed-off-by: Husni Faiz <ahamedhusni73@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67339 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* drivers/usb/hub/acpi.c: Don't use heap for ACPI nameArthur Heymans2022-09-162-5/+10
| | | | | | | | | | | | | | | | Using malloc would increase the heap use each time this function is called. Instead allocate a per struct device buffer inside the chip_info struct. Found by coverity scan, CID 1488815. Change-Id: Ie24870b34338624b3bf3a6f420debdd24a68ffbd Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64338 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* drivers/i2c/nau8825: Add ADCOUT IO drive strength controlEric Lai2022-09-162-0/+6
| | | | | | | | | | | | | Add a property to control the driving of ADCOUT. BUG=b:234789689 TEST= build passed. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: Ibbedd5838a795ee645a5458b960062c5530ff3b5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67659 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
* Revert "drivers/wifi: Move MTL Magnetar CNVi DIDs from SoC to generic driver"Subrata Banik2022-09-161-5/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 510a55d4eeaeb32047c17328ef238b55b89e7296. Reason for revert: Observed `missing read resource` issue for cnvi device BUG=b:244687646 TEST=No error seen in AP log while booting Google/rex Without this patch: [SPEW ] PCI: 00:14.3 read_resources bus 0 link: 0 [ERROR] GENERIC: 0.0 missing read_resources [SPEW ] PCI: 00:14.3 read_resources bus 0 link: 0 done With this patch: [SPEW ] PCI: 00:14.3 read_resources bus 0 link: 0 [SPEW ] PCI: 00:14.3 read_resources bus 0 link: 0 done Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I1e881313729f1088cffa7c161722ee79bb9acc49 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67566 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
* timer: Change timer util functions to 64-bitRob Barnes2022-09-143-5/+5
| | | | | | | | | | | | | | | | | | | | Since mono_time is now 64-bit, the utility functions interfacing with mono_time should also be 64-bit so precision isn't lost. Fixed build errors related to printing the now int64_t result of stopwatch_duration_[m|u]secs in various places. BUG=b:237082996 BRANCH=All TEST=Boot dewatt Change-Id: I169588f5e14285557f2d03270f58f4c07c0154d5 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66170 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* Revert "drivers/mrc_cache: Don't compute checksum if TPM hash is used"Reka Norman2022-09-121-3/+3
| | | | | | | | | | | | | | | | | | | | This reverts commit f83b7d494e3ceb6bec11027ae5f21999ee5ad196. It turns out we have tests which use `futility validate_rec_mrc` to validate the MRC cache, which includes verifying the data checksum. Revert this to allow the tests to pass while we figure out how to fix this. BUG=b:245277259, b:242667207 TEST=None Signed-off-by: Reka Norman <rekanorman@chromium.org> Change-Id: Id913d00584444c21cb94668bdc96f4de51af7cee Reviewed-on: https://review.coreboot.org/c/coreboot/+/67432 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* drivers/intel/ptt: Use the correct detection methodMichał Żygowski2022-09-121-0/+12
| | | | | | | | | | | | | | | | | | | | On some platforms the HFSTS4 bit 19 does not indicate active PTT. Instead of ME HFSTS4, use TXT FTIF register to check active TPM for the current boot. Discrete TPM shall be deactivated when PTT is enabled so this always should return true value of PTT state. Leave the old method for backwards compatibility if TXT FTIF would not be applicable for older microarchitectures. Based on DOC #560297. TEST=Check if PTT is detected as active on MSI PRO Z690-A DDR4 WIFI Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I3a55c9f38f5bb94fb1186592446a28e675c1207c Reviewed-on: https://review.coreboot.org/c/coreboot/+/63956 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
* drivers/intel/fsp2_0: Fix location of timestamp for loading FSP-SReka Norman2022-09-081-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, the "loading FSP-S" timestamp is added in fsp_silicon_init(). However, most Intel platforms actually load FSP-S earlier than this, in soc_fsp_load(). So the timestamp is added in the wrong place. Add the timestamp in fsps_load() instead, after the load_done early return so that it will only be added for the first call. Before: 949:finished CSE firmware sync 961,833 (17,998) 17:starting LZ4 decompress (ignore for x86) 1,018,328 (56,495) 18:finished LZ4 decompress (ignore for x86) 1,018,797 (469) 30:device enumeration 1,035,096 (16,298) 971:loading FSP-S 1,048,082 (12,986) 954:calling FspSiliconInit 1,049,331 (1,249) After: 949:finished CSE firmware sync 959,355 (16,370) 971:loading FSP-S 978,139 (18,784) 17:starting LZ4 decompress (ignore for x86) 1,015,796 (37,656) 18:finished LZ4 decompress (ignore for x86) 1,016,271 (475) 30:device enumeration 1,032,567 (16,295) 954:calling FspSiliconInit 1,046,867 (14,300) BUG=b:239769975 TEST="loading FSP-S" is added in the right place on nivviks (see above). Change-Id: Ib26cf96ae97766333fe75ae44381d4f7c6cc7b61 Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67334 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* drivers/i2c: Add a new RTC RV-3028-C7 from Micro CrystalWerner Zeh2022-09-075-0/+289
| | | | | | | | | | | | | | | This patch adds a driver for a new RTC from Micro Crystal. Supported features are: * configure backup voltage switchover via devicetree * configure backup capacitor charging mode via devicetree * set date if a voltage drop on backup voltage was detected to either a user definable (devicetree) or coreboot build date Change-Id: I37176ea726e50e4e74d409488981d7618ecff8bb Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67099 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
* drivers/intel/dptf: Add multiple fan support under dptfSumeet Pawnikar2022-09-042-16/+79
| | | | | | | | | | | | | | Add multiple fan support for dptf policies BUG=b:235254828 BRANCH=None TEST=Built and tested on Redrix system for two fans Change-Id: I96ead90e3b805bd20de03e4bef4fa4b9fbaaaedd Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65611 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* drivers/elog/gsmi.c: Fix compiling for 64bitArthur Heymans2022-09-011-3/+4
| | | | | | | | Change-Id: Ic8e04ae043145a3633c0b8379a797724f95fd7ea Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65880 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* drivers/i2c/tpm: Remove TI50_FIRMWARE_VERSION_NOT_SUPPORTEDReka Norman2022-08-291-7/+0
| | | | | | | | | | | | | | | | | | | This workaround was added since reading the firmware version on Ti50 versions < 0.0.15 will cause the Ti50 to become unresponsive. No one is using Ti50 this old anymore, so remove the workaround. BUG=b:224650720,b:236911319 TEST=Boot to OS on nivviks with Ti50 0.22.4. Check the log contains the firmware version: [INFO ] Firmware version: Ti50/D3C1 RO_B:0.0.26/- RW_B:0.22.4/ti50_common:v095c Change-Id: I3628b799e436a80d0512dabd356c4b2566ed600a Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67138 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
* drivers/mrc_cache: Don't compute checksum if TPM hash is usedReka Norman2022-08-271-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When MRC_SAVE_HASH_IN_TPM is selected, mrc_data_valid() uses the TPM hash to verify the MRC cache data, not the checksum. However, we still calculate the checksum when updating the cache. Skip this calculation when MRC_SAVE_HASH_IN_TPM is selected to save boot time. On nissa, this reduces boot time by ~14 ms: Before: 3:after RAM initialization 854,298 (28,226) After: 3:after RAM initialization 849,626 (14,463) Note, the reason the calculation is so slow is that the new MRC data lives in CBMEM, which is not yet marked as cacheable in romstage. BUG=b:242667207 TEST=MRC caching still works as expected on nivviks. After clearing the MRC cache, memory training happens on the next boot, but doesn't on subsequent boots. Change-Id: Ifbb75ecfa17421c0565aec1f3eb48d950244f821 Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67042 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Shelley Chen <shchen@google.com>
* drivers: Implement EFI_PEI_MP_SERVICES_PPI with FSP_UNSUPPORTED typeSubrata Banik2022-08-243-0/+98
| | | | | | | | | | | | | | | | | | | | | | | This patch implements EFI_PEI_MP_SERVICES_PPI structure definitions with APIs that return mp_api_unsupported(). The reason behind this change is to fix an FSP issue where FSP assumes ownership of the APs (Application Processors) upon passing a `NULL` pointer to the CpuMpPpi FSP-S UPD.Hence, this patch implements `MP_SERVICES_PPI_DEFAULT` config to fill EFI_PEI_MP_SERVICES_PPI with `mp_api_unsupported` APIs. Later this data structure can be passed to the CpuMpPpi UPD to avoid APs from getting hijacked by FSP while coreboot decides to set SkipMpInit UPD. TEST=Able to build and boot Google/Taeko with this patch. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I31fcaa2aa633071b6d6bfa05dbe891ef87978d2c Reviewed-on: https://review.coreboot.org/c/coreboot/+/66708 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* drivers/spi/tpm: Add Ti50 entry to dev_mapYidi Lin2022-08-241-0/+1
| | | | | | | | | | | BUG=none TEST=See "[INFO ] Initialized TPM device TI50 revision 83" Signed-off-by: Yidi Lin <yidilin@chromium.org> Change-Id: I3af5f4653b6b8ecd086f85ec573530a4e5c57211 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66786 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* drivers/siemens/nc_fpga: Fix typo in commentAngel Pons2022-08-231-1/+1
| | | | | | | | | | | earyl ---> early Change-Id: I06412fd9487aaa1115fdbd86ff44b34db97d97d8 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66746 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Uwe Poeche <uwe.poeche@siemens.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
* tpm: Correct TI50_FIRMWARE_VERSION_NOT_SUPPORTED help textYu-Ping Wu2022-08-211-1/+1
| | | | | | | | | | | | | | | | | | | | Reading firmware_version register is supported on Ti50 version 0.22.4. Therefore correct the help text of the Kconfig option TI50_FIRMWARE_VERSION_NOT_SUPPORTED. Also change the message level to BIOS_WARNING. BUG=b:234533588 TEST=emerge-corsola coreboot BRANCH=none Change-Id: I66a0ef896c9dc4cd0f586555a55dbcd1cfd863f9 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66906 Reviewed-by: Yidi Lin <yidilin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Andrey Pronin <apronin@google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
* mb/google/brya/var/ghost: Enable NXP UWB SR150 chipJack Rosenthal2022-08-171-1/+1
| | | | | | | | | | | | | | | Add GPIO configuration and device tree to enable the chip. BUG=b:240607130 BRANCH=firmware-brya-14505.B TEST=Patch linux with NXP's pending drivers UWB device is probed and can respond to a simple hello packet Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Change-Id: I83be712d243c365a5cbfe6f69a6bd85440c5bec7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66471 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* drivers/i2c: add MAX98396 driverEric Lai2022-08-174-0/+131
| | | | | | | | | | | | | Add MAX98396 support. BUG=b:232606045 TEST=build passed. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I835b51ea1fcc9363992d43a625f80cb545802fc6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66217 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* pciexp_device: Join pciexp_find_(next_)extended_cap() APIsNico Huber2022-08-171-1/+1
| | | | | | | | | | | | | | | Move the `offset` parameter into pciexp_find_extended_cap(). If it's called with `0`, we start a new search. If it's an existing offset, we continue the search. This makes it easier to search for multiple occurences of a capa- bility in a single loop. Change-Id: I80115372a82523b90460d97f0fd0fa565c3f56cb Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66453 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* drivers/nxp/uwb: Add new driver for NXP UWB SR1xx chipJack Rosenthal2022-08-144-0/+196
| | | | | | | | | | | | | | | | | | | | | Add a new driver for NXP UWB SR1xx (e.g., SR150) device. The driver was originally written by Tim Wawrzynczak as a WIP in CL:3503703, and was based on drivers/spi/acpi. BUG=b:240607130 BRANCH=firmware-brya-14505.B TEST=On ghost (with follow-up CL), patch linux with NXP's pending drivers -> UWB device is probed and can respond to a simple hello packet Co-authored-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Change-Id: I5b1b0a5c1b48d0b09e7ab5f2ea6b6bc2fba2a7d8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66466 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* payloads/tianocore: Rename TianoCore to edk2Sean Rhodes2022-08-138-10/+10
| | | | | | | | | | | | | | | | | | | | | | coreboot uses TianoCore interchangeably with EDK II, and whilst the meaning is generally clear, it's not the payload it uses. EDK II is commonly written as edk2. coreboot builds edk2 directly from the edk2 repository. Whilst it can build some components from edk2-platforms, the target is still edk2. [1] tianocore.org - "Welcome to TianoCore, the community supporting" [2] tianocore.org - "EDK II is a modern, feature-rich, cross-platform firmware development environment for the UEFI and UEFI Platform Initialization (PI) specifications." Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I4de125d92ae38ff8dfd0c4c06806c2d2921945ab Reviewed-on: https://review.coreboot.org/c/coreboot/+/65820 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* drivers: Add SPDX identifiers to files missing themMartin Roth2022-08-113-0/+6
| | | | | | | | | | | This adds SPDX identifiers to the remaining source files in the drivers directory that don't already have them. Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Change-Id: I97f96de857515214069c3b77f3c781f7f0555c6e Reviewed-on: https://review.coreboot.org/c/coreboot/+/66499 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* payloads/tianocore: Remove the option for CorebootPayloadPkgSean Rhodes2022-08-071-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | Recent changes to both coreboot and edk2 means that UefiPayloadPkg seems to work on all hardware. It has been tested on: * Intel Core 2nd, 3rd, 4th, 5th, 6th, 8th, 8th, 9th, 10th, 11th and 12th generation processors * Intel Small Core BYT, BSW, APL, GLK and GLK-R processors * AMD Stoney Ridge and Picasso This includes the problematic Lenovo X230s. The most likely fixes are: * Configuring the PCI Base and Length in edk2 * Fixes to the HostBridgeLib in edk2 * Adjustment to the SD/eMMC initialisation timeout This means we can now remove the already deprecated option for CorebootPayloadPkg and the legacy 8254 timer build option. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ice7b7576eb3d32ea46e5138266b7df3fbcdcf7ea Reviewed-on: https://review.coreboot.org/c/coreboot/+/65721 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
* drivers/i2c/dw_i2c: Re-add check for empty i2c transfer listNico Huber2022-08-031-1/+1
| | | | | | | | | | | | | The check was recently removed to allow callers to pass `count == 0`. Dereferencing the `msg` array is invalid in that case, though. Linux, where we borrowed the i2c interface from, also treats this with -EINVAL. Change-Id: I1eec02dd3a3fcf2d477a62cc65292fca40e469d3 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66341 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Tim Crawford <tcrawford@system76.com>
* drivers/elog: Use format stringMatei Dibu2022-08-011-1/+1
| | | | | | | | | | | | | | | | | | clang shows the warning below: src/drivers/elog/elog.c:171:13: error: format string is not a string literal (potentially insecure) [-Werror,-Wformat-security] elog_debug(msg); ^~~ Found-by: clang (13.0.1) Change-Id: I3f8949f9ce0c4ef4823530c61c503b0883bb5efc Signed-off-by: Matei Dibu <matdibu@protonmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66262 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
* drivers/wifi/generic: Revert changes to generate missing SSDT for PCIeReka Norman2022-07-272-28/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | wifi This reverts commit 5e6fd360de7fe92f1e8b1b3eb20241809e2a6aff. On nereid, the SSDT entry for the PCIe wifi device is missing, causing wake-on-WLAN not to work since the _PRW is missing. It seems like when commit 5e6fd360de changed the SSDT generation logic for CNVi and PCIe wifi, it broke the PCIe case. `wifi_pcie_ops` are never assigned to any device, so `parent && parent->ops == &wifi_pcie_ops` always returns false, and the `wifi_cnvi_ops` are used even for PCIe devices. Undo the changes in that CL. This allows both the CNVi and PCIe cases to work. That CL was meant to fix an issue with the CNVi _PRW containing garbage, but I can't reproduce this when the change is undone. It was also meant to fix the following error on CNVi devices, but I don't see any errors with this change: [ERROR] NONE missing set_resources BUB=b:233325709 TEST=On both nivviks (CNVi) and nereid (PCIe), check that the SSDT contains the correct wifi device entries (below), including a _PRW containing the correct GPE, and check that wake-on-WLAN works. nivviks: ``` Scope (\_SB.PCI0.CNVW) { Name (_PRW, Package (0x02) // _PRW: Power Resources for Wake { 0x6D, 0x03 }) Method (_DSM, 4, Serialized) // _DSM: Device-Specific Method { <snip> } } ``` nereid: ``` Device (\_SB.PCI0.RP01.WF00) { Name (_UID, 0x923ACF1C) // _UID: Unique ID Name (_DDN, "WIFI Device") // _DDN: DOS Device Name Name (_ADR, 0x0000000000000000) // _ADR: Address } Scope (\_SB.PCI0.RP01.WF00) { Name (_PRW, Package (0x02) // _PRW: Power Resources for Wake { 0x23, 0x03 }) Method (_DSM, 4, Serialized) // _DSM: Device-Specific Method { <snip> } } ``` Fixes: 5e6fd360de ("drivers/wifi/generic: Fix properties in generic-under-PCI device case") Change-Id: I100c5ee3842997c50444e5ce68d583834ed3a8ad Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66063 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* drivers/pci/generic: Add support for `_PRW`Robert Zieba2022-07-202-0/+5
| | | | | | | | | | | | | This commit adds support for `_PRW` in this driver. BUG=b:237682766 TEST=Built and booted on Skyrim device, dumped SSDT Change-Id: Ife4ba48994cbf993bc88df8354576336438e4258 Signed-off-by: Robert Zieba <robertzieba@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65799 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* drivers/pcie/generic: Add support for custom ACPI nameRobert Zieba2022-07-202-1/+7
| | | | | | | | | | | | | | This commit adds code to allow the driver to use an ACPI device name that is set in the device tree. BUG=b:237682766 TEST=Boot changes on Skyrim device, dumped SSDT Signed-off-by: Robert Zieba <robertzieba@google.com> Change-Id: Ie40a335e35b8ac83658e67d7cfba0750dd4784ad Reviewed-on: https://review.coreboot.org/c/coreboot/+/65798 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* drivers/pcie/generic: Clean up driverRobert Zieba2022-07-202-29/+7
| | | | | | | | | | | | | | | | | | This removes unneeded and unused functionality in the driver as part of an effort to make the driver more generic and useful. The things that have been removed are: `DmaProperty` and its associated `is_untrusted` config, `_DSD` generation, and the companion device functionality. This driver isn't currently used anywhere so there won't be any issues from removing the above functionality. BUG=b:237682766 TEST=Built and booted coreboot on Skyrim device Change-Id: I0abd9148ab66ea9426069102ecc8c2fa77fea98e Signed-off-by: Robert Zieba <robertzieba@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65797 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* drivers/amd/agesa: Fix some white spaces issuesElyes Haouas2022-07-176-44/+44
| | | | | | | | Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I0a11d303d2e2c83cb72773656f5caedec666dc66 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65898 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* src/drivers/intel/i210: Remove unuseful 'return' in void functionElyes HAOUAS2022-07-171-1/+0
| | | | | | | | Change-Id: Id33ef66e7388df2173ee8888265ed4379f05a93e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61548 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* drivers: Get rid of unnecessary blank lines {before,after} braceElyes HAOUAS2022-07-1722-29/+1
| | | | | | | | Change-Id: Ic1b38e93d919c1286a8d130700a4a2bfd6b55258 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61557 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* drivers/intel/dptf: Correct UID for TBAT deviceVarshit B Pandya2022-07-161-1/+1
| | | | | | | | | | | | | | | | | | | | As per Intel Dynamic Tuning Spec revision 1.3.13, section 14.1.2 TBAT _UID should match the _UID implemented for battery device ACPI object for OS _UID for TBAT is currently set to "TBAT" but should be 1. Battery device is define at src/ec/google/chromeec/acpi/battery.asl Setting _UID to 1 because right now ChromeOS is the only user of DPTF driver TEST: Build and boot brya0 Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com> Change-Id: I1e4474e59cf01f937fbd51e5b674a609f0c47625 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65605 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* driver/wifi: Remove unused function wifi_emit_dsmVarshit B Pandya2022-07-161-23/+0
| | | | | | | | | | | | | As part of this CL https://review.coreboot.org/c/coreboot/+/61020 this function was decoupled and support for new DSM was added. This function is no longer used so remove it. Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com> Change-Id: Iad9dca8e50bad87178dfcc1951276703721d5f60 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65850 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Meera Ravindranath <meera.ravindranath@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* arch/x86: Mark prepare_and_run_postcar noreturnArthur Heymans2022-07-141-1/+0
| | | | | | | | | | | This moves the die() statement to a common place. Change-Id: I24c9f00bfee169b4ca57b469c089188ec62ddada Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65812 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Julius Werner <jwerner@chromium.org>
* commonlib: Substitude macro "__unused" in compiler.hBill XIE2022-07-142-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | Since there are many identifiers whose name contain "__unused" in headers of musl libc, introducing a macro which expands "__unused" to the source of a util may have disastrous effect during its compiling under a musl-based platform. However, it is hard to detect musl at build time as musl is notorious for having explicitly been refusing to add a macro like "__MUSL__" to announce its own presence. Using __always_unused and __maybe_unused for everything may be a good idea. This is how it works in the Linux kernel, so that would at least make us match some other standard rather than doing our own thing (especially since the other compiler.h shorthand macros are also inspired by Linux). Signed-off-by: Bill XIE <persmule@hardenedlinux.org> Change-Id: I547ae3371d7568f5aed732ceefe0130a339716a9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65717 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Julius Werner <jwerner@chromium.org>
* */fsp/exit_car: Push stack address into %espArthur Heymans2022-07-091-1/+1
| | | | | | | | | | | | | | | | | | | | | | | Fixes: 5315e96abf ("arch/x86/postcar: Use a separate stack for C execution") Resolves: https://mail.coreboot.org/hyperkitty/list/coreboot@coreboot.org/ thread/TGIWAKZKELJRAEMKJNYRJ55MX2CXYNCV/ Link: https://mail.coreboot.org/hyperkitty/list/coreboot@coreboot.org/ thread/2JC3GNJSGXUD6DRVUY7O2O3W6OM3E2MY/ 5315e96abf broke platforms using FSP-M to tear down CAR. It was pushing the value at '_estack' into %esp rather than the address '_estack'. Change-Id: Ie1fc70bd60fe3a2519ffb71625a35630fa732ff6 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65716 Reviewed-by: Patrick Georgi <patrick@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* treewide: Unify Google brandingJon Murphy2022-07-042-2/+2
| | | | | | | | | | | | | | | | | Branding changes to unify and update Chrome OS to ChromeOS (removing the space). This CL also includes changing Chromium OS to ChromiumOS as well. BUG=None TEST=N/A Change-Id: I39af9f1069b62747dbfeebdd62d85fabfa655dcd Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65479 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* src/driver/intel/mipi_camera: Update ACPI entry to provide silicon infozhixingma2022-07-041-1/+3
| | | | | | | | | | | | | | CPUID_RAPTORLAKE_P_Q0 is ES. Add it to generate is_es = 1 in ACPI BUG=b:229134437 BRANCH=firmware-brya-14505.B TEST=Booted to OS on adlrvp + rpl silicon Signed-off-by: zhixingma <zhixing.ma@intel.com> Change-Id: I67d70dc7e916a4818869aef86e7e642b66ea5dae Reviewed-on: https://review.coreboot.org/c/coreboot/+/65118 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
* drivers/mrc_cache: Do not verify TPM MRC hash if secdata is mockedMichał Żygowski2022-06-241-1/+1
| | | | | | | | | | | | | | | | | | | Having PTT means mocking secdata, so saving/reading the hash always succeeds, but there is no data stored/read from/to TPM. The code comparing MRC hashes did not care if secdata mocking was enabled and failed during hash comparison with invalid data. This broke the fastboot even if the MRC cache data was filled and correctly checksummed. If mocking is enabled simply fallback to checksum computing to proceed with fastboot. TEST=Boot MSI PRO Z690-A WIFI DDR4 in fastboot mode with PTT and vboot enabled. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Ic0cf04b129fe1c5e94cd8a803bb21aa350c3f8da Reviewed-on: https://review.coreboot.org/c/coreboot/+/64221 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* drivers/crb: Generate TPM PPI ACPI codeMichał Żygowski2022-06-231-0/+4
| | | | | | | | | | | | The TPM PPI code was only generated for memory mapped non-CRB TPMs. There is no reason why CRB TPM should not have the PPI, e.g. PTT. Call the relevant method to add the PPI to SSDT. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I3d3f08ea686c95ef75ae8fe7a5dcf16f7492ce68 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64422 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
* device/resource: Add _kb postfix for resource allocatorsKyösti Mälkki2022-06-222-2/+2
| | | | | | | | | | | | There is a lot of going back-and-forth with the KiB arguments, start the work to migrate away from this. Change-Id: I329864d36137e9a99b5640f4f504c45a02060a40 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64658 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* drivers/usb/gadget.c: Use 'printk()' instead of 'dprintk()'Elyes HAOUAS2022-06-201-20/+18
| | | | | | | | | | | dprintk(BIOS_,...) was probably useed for debug print, so use printk(BIOS_, ...) instead. Change-Id: Ia4171c8b4b42f6b0c1c9c0438bab2eef73f8c416 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61405 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
* drivers/intel/gma/acpi: Replace LNotEqual(a,b) with ASL 2.0 syntaxFelix Singer2022-06-091-2/+2
| | | | | | | | | | Replace `LNotEqual(a, b)` with `a != b`. Change-Id: Ib1b3f85f95511e903948b385e86e5102d5b43add Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60698 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
* drivers/intel/gma/acpi: Replace LGreater(a,b) with ASL 2.0 syntaxFelix Singer2022-06-091-2/+2
| | | | | | | | | | Replace `LGreater(a, b)` with `a > b`. Change-Id: I56479726f91f33e1d3062a31f1efb82c0814316c Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60681 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
* drivers/intel/gma/acpi: Replace LLess(a,b) with ASL 2.0 syntaxFelix Singer2022-06-091-3/+3
| | | | | | | | | | Replace `LLess(a, b)` with `a < b`. Change-Id: I043ffad90737f4217d01c49e03af81549a0ffb1b Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60677 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
* drivers/intel/gma/acpi: Replace LEqual(a,b) with ASL 2.0 syntaxFelix Singer2022-06-092-7/+7
| | | | | | | | | | Replace `LEqual(a, b)` with `a == b`. Change-Id: I965a0718f6bca1dc27b928bdd9374857f5ea3215 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60660 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
* drivers/tpm/cr50: Add TPM IRQ timeout Kconfig optionYu-Ping Wu2022-06-084-38/+29
| | | | | | | | | | | | | | | | | | | | | | | The current 10ms timeout for SPI TPM IRQ is not enough for platforms using ti50 (such as corsola). Therefore, introduce a new Kconfig option 'GOOGLE_TPM_IRQ_TIMEOUT_MS'. For platforms using cr50, we need to support legacy pre-ready-IRQ cr50 factory images during the initial boot, so the timeout remains 100ms for I2C TPM and 10ms for SPI TPM. For all the other platforms using ti50, the default timeout is increased to 750ms, as suggested by the ti50 team (apronin@google.com). BUG=b:232327704 TEST=emerge-corsola coreboot BRANCH=none Change-Id: I8dbb919e4a421a99a994913613a33738a49f5956 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64412 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-20 02:36:13 +0000