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* ec/google/chromeec: Add is_battery_present_and_above_critical_thresholdJamie Ryu2023-10-161-0/+8
| | | | | | | | | | | | | | | This adds is_battery_present_and_above_critical_threshold to check the battery is present and the battery level is above critical level. BUG=b:296952944 TEST=Build rex and check is_battery_present_and_above_critical_threshold returns the correct battery status. Change-Id: Ib38be55bc42559bab4f12d5e8580ddc3e1a6acc1 Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78321 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
* vc/google/chromeos: Move clear_ec_ap_idle() to common codeDerek Huang2023-09-141-0/+5
| | | | | | | | | | | | | | | | Previously the clear_ec_ap_idle() is implemented in cr50_enable_update.c and be called in the file. Move it to common code so that it can be called in cse_board_reset.c TEST=emerge-brask coreboot Change-Id: I2dbe41b01e70f7259f75d967e6df694a3e0fac23 Signed-off-by: Derek Huang <derekhuang@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77631 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Reka Norman <rekanorman@chromium.org>
* ec/google/chromeec: Split wait-loop for DP and HPD flagsKapil Porwal2023-07-151-1/+5
| | | | | | | | | | | | | | | | | Split wait-loop for DP and HPD flags as below - - google_chromeec_wait_for_hpd - google_chromeec_wait_for_dp_mode_entry BUG=b:247670186 TEST=Verify display over TCSS and its impact on boot time for google/rex Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I3e565d6134f6433930916071e94d56d92dc6cb06 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76370 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* ec/google/chromeec: Deprecate dev_index from google_chromeec_rebootCaveh Jalali2022-11-121-1/+1
| | | | | | | | | | | | | | | This removes the dev_index argument from the google_chromeec_reboot API. It's always set to 0, so don't bother passing it. BUG=b:258126464 BRANCH=none TEST=none Change-Id: Iadc3d7c6c1e048e4b1ab8f8cec3cb8eb8db38e6a Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69373 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* ec/google/chromeec: Remove google_chromeec_vbnv_context()Yu-Ping Wu2022-06-241-1/+0
| | | | | | | | | | | | | | With CB:65012, google_chromeec_vbnv_context() is no longer used. Remove it from the codebase. BUG=b:178689388 TEST=./util/abuild/abuild -t GOOGLE_STOUT -a -x Change-Id: I717f600f0f73c3ca932b6a442a9d5b90c35c8f3b Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65326 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* ec/google/chromeec: Update google_chromeec_usb_pd_get_info()Derek Huang2021-10-061-3/+0
| | | | | | | | | | | | | | google_chromeec_usb_pd_get_info() is used in ec.c only. Make it static and drop from ec.h. BUG=b:192947843 Signed-off-by: Derek Huang <derek.huang@intel.corp-partner.google.com> Change-Id: I4b3df4223d5c26ea1c1a52b26f7d49fa4c947de8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58060 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
* ec/google/chromeec: Add new API for USB-C mux handlingDerek Huang2021-10-061-0/+8
| | | | | | | | | | | | | Add google_chromeec_get_usbc_mux_info() to obtain USB-C mux related information. BUG=b:192947843 Signed-off-by: Derek Huang <derek.huang@intel.corp-partner.google.com> Change-Id: Idc27f23214c2d5b91334ae3efe248100329964ba Reviewed-on: https://review.coreboot.org/c/coreboot/+/58059 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
* ec/google/chromeec: Add APIs for USB-C DP ALT modeDerek Huang2021-10-061-0/+8
| | | | | | | | | | | | | | | | | | Add API to allow AP to send the command to EC to enter DP ALT mode and API to wait for DP HPD event. BUG=b:192947843 TEST=select ENABLE_TCSS_DISPLAY_DETECTION in Kconfig.name. Build coreboot and update your system. Boot the system you will find below message in the coreboot log with or without USB-C display connected: 'HPD ready after %lu ms' or 'HPD not ready after %ldms. Abort.'. Signed-off-by: Derek Huang <derek.huang@intel.corp-partner.google.com> Change-Id: Id11510c1ff58579ae2cddfe5a4d69646fd84f5c3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57138 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
* ec/google/chromeec: Update some PD and DisplayPort APIsDerek Huang2021-10-061-2/+5
| | | | | | | | | | | | | | | | 1. Update google_chromeec_pd_get_amode() to return bitmask. 2. Update google_chromeec_wait_for_displayport() to handle the updated return value of google_chromeec_pd_get_amode(). 3. Drop google_chromeec_pd_get_amode() from ec.h and make it static because it's not used outside of ec.c. BUG=b:192947843 Signed-off-by: Derek Huang <derek.huang@intel.corp-partner.google.com> Change-Id: I6020c4305e30018d4c97d862c16e8d642c951765 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58058 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
* ec/google/chromeec: Update google_chromeec_usb_pd_control()Derek Huang2021-10-061-2/+2
| | | | | | | | | | | | | | | Add parameter `active_cable` to obtain the cable type (active or passive) which is needed for USB-C configuration for some SoCs (at least Intel TGL and ADL), change the function name to google_chromeec_usb_pd_get_info() for better understanding. BUG=b:192947843 Signed-off-by: Derek Huang <derek.huang@intel.corp-partner.google.com> Change-Id: Ie91a3096d49d5dde75e60ab0f2f38152cef720f6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58057 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
* src/acpi to src/lib: Fix spelling errorsMartin Roth2021-10-051-2/+2
| | | | | | | | | | | | These issues were found and fixed by codespell, a useful tool for finding spelling errors. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I5b8ecdfe75d99028fee820a2034466a8ad1c5e63 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58080 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* ec/google: Use EC_HOST_EVENT_NONERob Barnes2021-06-301-1/+1
| | | | | | | | | | | | | | google_chromeec_get_event returns 0 for no event. Return EC_HOST_EVENT_NONE=0 to improve readability. BUG=b:184074997 TEST=Build and boot guybrush without error Signed-off-by: Rob Barnes <robbarnes@google.com> Change-Id: Ic08ed9ccdd7c0023d0fe8b641fcf60dca495a242 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55547 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* ec/google/chromeec/ec.h: Remove repeated wordElyes HAOUAS2021-01-181-2/+2
| | | | | | | | Change-Id: I7f567f2b4c582e4b2bb102ef0e0f68c5bf6cfb9e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49515 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
* ec/google/chromeec: add SSFC CBI supportMarco Chen2021-01-081-0/+1
| | | | | | | | | | | | | | | An API is added to get SSFC value from cros EC. BUG=b:174118027 BRANCH=octopus TEST=check SSFC value from EC is correct compared to value in CBI Change-Id: Ifd521514bbc2e90c789f3760b72e8326e614e2b1 Signed-off-by: Marco Chen <marcochen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48791 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jett Rink <jettrink@google.com> Reviewed-by: Zhuohao Lee <zhuohao@chromium.org>
* ec/google/chromeec: Add more wrappers for regulator controlYidi Lin2020-11-181-0/+20
| | | | | | | | | | | | | | | | google_chromeec_regulator_enable is for enabling/disabling the regulator. google_chromeec_regulator_is_enabled is for querying if the regulator is enabled. BUG=b:168863056,b:147789962 BRANCH=none TEST=emerge-asurada coreboot Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Change-Id: Ia804242042b0026af19025a0c4a74b3ab8475dab Reviewed-on: https://review.coreboot.org/c/coreboot/+/46686 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* fw_config: Convert fw_config to a 64-bit fieldTim Wawrzynczak2020-10-301-1/+1
| | | | | | | | | | | | | | | | | We all knew this was coming, 32 bits is never enough. Doing this early so that it doesn't affect too much code yet. Take care of every usage of fw_config throughout the codebase so the conversion is all done at once. BUG=b:169668368 TEST=Hacked up this code to OR 0x1_000_0000 with CBI-sourced FW_CONFIG and verify the console print contained that bit. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I6f2065d347eafa0ef7b346caeabdc3b626402092 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45939 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* ec/google/chromeec: Add wrappers to get/set the voltageYidi Lin2020-10-201-0/+18
| | | | | | | | | | | | | | Add APIs to get and set the voltage for the target regulator. BUG=b:147789962 BRANCH=none TEST=emerge-asurada coreboot Change-Id: I0e56df45fc3309c387b9949534334eadefb616b2 Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46404 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* src/ec/google/chromeec: Get Type-C Mux info from EC (TCPM)Divya Sasidharan2020-10-141-1/+10
| | | | | | | | | | | | | | | | | | EC being the TCPM decides the mux configuration after negotiating with the port partner on the Type-C port. The APIs added here will give the current essential mux state information for a given port. BUG=None BRANCH=None TEST=Built coreboot image and verified that using this patch mux is being set for display during boot Change-Id: If994a459288ef31b0e6da8c6cdfd0ce3a0303981 Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com> Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42078 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* ec/google/chromeec: Add helper to request AP resetKarthikeyan Ramasubramanian2020-08-141-0/+7
| | | | | | | | | | | | | | | | | | | | Add a helper function to initiate AP reset through Embedded Controller (EC). BUG=b:162290856 TEST=Ensure that the EC resets AP on boards where the command is supported. Change-Id: I01d7dfec72a8a3f6d2c4844bc062672e494860d8 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44188 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* treewide: Remove "this file is part of" linesPatrick Georgi2020-05-111-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Stefan thinks they don't add value. Command used: sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool) The exceptions are for: - crossgcc (patch file) - gcov (imported from gcc) - elf.h (imported from GNU's libc) - nvramtool (more complicated header) The removed lines are: - fmt.Fprintln(f, "/* This file is part of the coreboot project. */") -# This file is part of a set of unofficial pre-commit hooks available -/* This file is part of coreboot */ -# This file is part of msrtool. -/* This file is part of msrtool. */ - * This file is part of ncurses, designed to be appended after curses.h.in -/* This file is part of pgtblgen. */ - * This file is part of the coreboot project. - /* This file is part of the coreboot project. */ -# This file is part of the coreboot project. -# This file is part of the coreboot project. -## This file is part of the coreboot project. --- This file is part of the coreboot project. -/* This file is part of the coreboot project */ -/* This file is part of the coreboot project. */ -;## This file is part of the coreboot project. -# This file is part of the coreboot project. It originated in the - * This file is part of the coreinfo project. -## This file is part of the coreinfo project. - * This file is part of the depthcharge project. -/* This file is part of the depthcharge project. */ -/* This file is part of the ectool project. */ - * This file is part of the GNU C Library. - * This file is part of the libpayload project. -## This file is part of the libpayload project. -/* This file is part of the Linux kernel. */ -## This file is part of the superiotool project. -/* This file is part of the superiotool project */ -/* This file is part of uio_usbdebug */ Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* device: Constify struct device * parameter to acpi_fill_ssdt()Furquan Shaikh2020-04-281-1/+1
| | | | | | | | | | | | | | .acpi_fill_ssdt() does not need to modify the device structure. This change makes the struct device * parameter to acpi_fill_ssdt() as const. Change-Id: I110f4c67c3b6671c9ac0a82e02609902a8ee5d5c Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40710 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* google/chromeec: Add wrapper for EC_CMD_GET_KEYBD_CONFIGRajat Jain2020-04-201-0/+8
| | | | | | | | | | Add a wrapper command for the subject command Signed-off-by: Rajat Jain <rajatja@google.com> Change-Id: I29a4021c2ea0d1cbb4a72f56bf2232d8f9c80ac3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40313 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* google/chromeec: Revise parameters of EC USB PD API callGaggery Tsai2020-04-201-2/+3
| | | | | | | | | | | | | | | | | This patch adds voltage and curent parameters in google_chromeec_get_usb_pd_power_info and remove power parameter. Caller could use the voltage and current information to calculate charger power rating. The reason for this change is, some applications need the voltage information to calculate correct system power eg PsysPmax. BUG=b:151972149 TEST=emerge-puff coreboot; emerge-fizz coreboot Change-Id: I11efe6f45f2f929fcb2763d192268e677d7426cb Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39849 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* ec/google/chromeec: add BOARD_VERSION CBI supportAaron Durbin2020-04-161-0/+3
| | | | | | | | | | | | | Obtaining the CBI_TAG_BOARD_VERSION value wasn't in the code base. Add the binding for it so it can be used. BUG=b:153640981 Change-Id: Ie2f289631f908014432596448e56b5048a196a10 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40355 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
* ec/google/chromeec: expose failure and unprovisioned SKU id valuesAaron Durbin2020-04-111-0/+3
| | | | | | | | | | | | | | Provide CROS_SKU_UNKNOWN and CROS_SKU_UNPROVISIONED defintion so callers can utilize the default and failing value without open coding it. BUG=b:153642124 Change-Id: I447004e9016b6ab3306ea532721494ebbcda741d Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40299 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* ec/google/chromeec: Replace uses of ec_current_image with ec_imageFurquan Shaikh2020-04-091-1/+1
| | | | | | | | | | | | | | | | This change replaces all uses of ec_current_image with ec_image since Chromium OS EC has deprecated (sha 78d1ed61d) the use of enum ec_current_image and instead changed it to enum ec_image. BUG=b:149987779 Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I7e45ea6c736b44040561f0f8a80f817ade8db864 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40267 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* src/ec: Use SPDX for GPL-2.0-only filesAngel Pons2020-04-051-12/+3
| | | | | | | | | | Done with sed and God Lines. Only done for C-like code for now. Change-Id: I422d072a9ab3350e364004ba34911cd183fc6612 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40052 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* src (minus soc and mainboard): Remove copyright noticesPatrick Georgi2020-03-171-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | They're listed in AUTHORS and often incorrect anyway, for example: - What's a "Copyright $year-present"? - Which incarnation of Google (Inc, LLC, ...) is the current copyright holder? - People sometimes have their editor auto-add themselves to files even though they only deleted stuff - Or they let the editor automatically update the copyright year, because why not? - Who is the copyright holder "The coreboot project Authors"? - Or "Generated Code"? Sidestep all these issues by simply not putting these notices in individual files, let's list all copyright holders in AUTHORS instead and use the git history to deal with the rest. Change-Id: I89b10076e0f4a4b3acd59160fb7abe349b228321 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39611 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* ec/google/chromeec: Fix dev ops for chromeecFurquan Shaikh2020-03-061-5/+0
| | | | | | | | | | | | | | | | | | CB:38541 ("ec/google/chromeec: Add SSDT generator for ChromeOS EC") added a new device_operations structure for chromeec for handling ACPI SSDT generation. However, this resulted in the original device_operations which handled lpc read resources to be skipped. This change fixes the above regression by combining the device operations for reading resources and ACPI SSDT generation into a single structure and retains the old logic for enabling of pnp devices. Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I3a242f4b15603f957e0e81d121e5766fccf3c28d Reviewed-on: https://review.coreboot.org/c/coreboot/+/39321 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
* ec/google/chromeec: Introduce SKU_ID helpersEdward O'Callaghan2020-02-281-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The following introduces helpers that, by default, accommodate a larger SKU id space. The following is the rational for that: Allow INT32_MAX SKU id encodings beyond UINT8_MAX. This allows for the SKU id to accommodate up to 4 bytes however we reserve the highest bit for SKU_UNKNOWN to be encoded. However, the legacy UINT8_MAX encoding is supported by leveraging the Kconfig by overriding it with the legacy max of 0xff. Follow ups migrate boards to this common framework. V.2: Fixup array size && drop sku_id SKU_UNKNOWN check and pass whatever is set to userspace as firmware doesn't care about the value. V.3: Use SPDX-License header. BUG=b:149348474 BRANCH=none TEST=tested on hatch. Change-Id: I805b25465a3b4ee3dc0cbda5feb9e9ea2493ff9e Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39018 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
* ec/google/chromeec: Add SSDT generator for ChromeOS ECTim Wawrzynczak2020-02-181-0/+23
| | | | | | | | | | | | | | | | | | | | | | Upcoming patches for the Linux kernel (5.6 ?) would like to consume information about the USB PD ports that are attached to the device. This information is obtained from the CrOS EC and exposed in the SSDT ACPI table. Also, the device enable for this PCI device is moved from ec_lpc.c to a new file, ec_chip.c, where EC-related ACPI methods can live. It still allows other code to call functions on device enable (so that PnP enable for the LPC device still gets called). BUG=b:146506369 BRANCH=none TEST=Verify the SSDT contains the expected information Change-Id: I729caecd64d9320fb02c0404c8315122f010970b Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38541 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
* ec/google/chromeec: Add new wrappers for host commandsTim Wawrzynczak2020-02-011-0/+30
| | | | | | | | | | | | | | | | Add new functions to get (from the EC): 1) The number of USB-PD ports 2) The capabilities of each port (EC_CMD_GET_PD_PORT_CAPS) BUG=b:146506369 BRANCH=none TEST=Instrumented calls to these and verified the data Change-Id: I57edbe1592cd28b005f01679ef8a8b5de3e1f586 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38540 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
* ec/google/chromeec: add support for fw_config cbi fieldJett Rink2020-01-221-2/+3
| | | | | | | | | | | | | | | The firmware configuration (fw_config) field is store in the CBI EEPROM and it should be used to make firmware customization instead of sku/variant id. BUG=b:145519081 TEST=builds Change-Id: I790998a29e724ecdff8876cca072267537b7cea6 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38410 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* include: Make stdbool.h a separate fileJulius Werner2019-11-181-2/+1
| | | | | | | | | | | | | | This patch moves the traditional POSIX stdbool.h definitions out from stdint.h into their own file. This helps for using these definitions in commonlib code which may be compiled in different environments. For coreboot everything should chain-include this stuff via types.h anyway so nothing should change. Change-Id: Ic8d52be80b64d8e9564f3aee8975cb25e4c187f5 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36837 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* ec/google/chromeec: Add EC driver support for software syncTim Wawrzynczak2019-10-311-0/+121
| | | | | | | | | | | | | | | | | | Quite a few new functions added here in order to support the use-case of performing EC software sync within coreboot. Most of these functions are related to retrieving the EC's hash, and writing a new image into the EC's flash. BUG=b:112198832 BRANCH=none TEST=With whole patch series, successfully performed EC software sync Change-Id: I0d3c5184dbe96f04b92878f2c19c7875503a910a Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36207 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* ec/google/chromeec: Clean up ec.[ch]Tim Wawrzynczak2019-10-291-9/+9
| | | | | | | | | | | | | | | | | | | Change all uN integral types to uintN_t. Make the names of host command params/responses consistent. Use static struct initialization to ensure all fields are initialized. BUG=none BRANCH=none TEST=compiles Change-Id: Ibe1e29e88975c85eea215adedc5f5e483243e0d6 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36340 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Joel Kitching <kitching@google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* google/chromeos: Support AP watchdog flag from Chrome ECYou-Cheng Syu2019-08-231-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | After ChromiumOS CL:1293132 and CL:1295890, Chrome EC can store the flag telling if the last reboot was triggered by AP watchdog for some boards (e.g., Kukui). This CL adds a new function google_chromeec_get_ap_watchdog_flag(), which reads the AP watchdog flag from Chrome EC, and updates the tables of reset causes and reset flags. A new Kconfig option CHROMEOS_USE_EC_WATCHDOG_FLAG is added for elog_handle_watchdog_tombstone() to determine if watchdog reset was triggered by the AP watchdog flag from EC instead of the tombstone in AP. BUG=b:109900671,b:118654976 BRANCH=none TEST=test with https://review.coreboot.org/c/coreboot/+/31843 Change-Id: I7a970666a8c6da32ac1c6af8280e808fe7fc106d Signed-off-by: You-Cheng Syu <youcheng@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31834 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
* ec/google/chromeec: Update ec_commands.hYou-Cheng Syu2019-08-231-7/+0
| | | | | | | | | | | | | | | | | | | | | Copy ec_commands.h directly from ChromiumOS EC repository (CL:1520574). Since ec_commands.h already defines usb_charge_mode and only USB_CHARGE_MODE_DISABLED is used in coreboot, enum usb_charge_mode is removed from ec.h. To avoid redefinition of the BIT macro, #ifndef check is added to include/types.h. BUG=b:109900671,b:118654976 BRANCH=none TEST=emerge-kukui -j coreboot Change-Id: I7ed5344fc8923e45e17c3e2a34371db6f80b079d Signed-off-by: You-Cheng Syu <youcheng@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31885 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* ec/google/chromeec: Clarify return value of google_chromeec_commandDaisuke Nojiri2019-02-261-0/+6
| | | | | | | | | | | | | | | | | | | | | | This patch clarifies the definition of google_chromeec_command. Currently absence of the definition isn't causing any problem because wrapper APIs check 'ret != 0' or wrapper APIs check 'ret < 0' for an interface which returns only negative error codes. However, there is a chance that a new wrapper API will be addedl which check 'ret < 0' to catch errors, assuming other interfaces behave the same. Or existing wrapper APIs will be broken as soon as they're compiled for another interface. BUG=chromium:935038 TEST=none Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Change-Id: I2ce7109b5f2a1d5294f167719730bc1f039ba03f Reviewed-on: https://review.coreboot.org/c/31613 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* ec/google/chromeec: add support for retrieving OEM nameWisley Chen2018-11-161-0/+1
| | | | | | | | | | | | | | | OEM name can be stored in CBI. This change can support for fetching the OEM name from CBI. BUG=b:118798180 TEST=Verified to get data from CBI Change-Id: I4938c4d60fcad9e1f43ef69cc4441d1653de7e24 Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/29497 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* ec/google/chromeec: Use common MEC interfaceDuncan Laurie2018-10-181-3/+0
| | | | | | | | | | | | | | | Switch to using the common MEC interface instead of the Chrome EC specific code. Tested on a Chell chromebook that has a MEC based Chrome EC to ensure that the EC interface is still functional. Change-Id: Idf26e62c2843993c2df2ab8ef157b263a71a97c9 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/29112 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* ec/google/chromeec: Update google_chromeec_get_board_version prototypeKarthikeyan Ramasubramanian2018-09-201-1/+10
| | | | | | | | | | | | | | | | The helper function to get the board version from EC returns 0 on failure. But 0 is also a valid board version. Update the helper function to return -1 on failure and update the use-cases. BUG=b:114001972,b:114677884,b:114677887 Change-Id: I93e8dbce2ff26e76504b132055985f53cbf07d31 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Tested-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/28576 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Jett Rink <jettrink@google.com>
* ec/google/chromeec: add support for retrieving DRAM part numberAaron Durbin2018-08-081-0/+1
| | | | | | | | | | | | | | | The DRAM part number can be stored in the CBI data. Therefore, add support for fetching the DRAM part number from CBI. BUG=b:112203105 TEST=Fetched data from CBI on phaser during testing. Change-Id: Ia721c01aab5848ff36e11792adf9c494aa25c01d Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/27945 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
* ec/google/chromeec: Initialize SMI mask in google_chromeec_events_initFurquan Shaikh2018-06-011-0/+1
| | | | | | | | | | | | | This change adds smi_events to google_chromeec_event_info and allows mainboards to set SMI mask if current boot type is not S3 wakeup. Change-Id: I899a6af6e57d295b4eac2039c8245ebcc73a42bb Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/26709 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* mainboard/google/fizz: Check HDMI HPD and DisplayPort HPDDaisuke Nojiri2018-03-061-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some type-c monitors do not immediately assert HPD. If we continue to boot without HPD asserted, Depthcharge fails to show pictures on a monitor even if HPD is asserted later. Also, if an HDMI monitor is connected, no wait is needed. If only an HDMI monitor is connected, currently the API always loops until the stopwatch expires. This patch will make the AP skip DisplayPort wait loop if it detects an HDMI monitor. And if an HDMI monitor is not detected, the AP will wait for DisplayPort mode (like before) but also its HPD signal. This patch also extends the wait loop time-out to 3 seconds. BUG=b:72387533 BRANCH=none TEST=Verify firmware screen is displayed even when a type-c monitor does not immediately assert HPD. Verify if HDMI monitor is connected, AP does not wait (and firmware screen is displayed on HDMI monitor). Change-Id: I0e1afdffbebf4caf35bbb792e7f4637fae89fa49 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://review.coreboot.org/23816 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
* chromeec: Add google_chromeec_wait_for_displayDaisuke Nojiri2018-02-171-0/+1
| | | | | | | | | | | | | | | | The google_chromeec_wait_for_display API checks whether a display is ready or not. It waits in a loop until EC says it entered DisplayPort alternative mode or times out in 2 seconds. BUG=b:72387533 BRANCH=none TEST=See 23746 "mb/google/fizz: Wait until display is ready" Change-Id: Ieee5db77bd6e147936ea8fc735dcbeffec98c0f8 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://review.coreboot.org/23745 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* chromeec: Add google_chromeec_pd_get_amodeDaisuke Nojiri2018-02-171-0/+1
| | | | | | | | | | | | | | | | The google_chromeec_pd_get_amode API checks whether TCPM is in a specified alternate mode or not. BUG=b:72387533 BRANCH=none TEST=See 23746 "mb/google/fizz: Wait until display is ready" Change-Id: Ib9b4ad06b61326fa167c77758603e038d817f928 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://review.coreboot.org/23744 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
* ec/google: Get OEM ID and SKU ID from ECDaisuke Nojiri2018-02-051-0/+9
| | | | | | | | | | | | | | | | | This patch adds EC_CMD_GET_CROS_BOARD_INFO and two APIs to fetch OEM ID and SKU ID from cros EC. CBI abbreviates Cros Board Info. BUG=b:70294260 BRANCH=none TEST=Verify AP log shows expected OEM ID and SKU ID on Fizz. Change-Id: Iff69a2dc0e562d87dd287f79c407f23aeb09fb9e Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://review.coreboot.org/23549 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* google/chromeec: Enable unified host event programming interfaceJenny TC2018-01-171-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Unified Host Event Programming Interface (UHEPI) enables a unified host command EC_CMD_PROGRAM_HOST_EVENT to set/get/clear different host events. Old host event commands (0x87, 0x88, 0x89, 0x8A, 0x8B, 0x8C, 0x8D, 0x8E, 0x8F) is supported for backward compatibility. But newer version of BIOS/OS is expected to use UHEPI command (EC_CMD_PROGRAM_HOST_EVENT) The UHEPI also enables the active and lazy wake masks. Active wake mask is the mask that is programmed in the LPC driver (i.e. the mask that is actively used by LPC driver for waking the host during suspended state). It is same as the current wake mask that is set by the smihandler on host just before entering sleep state S3/S5. On the other hand, lazy wake masks are per-sleep masks (S0ix, S3, S5) so that they can be used by EC to set the active wake mask depending upon the type of sleep that the host has entered. This allows the host BIOS to perform one-time programming of the wake masks for each supported sleep type and then EC can take care of appropriately setting the active mask when host enters a particular sleep state. BRANCH=none BUG=b:63969337 TEST=verify masks with ec hostevent command on S0,S3,S5 and S0ix 1). Verified wake masks with ec hostevent command on S0,S3,S5 and S0ix 2). suspend_stress_test with S3 and S0ix 3). Verified "mosys eventlog list" in S3 and s0ix resume to confirm wake sources (Lid, power buttton and Mode change) 4). Verified "mosys eventlog list" in S5 resume to confirm wake sources (Power Button) 5). Verified above scenarios with combination of Old BIOS + New EC and New BIOS + Old EC Change-Id: I4917a222c79b6aaecb71d7704ffde57bf3bc99d9 Signed-off-by: Jenny TC <jenny.tc@intel.com> Reviewed-on: https://review.coreboot.org/21085 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
* chromeec: Add command to override charger limitDaisuke Nojiri2017-12-081-0/+10
| | | | | | | | | | | | | | | | | This patch adds EC_CMD_OVERRIDE_DEDICATED_CHARGER_LIMIT, which overrides the max input current and voltage when a barrel jack adapter supplies power. BUG=b:64442692 BRANCH=none TEST=Boot Fizz. Use chgsup console command to verify the max current and voltage are set as expected. Change-Id: I8c6fc54e519ce13e3db82ee2cecaa96c6eb42d8a Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://review.coreboot.org/22624 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-09-10 09:46:44 +0000