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* arch/io.h: Add missing includesKyösti Mälkki2019-03-041-0/+1
| | | | | | | | | | Fixes indirect includes that would break with followup work. Change-Id: I37ca01b904a0b422a4d09475377e755e167a6ab3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31697 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* cpu/x86/mtrr: Fix _FROM_4G_TOP() macroNico Huber2019-02-121-1/+1
| | | | | | | | | | | | | | | This macro was unnecessarily complex. Trying to avoid an overflow for unknown reasons, and instead shifted the result into the sign bit in C. Using a plain number literal that forces C to use an adequate integer type seems to be safe. We start with 0xffffffff, subtract `x` and add 1 again. Turned out to be a common pattern and can't overflow for any positive 32-bit `x`. Change-Id: Ibb0c5b88a6e42d3ef2990196a5b99ace90ea8ee8 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/31322 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
* Revert "cpu/x86/mtrr: Fix sign overflow"Nico Huber2019-02-111-1/+1
| | | | | | | | | | | | | | | | This reverts commit 6bbc8d8050b1d51ec4bf15003a2da54e20d476c7. The macro is used in assembly where integer suffixes are not portable. Also, it is unclear how this can overflow as it's already the macros purpose to avoid the overflow. Change-Id: I12c9bfe40891ae3afbfda05f60a20b59e2954aed Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/31290 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* cpu/x86/mtrr: Fix sign overflowPatrick Rudolph2019-02-051-1/+1
| | | | | | | | | | | | Use unsigned long to prevent sign overflow. Fixes wrong MTRRs settings on x86_64 romstage. Signed-off-by: Patrick Rudolph <siro@das-labor.org> Change-Id: I71b61a45becc17bf60a619e4131864c82a16b0d1 Reviewed-on: https://review.coreboot.org/c/30502 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
* src/cpu/intel: Set get_ia32_fsb function commonElyes HAOUAS2019-01-271-0/+30
| | | | | | | | | | | | Add get_ia32_fsb returns FSB values in MHz of intel's CPUs. Also add get_ia32_fsb_x3 function. It returns round up 3 * get_ia32_fsb. Change-Id: I232bf88de7ebba6ac5865db046ce79e9b2f3ed28 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/30103 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* cpu/intel/car: Prepare for C_ENVIRONMENT_BOOTBLOCKKyösti Mälkki2019-01-081-4/+0
| | | | | | | | | | | Pass timestamps and BIST to romstage using the same signature as C_ENVIRONMENT_BOOTBLOCK will. Change-Id: Ic90da6b1b5ac3b56c69b593ba447ed8e05c8a4e2 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30492 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* amdfam10 boards: Use defaults for get_pci1234()Kyösti Mälkki2019-01-041-0/+1
| | | | | | | | | | | | | | All these boards use the same default initialiser. As this is initialized late after device enumeration, it can't really be used to alter platform configuration. Change-Id: I30fc0298081df0442ec4e9a527340b93a3cd6106 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30648 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* amdfam10 boards: Add temporary pirq_router_bus variableKyösti Mälkki2019-01-041-0/+2
| | | | | | | | | | | | It's expected that further analysis shows this to always evaluate to 0. Change-Id: I68599b961ca3b5e3652539c5d825a00444958d1b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30644 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* amdfam10 boards: Declare get_pci1234() just onceKyösti Mälkki2019-01-041-1/+2
| | | | | | | | | Change-Id: I68bb9c4301c846fe2270cd7c434f35a79ab25572 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30627 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* cpu/intel/car: Drop remains of setup_stack_and_mtrrs()Kyösti Mälkki2018-12-301-17/+0
| | | | | | | | | | Platforms have moved to POSTCAR_STAGE=y. Change-Id: I79c87e546805dbe0a4c28ed95f4d12666734eb79 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30489 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* soc/intel: Drop romstage_after_car()Kyösti Mälkki2018-12-281-3/+0
| | | | | | | | | | Platforms moved to POSTCAR_STAGE so these are no longer used. Change-Id: I9a7b5a1f29b402d0e996f2c2f8c6db3800cdddf3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30387 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* Fix typos involving "the the"Jonathan Neuschäfer2018-12-181-1/+1
| | | | | | | | Change-Id: I179264ee6681a7ba4488b9f1c6bce1a19b4e1772 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/c/30160 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* cpu/x86: Make mp_get_apic_id() function externally availableSubrata Banik2018-12-151-0/+3
| | | | | | | | | | | | | | This function returns APIC id for respective cpu core. BUG=b:74436746 BRANCH=none TEST=mp_get_apic_id() can be accessed in other files now. Change-Id: I5c5eda8325f941ab84d8a3fe0dae64be71c44855 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/25620 Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* cpuid: Add helper function for cpuid(1) functionsSubrata Banik2018-12-131-0/+2
| | | | | | | | | | | | | | | | | This patch introduces 3 helper function for cpuid(1) : 1. cpu_get_cpuid() -> to get processor id (from cpuid.eax) 2. cpu_get_feature_flags_ecx -> to get processor feature flag (from cpuid.ecx) 3. cpu_get_feature_flags_edx -> to get processor feature flag (from cpuid.edx) Above 3 helper functions are targeted to replace majority of cpuid(1) references. Change-Id: Ib96a7c79dadb1feff0b8d58aa408b355fbb3bc50 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/30123 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
* smmstore: make smmstore's SMM handler code follow everything elsePatrick Georgi2018-12-051-0/+1
| | | | | | | | | | | Instead of SMMSTORE_APM_CNT use APM_CNT_SMMSTORE and define it in cpu/x86/smm.h Change-Id: Iabc0c9662284ed3ac2933001e64524011a5bf420 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/30023 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* elog: make elog's SMM handler code follow everything elsePatrick Georgi2018-12-051-0/+1
| | | | | | | | | | | Instead of ELOG_GSMI_APM_CNT use APM_CNT_ELOG_GSMI and define it in cpu/x86/smm.h Change-Id: I3a3e2f823c91b475d1e15b8c20e9cf5f3fd9de83 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/30022 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/common: Bring DISPLAY_MTRRS into the lightNico Huber2018-11-231-0/+7
| | | | | | | | | | | | | | | | | | Initially, I wanted to move only the Kconfig DISPLAY_MTRRS into the "Debug" menu. It turned out, though, that the code looks rather generic. No need to hide it in soc/intel/. To not bloat src/Kconfig up any further, start a new `Kconfig.debug` hierarchy just for debug options. If somebody wants to review the code if it's 100% generic, we could even get rid of HAVE_DISPLAY_MTRRS. Change-Id: Ibd0a64121bd6e4ab5d7fd835f3ac25d3f5011f24 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/29684 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* src: Remove unneeded include "{arch,cpu}/cpu.h"Elyes HAOUAS2018-11-122-3/+0
| | | | | | | | Change-Id: I17c4fc4e3e2eeef7c720c6a020b37d8f7a0f57a4 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29300 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* src: Replace common MSR addresses with macrosElyes HAOUAS2018-11-081-0/+1
| | | | | | | | Change-Id: I9fba67be12483ea5e12ccd34c648735d409bc8b0 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29252 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
* intel: Get rid of smm_get_pmbasePatrick Rudolph2018-11-071-3/+0
| | | | | | | | Change-Id: I2b3168c600a81502f9cd1ff3203c492cf026e532 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/27279 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* cpu/amd: Use common AMD's MSRElyes HAOUAS2018-11-051-0/+2
| | | | | | | | | | This Phase #2 follows the CL done on Phase #1 (Change-Id: I0236e0960cd) Change-Id: Ia296e1f9073b45c9137d17fbef29ce4fdfabcb7c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29369 Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* amd/mtrr: Fix IORR MTRRElyes HAOUAS2018-11-051-14/+4
| | | | | | | | | | | | IORR MTRR definitions renamed to avoid collision between <cpu/amd/mtrr.h> and <AGESA.h>. Change-Id: I3eeb0c69bbb76039039dc90683670cafcb00ed36 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29352 Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* src: Add missing include <stdint.h>Elyes HAOUAS2018-11-011-0/+2
| | | | | | | | Change-Id: Idf10a09745756887a517da4c26db7a90a1bf9543 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29403 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* src: Move shared amd64 and IA32 MSRs to <cpu/x86/msr.h>Elyes HAOUAS2018-10-302-189/+171
| | | | | | | | Change-Id: Ic9022a98878a2fcc85868a64aa9c2ca3eb2e2c4e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29177 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* {cpu,drivers,nb,sb}/amd: Replace {MSR,MTRR} addresses with macrosElyes HAOUAS2018-10-301-0/+12
| | | | | | | | | Change-Id: I7e8de35dcdad52bb311b34bfa9b272d17ed3186b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29243 Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* src: Add missing include <stdint.h>Elyes HAOUAS2018-10-301-0/+2
| | | | | | | | Change-Id: I6a9d71e69ed9230b92f0f330875515a5df29fc06 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29312 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* intel: Use CF9 reset (part 2)Patrick Rudolph2018-10-221-26/+0
| | | | | | | | | | | | | | | | | | | | | | | Make use of the common CF9 reset in SOC_INTEL_COMMON_RESET. Also implement board_reset() as a "full reset" (aka. cold reset) as that is what was used here for hard_reset(). Drop soc_reset_prepare() thereby, as it was only used for APL. Also, move the global-reset logic. We leave some comments to remind us that a system_reset() should be enough, where a full_reset() is called now (to retain current behaviour) and looks suspicious. Note, as no global_reset() is implemented for Denverton-NS, we halt there now instead of issuing a non-global reset. This seems safer; a non-global reset might result in a reset loop. Change-Id: I5e7025c3c9ea6ded18e72037412b60a1df31bd53 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/29169 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* cpu/amd: Use common AMD's MSRElyes HAOUAS2018-10-186-129/+53
| | | | | | | | | | | Phase 1. Due to the size of the effort, this CL is broken into several phases. Change-Id: I0236e0960cd1e79558ea50c814e1de2830aa0550 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29065 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
* src: Move common IA-32 MSRs to <cpu/x86/msr.h>Elyes HAOUAS2018-10-114-16/+40
| | | | | | | | | | | | | Use "cpu/x86/msr.h" for common IA-32 MSRs and correct IA-32 MSRs names. Change-Id: Ida7f2d608c55796abf9452f190a58802e498302d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/28752 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Move compiler.h to commonlibNico Huber2018-10-086-7/+0
| | | | | | | | | | | | | | | Its spreading copies got out of sync. And as it is not a standard header but used in commonlib code, it belongs into commonlib. While we are at it, always include it via GCC's `-include` switch. Some Windows and BSD quirk handling went into the util copies. We always guard from redefinitions now to prevent further issues. Change-Id: I850414e6db1d799dce71ff2dc044e6a000ad2552 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/28927 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* src: Fix MSR_PKG_CST_CONFIG_CONTROL register nameElyes HAOUAS2018-10-051-1/+1
| | | | | | | | Change-Id: I492224b6900b9658d54c8cf486ef5d64b299687f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/28871 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
* complier.h: add __always_inline and use it in code baseAaron Durbin2018-09-145-29/+30
| | | | | | | | | | | | Add a __always_inline macro that wraps __attribute__((always_inline)) and replace current users with the macro, excluding files under src/vendorcode. Change-Id: Ic57e474c1d2ca7cc0405ac677869f78a28d3e529 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/28587 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@google.com>
* amd/fam15: Add more MCA informationMarshall Dawson2018-09-071-0/+166
| | | | | | | | | | | | | | | | Add more definitions to be used for Machine Check Architecture support, mainly for determining the type of error that is being interpreted. MCA is described in detail in the BKDG. BUG=b:65446699 TEST=inspect BERT region, and dmesg, on full patch stack. Use test data plus a failing Grunt system. Change-Id: I0682288aa58c69aee323fb43f74027f7a1905b68 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/28473 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
* src/include: add more msr definesMatt Delco2018-08-171-1/+7
| | | | | | | | | | | | This change adds some MSRs that are needed in a subsequent change to add support for Continuous Performance Control. Change-Id: Id4ecff1bc5eedaa90b41de526b9a2e61992ac296 Signed-off-by: Matt Delco <delco@chromium.org> Reviewed-on: https://review.coreboot.org/28067 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
* amd/fam15: Add MCA bank register definitionsMarshall Dawson2018-08-081-0/+4
| | | | | | | | | | | Define the additional registers used for each Machine Check Architecture bank. Change-Id: I962f23662789a3b974f4946555f67fcfc6147df8 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/27925 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
* cpu/amd: Correct number of MCA banks clearedMarshall Dawson2018-08-082-0/+4
| | | | | | | | | | | | | | | | | | Use the value discovered in the MCG_CAP[Count] for the number of MCA status registers to clear. The generations should have the following number of banks: * Family 10h: 6 banks * Family 12h: 6 * Family 14h: 6 * Family 15h: 7 * Family 16h: 6 Change-Id: I0fc6d127a200b10fd484e051d84353cc61b27a41 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/27923 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
* cpu/amd: Rename MCA status registerMarshall Dawson2018-08-082-2/+2
| | | | | | | | | | | | Change the defined name of MCI_STATUS (i.e. MCi_STATUS) to reflect its MC0_STATUS address. Change-Id: I97d2631a186965bb8b18f544ed9648b3a71f5fb0 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/27922 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
* cpu/intel/smm/gen1: Use correct MSR for model_6fx and model_1067xArthur Heymans2018-07-301-0/+4
| | | | | | | | | | | | | According to the "Intel® 64 and IA-32 Architectures Software Developer’s Manual" the SMRR MSR are at a different offset for model_6fx and model_1067x. This still need SMRR enabled and lock bit set in MSR_FEATURE_CONTROL. Change-Id: I8ee8292ab038e58deb8c24745ec1a9b5da8c31a9 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/27585 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* cpu/intel/microcode: Add helper functions to get microcode infoRizwan Qureshi2018-07-301-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | Add 4 helper functions to get microcode info. * get_current_microcode_rev return the the version of the currently running microcode. * get_microcode_rev extract microcode revision from the given patch. * get_microcode_size extract microcode size from the given patch. * get_microcode_checksum extract checksum from the given patch. The simpler thing would be to just move the struct microcode to microcode.h so that the structure members can be dereferenced. To encapsulate the structure details added the helper functions. This information will be used in future to compare microcodes for update. Change-Id: I67a08ba40b393874d8cc17363fefe21e2ea904f3 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/27365 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* cpu/x86/mtrr.h: Rename MSR SMRR_PHYS_x to IA32_SMRR_PHYSxArthur Heymans2018-07-241-2/+2
| | | | | | | | | | | | | | This is how these MSR's are referenced in Intel® 64 and IA-32 Architectures Software Developer’s Manual. The purpose is to differentiate with MSR_SMRR_PHYSx. Change-Id: I54875f3a6d98a28004d5bd3197923862af8f7377 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/27584 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* src/{ec,include,lib}: Use "foo *bar" instead of "foo* bar"Elyes HAOUAS2018-07-091-2/+2
| | | | | | | | Change-Id: I447aaa1850b7e8b514a8c4c04bf5b426d3d1cd0a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27405 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* smm: Add canary to end of stack and die() if a stack overflow occursRaul E Rangel2018-06-281-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If CPU 0's stack grows to large, it will overflow into CPU 1's stack. If CPU 0 is handling the interrupt then CPU 1 should be in an idle loop. When the stack overflow occurs it will override the return pointer for CPU 1, so when CPU 0 unlocks the SMI lock, CPU 1 will attempt to return to a random address. This method is not foolproof. If code allocates some stack variables that overlap with the canary, and if the variables are never set, then the canary will not be overwritten, but it will have been skipped. We could mitigate this by adding a larger canary value if we wanted. I chose to use the stack bottom pointer value as the canary value because: * It will change per CPU stack. * Doesn't require hard coding a value that must be shared between the .S and .c. * Passing the expected canary value as a parameter felt like overkill. We can explore adding other methods of signaling that a stack overflow had occurred in a follow up. I limited die() to debug only because otherwise it would be very hard to track down. TEST=built on grunt with a small and large stack size. Then verified that one causes a stack overflow and the other does not. Stack overflow message: canary 0x0 != 0xcdeafc00 SMM Handler caused a stack overflow Change-Id: I0184de7e3bfb84e0f74e1fa6a307633541f55612 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/27229 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* nb/intel/fsp_rangeley: Use MSR_PLATFORM_INFO instead of 0xceElyes HAOUAS2018-06-141-0/+2
| | | | | | | | Change-Id: Ifb8aa43b6545482bc7fc136a90c4bbaa18d46089 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/22957 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* amd/geode_lx: Fix .c includesKyösti Mälkki2018-06-051-0/+4
| | | | | | | | | Change-Id: I2cce52561d30e30e1c81752cd2a455e7211006eb Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26825 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Piotr Król <piotr.krol@3mdeb.com>
* cpu/x86/mtrr.h: Clean up some guardsNico Huber2018-06-041-13/+11
| | | | | | | | | | | Move #includes to the top and remove unnecessary guards. Hopefully this prevents future surprises. Change-Id: Id4571c46a0c05a080b2b1cfec64b4eda07d793bb Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/26761 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* cpu/intel/car: Prepare for some POSTCAR_STAGE supportKyösti Mälkki2018-06-021-0/+2
| | | | | | | | | | | | | | | | The file cache_as_ram_ht.inc is used across a variety of CPUs and northbridges. We need to split it anyway for future C_ENVIRONMENT_BOOTBLOCK and verstage work. Split and rename the files, remove code that is globally implemented in POSTCAR_STAGE framework already. Change-Id: I2ba67772328fce3d5d1ae34c36aea8dcdcc56b87 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26747 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* cpu/x86/mtrr: Prepare for ROM_SIZE > 16MiBNico Huber2018-05-311-4/+14
| | | | | | | | | | | | Most, if not all, chipsets have MMIO between 0xfe000000 and 0xff000000. So don't try to cache more than 16MiB of the ROM. It's also common that at most 16MiB are memory mapped. Change-Id: I5dfa2744190a34c56c86e108a8c50dca9d428268 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/26567 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* cpu/x86/mtrr: Get rid of CACHE_ROM_SIZE_OVERRIDENico Huber2018-05-311-22/+25
| | | | | | | | | | | | | | | | | As far as I can see this Kconfig option was used wrong ever since it was added. According to the commit message of 107f72e (Re-declare CACHE_ROM_SIZE as aligned ROM_SIZE for MTRR), it was only necessary to prevent overlapping with CAR. Let's handle the potential overlap in C macros instead and get rid of that option. Currently, it was only used by most FSP1.0 boards, and only because the `fsp1_0/Kconfig` set it to CBFS_SIZE (WTF?). Change-Id: I4d0096f14a9d343c2e646e48175fe2127198a822 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/26566 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* Remove AMD K8 cpu and northbridge supportKyösti Mälkki2018-05-312-161/+0
| | | | | | | | Change-Id: I9c53dfa93bf906334f5c80e4525a1c27153656a3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26673 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* AMD: Remove some leftover includesKyösti Mälkki2018-05-242-853/+0
| | | | | | | | Change-Id: I740d945693b4f16495488fb76ad6d1ee531185ac Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26508 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-17 09:30:44 +0000