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* Spell *Boot Guard* with a space for official spellingPaul Menzel2021-12-161-1/+1
| | | | | | | | | | | | | | | | | See for example Intel document *Secure the Network Infrastructure – Secure Boot Methodologies* [1]. Change all occurrences with the command below: $ git grep -l BootGuard | xargs sed -i 's/BootGuard/Boot Guard/g' [1]: https://builders.intel.com/docs/networkbuilders/secure-the-network-infrastructure-secure-boot-methodologies.pdf Change-Id: I69fb64b525fb4799bcb9d75624003c0d59b885b5 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60136 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* lib/cbfs: Disable cbfs_preload in romstage when VBOOT_STARTS_IN_ROMSTAGERaul E Rangel2021-12-151-0/+4
| | | | | | | | | | | | | | | Preloading files before vboot runs and using them after vboot has finished will result in the wrong files getting used. Disable cbfs_preload to avoid this behavior. BUG=b:179699789 TEST=none Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I7698b481a73fb24eecf4c810ff8be8b6826528ca Reviewed-on: https://review.coreboot.org/c/coreboot/+/59876 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* rules.h, thread.h, lib/cbfs: Add ENV_STAGE_SUPPORTS_COOPRaul E Rangel2021-12-151-1/+1
| | | | | | | | | | | | | | This change consolidates the COOP rules. Co-op in theory works in all x86 stages now, but it hasn't been enabled yet. BUG=b:179699789 TEST=Boot guybrush to OS and verify preloads still work Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I1197406d1d36391998b08e3076146bb2fff59d00 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59550 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* cbfs: Enable CBFS verification KconfigsJulius Werner2021-12-132-20/+34
| | | | | | | | | | | | | | | | With the elimination of remaining non-verifying CBFS APIs in CB:59682, CBFS verification is now ready to be used in its simplest form, so enable the respective Kconfig options in menuconfig. Add a few more restrictions to the TOCTOU_SAFETY option for problems that haven't been solved yet, and transform a comment in cbfs.c into a die() to make sure we don't accidentally forget implementing it once vboot integration gets added. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Ifeba5c962c943856ab79bc6c4cb90a60c1de4a60 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59982 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
* cbfs: Remove deprecated APIsJulius Werner2021-12-061-40/+0
| | | | | | | | | | | | | | This patch removes all remaining pieces of the old CBFS API, now that the last straggling use cases of it have been ported to the new one (meaning cbfs_map()/cbfs_load()/etc... see CB:39304 and CB:38421). Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I1cec0ca2d9d311626a087318d1d78163243bfc3c Reviewed-on: https://review.coreboot.org/c/coreboot/+/59682 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
* cbfs | tspi: Join hash calculation for verification and measurementJulius Werner2021-12-031-19/+28
| | | | | | | | | | | | | | | | | | | This patch moves the CBFS file measurement when CONFIG_TPM_MEASURED_BOOT is enabled from the lookup step into the code where a file is actually loaded or mapped from flash. This has the advantage that CBFS routines which just look up a file to inspect its metadata (e.g. cbfs_get_size()) do not cause the file to be measured twice. It also removes the existing inefficiency that files are loaded twice when measurement is enabled (once to measure and then again when they are used). When CBFS verification is enabled and uses the same hash algorithm as the TPM, we are even able to only hash the file a single time and use the result for both purposes. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I70d7066c6768195077f083c7ffdfa30d9182b2b7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59681 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* region: Rename rdev_readat_full to rdev_read_fullJulius Werner2021-12-031-1/+1
| | | | | | | | | | | The 'at' part of the name refers to starting to read from a specific offset, so it doesn't make sense for the 'full' version of the function. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I60d595f0cbd161df171eaa4a76c7a00b6377e2b0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59820 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* cbfs: Add unverified_area APIsJulius Werner2021-11-301-74/+100
| | | | | | | | | | | | | | | | | | | | | | This patch adds a new ..._unverified_area_... group of functions to the cbfs_map/_load/_alloc() APIs. These functions can be used to access custom FMAP sections and are meant to replace the existing cbfs_locate_file_in_region(). The name is intended to highlight that accesses through this API will not be verified when CBFS_VERIFICATION is enabled and should always be treated as if they may return malicious data. (Due to laziness I'm not adding the combination of this API with the ..._type_... variant at this point, since it seems very unlikely that we'll ever have a use case for that. If we ever do, it should be easy to add later.) (Also remove the 'inline' from cbfs_file_hash_mismatch(). I'm not sure why I put it there in the first place, probably a bad copy&paste.) Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I402265900f7075aa0c2f58d812c67ea63ddf2900 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59678 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* cbfs: Add helper functions to look up size and type of a fileJulius Werner2021-11-171-8/+8
| | | | | | | | | | | | | | | | | | | | | | | This patch adds cbfs_get_size() and cbfs_get_type() helper functions (and _ro_ variations) to look up the size or type of a CBFS file without loading it. Generally, use of these should be discouraged because that tends to mean that the file needs to be looked up more than once, and cbfs_alloc() or cbfs_type_load() are usually the more efficient alternative... but sometimes they're unavoidable, so we might as well offer them. Also remove the <cbfs_private.h> header which had already become sort of unnecessary with previous changes. cbfs_boot_lookup() is now exported in <cbfs.h> for use in inlines, but should not be used directly by other files (and is prefixed with an underscore to highlight that). Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I8092d8f6e04bdfb4df6c626dc7d42b402fe0a8ba Reviewed-on: https://review.coreboot.org/c/coreboot/+/59312 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
* src/lib/prog_loaders: Add preload_ramstageRaul E Rangel2021-11-161-0/+8
| | | | | | | | | | | | | | This will enable preloading ramstage. By preloading the file into cbfs_cache we reduce boot time. BUG=b:179699789 TEST=Boot guybrush to OS and see 12ms reduction in boot time. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ibe12de806449da25bc0033b02fcb97c3384eddc1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58982 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* lib/prog_loaders, soc/amd/: Make payload_preload use cbfs_preloadRaul E Rangel2021-11-162-55/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that CBFS has this functionality built in, we no longer need to manually code it. payload_preload used to use the payload_preload_cache region to store the raw payload contents. This region was placed outside the firmware reserved region, so it was available for use by the OS. This was possible because the payload isn't loaded again on S3 resume. cbfs_preload only uses the cbfs_cache region. This region must be reserved because it gets used on the S3 resume path. Unfortunately this means that cbfs_cache must be increased to hold the payload. Cezanne is the only platform currently using payload_preload, and the size of cbfs_cache has already been adjusted. In the future we could look into adding an option to cbfs_preload that would allow it to use a different memory pool for the cache allocation. BUG=b:179699789 TEST=Boot guybrush and verify preloading the payload was successful CBFS DEBUG: get_preload_rdev(name='fallback/payload') preload successful Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Idc521b238620ff52b8ba481cd3c10e5c4f1394bd Reviewed-on: https://review.coreboot.org/c/coreboot/+/58962 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* lib/hardwaremain: Run timers more frequentlyRaul E Rangel2021-11-151-0/+5
| | | | | | | | | | | | | | | This change makes it so the timers run after each boot state callback, and after each boot state. This gives coop threads the opportunity to run more frequently and predictably. BUG=b:179699789 TEST=Boot guybrush to OS, see SPI transactions progress faster. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I9508e7777d52fe934cc09d486abc0dab5cf7dad8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58955 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
* arch/x86: Refactor the SMBIOS type 17 write functionSubrata Banik2021-11-111-13/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | List of changes: 1. Create Module Type macros as per Memory Type (i.e. DDR2/DDR3/DDR4/DDR5/LPDDR4/LPDDR5) and fix compilation issue due to renaming of existing macros due to scoping the Memory Type. 2. Use dedicated Memory Type and Module type for `Form Factor` and `TypeDetail` conversion using `get_spd_info()` function. 3. Create a new API (convert_form_factor_to_module_type()) for `Form Factor` to 'Module type' conversion as per `Memory Type`. 4. Add new argument as `Memory Type` to smbios_form_factor_to_spd_mod_type() so that it can internally call convert_form_factor_to_module_type() for `Module Type` conversion. 5. Update `test_smbios_form_factor_to_spd_mod_type()` to accommodate different memory types. 6. Skip fixed module type to form factor conversion using DDR2 SPD4 specification (inside dimm_info_fill()). Refer to datasheet SPD4.1.2.M-1 for LPDDRx and SPD4.1.2.L-3 for DDRx. BUG=b:194659789 TEST=Refer to dmidecode -t 17 output as below: Without this code change: Handle 0x0012, DMI type 17, 40 bytes Memory Device Array Handle: 0x000A Error Information Handle: Not Provided Total Width: 16 bits Data Width: 16 bits Size: 2048 MB Form Factor: Unknown .... With this code change: Handle 0x0012, DMI type 17, 40 bytes Memory Device Array Handle: 0x000A Error Information Handle: Not Provided Total Width: 16 bits Data Width: 16 bits Size: 2048 MB Form Factor: Row Of Chips .... Change-Id: Ia337ac8f50b61ae78d86a07c7a86aa9c248bad50 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56628 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* lib/thread: Start stopwatch after printkRaul E Rangel2021-11-101-2/+2
| | | | | | | | | | | | | | | | | | We are currently counting how long it takes to print the waiting message, in addition to the actual time we spent waiting. This results in inflating the measurement by 1.7ms when the serial console is enabled. This CL makes it so the print happens before the stopwatch starts. BUG=b:179699789 TEST=No longer see printk time taken into account on serial console Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ib48e37c1b2cb462d634141bf767673936aa2dd26 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58960 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Rob Barnes <robbarnes@google.com>
* Rename ECAM-specific MMCONF KconfigsShelley Chen2021-11-101-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, the MMCONF Kconfigs only support the Enhanced Configuration Access mechanism (ECAM) method for accessing the PCI config address space. Some platforms have a different way of mapping the PCI config space to memory. This patch renames the following configs to make it clear that these configs are ECAM-specific: - NO_MMCONF_SUPPORT --> NO_ECAM_MMCONF_SUPPORT - MMCONF_SUPPORT --> ECAM_MMCONF_SUPPORT - MMCONF_BASE_ADDRESS --> ECAM_MMCONF_BASE_ADDRESS - MMCONF_BUS_NUMBER --> ECAM_MMCONF_BUS_NUMBER - MMCONF_LENGTH --> ECAM_MMCONF_LENGTH Please refer to CB:57861 "Proposed coreboot Changes" for more details. BUG=b:181098581 BRANCH=None TEST=./util/abuild/abuild -p none -t GOOGLE_KOHAKU -x -a -c max Make sure Jenkins verifies that builds on other boards Change-Id: I1e196a1ed52d131a71f00cba1d93a23e54aca3e2 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57333 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* src/lib: Add FW_CONFIG_SOURCE_VPDWonkyu Kim2021-11-081-0/+12
| | | | | | | | | | | | | | | | | | Read fw_config value from VPD. This new option can be used where chrome EC is not supported like pre-silicon platform and fw_config can be updated by VPD tool in OS. TEST= boot to OS and read fw_config from vpd 1. Boot to OS 2. Write "fw_config" in VPD ex) vpd -i "RW_VPD" -s "fw_config"="1" 3. reboot and check fw_config value from coreboot log Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: I4df7d5612e18957416a40ab854fa63c8b11b4216 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58839 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* src/lib/fw_config: Change fw_config sources priorityWonkyu Kim2021-11-081-17/+16
| | | | | | | | | | | | | | | | Request fw_config values from various sources (as enabled via Kconfig) until a valid value has been read. With this change, Chrome EC CBI takes precedence over CBFS fw_config. TEST=select both configs and check fallback behavior. 1. select both FW_CONFIG_SOURCE_CHROMEEC_CBI and FW_CONFIG_SOURCE_CBFS 2. check log for reading fw_config from CBI and CBFS Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: I215c13a4fcb9dc3b94f73c770e704d4e353e9cff Reviewed-on: https://review.coreboot.org/c/coreboot/+/58833 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* lib/cbfs: Add cbfs_preload()Raul E Rangel2021-11-042-6/+175
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This API will hide all the complexity of preloading a CBFS file. It makes it so the callers simply specify the file to preload and CBFS takes care of the rest. It will start a new thread to read the file into the cbfs_cache. When the file is actually required (i.e., cbfs_load, etc) it will wait for the preload thread to complete (if it hasn't already) and perform verification/decompression using the preloaded buffer. This design allows decompression/verification to happen in the main BSP thread so that timestamps are correctly reflected. BUG=b:179699789 TEST=Test with whole CL chain, verify VGA bios was preloaded and boot time was reduced by 12ms. Logs: Preloading VGA ROM CBFS DEBUG: _cbfs_preload(name='pci1002,1638.rom', force_ro=false) CBFS: Found 'pci1002,1638.rom' @0x20ac40 size 0xd800 in mcache @0xcb7dd0f0 spi_dma_readat_dma: start: dest: 0x021c0000, source: 0x51cc80, size: 55296 took 0 us to acquire mutex start_spi_dma_transaction: dest: 0x021c0000, source: 0x51cc80, remaining: 55296 ... spi_dma_readat_dma: end: dest: 0x021c0000, source: 0x51cc80, remaining: 0 ... CBFS DEBUG: _cbfs_alloc(name='pci1002,1638.rom', alloc=0x00000000(0x00000000), force_ro=false, type=-1) CBFS: Found 'pci1002,1638.rom' @0x20ac40 size 0xd800 in mcache @0xcb7dd0f0 waiting for thread took 0 us CBFS DEBUG: get_preload_rdev(name='pci1002,1638.rom', force_ro=false) preload successful In CBFS, ROM address for PCI: 03:00.0 = 0x021c0000 PCI expansion ROM, signature 0xaa55, INIT size 0xd800, data ptr 0x01b0 PCI ROM image, vendor ID 1002, device ID 1638, PCI ROM image, Class Code 030000, Code Type 00 Copying VGA ROM Image from 0x021c0000 to 0xc0000, 0xd800 bytes $ cbmem ... 40:device configuration 5,399,404 (8,575) 65:Option ROM initialization 5,403,474 (4,070) 66:Option ROM copy done 5,403,488 (14) ... Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I879fc1316f97417a4b82483d353abdbd02b98a31 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56491 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* lib/thread: Use __func__ instead of repeating function nameRaul E Rangel2021-11-041-4/+4
| | | | | | | | | | | | | | | This cleans up the warning message: WARNING: Prefer using '"%s...", __func__' to using 'thread_run', this function's name, in a string BUG=b:179699789 TEST=boot guybrush Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I85bacb7b2d9ebec40b6b05edc2ecf0ca1fc8ceee Reviewed-on: https://review.coreboot.org/c/coreboot/+/58867 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
* lib/thread: Add ERROR prefix to error messagesRaul E Rangel2021-11-041-4/+4
| | | | | | | | | | | | | This makes it easier to grep for errors. BUG=b:179699789 TEST=Boot guybrush Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I7eecdfed6046b7d609069e7427f6883a4e9e521d Reviewed-on: https://review.coreboot.org/c/coreboot/+/58866 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
* lib: Add list.c to all stagesRaul E Rangel2021-11-041-1/+2
| | | | | | | | | | | | | This will be used in cbfs.c which is used in all stages. BUG=b:179699789 TEST=Build guybrush Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I0713ae766c0ac9e43de702690ad0ba961d636d18 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58804 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* lib/cbfs: Add CBFS_CACHE_ALIGN Kconfig optionRaul E Rangel2021-11-042-2/+8
| | | | | | | | | | | | | | | | This option will allow platforms to set the alignment of the cbfs_cache buffers. BUG=b:179699789 TEST=gdb -ex 'p cbfs_cache' /tmp/coreboot/guybrush/cbfs/fallback/ramstage.debug $1 = {buf = 0x0, size = 0, alignment = 8, last_alloc = 0x0, second_to_last_alloc = 0x0, free_offset = 0} Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I74598d4bcbca9a01cc8c65012d7e4ae341d052b1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58706 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
* commonlib/mem_pool: Allow configuring the alignmentRaul E Rangel2021-11-041-4/+5
| | | | | | | | | | | | | | | | | | AMD platforms require the destination to be 64 byte aligned in order to use the SPI DMA controller. This is enforced by the destination address register because the first 6 bits are marked as reserved. This change adds an option to the mem_pool so the alignment can be configured. BUG=b:179699789 TEST=Boot guybrush to OS Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I8d77ffe4411f86c54450305320c9f52ab41a3075 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56580 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* lib/list: Add list_appendRaul E Rangel2021-11-031-0/+8
| | | | | | | | | | | | | This method will add a node to the end of the list. BUG=b:179699789 TEST=Boot guybrush to the OS Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I1792e40f789e3ef16ceca65ce4cae946e08583d1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58805 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* google/trogdor: Add backlight support for Parade ps8640xuxinxiong2021-11-022-0/+42
| | | | | | | | | | | | | | | Add backlight support in ps8640 through the AUX channel using eDP DPCD registers. BUG=b:202966352 BRANCH=trogdor TEST=verified firmware screen works on homestar rev4 Change-Id: Ief1bf56c89c8215427dcbddfc67e8bcd4c3607d2 Signed-off-by: xuxinxiong <xuxinxiong@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58624 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* lib: Add new argument as `ddr_type` to smbios_bus_width_to_spd_width()Subrata Banik2021-11-021-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add DDR5 and LPDDR5 memory type checks while calculating bus width extension (in bits). Additionally, update all caller functions of smbios_bus_width_to_spd_width() to pass `MemoryType` as argument. Update `test_smbios_bus_width_to_spd_width()` to accommodate different memory types. Create new macro to fix incorrect bus width reporting on platform with DDR5 and LPDDR5 memory. With this code changes, on DDR5 system with 2 Ch per DIMM, 32 bit primary bus width per Ch showed the Total width as: Handle 0x000F, DMI type 17, 40 bytes Memory Device Array Handle: 0x0009 Error Information Handle: Not Provided Total Width: 80 bits Data Width: 64 bits Size: 16 GB ... BUG=b:194659789 Tested=On Alder Lake DDR5 RVP, SMBIOS type 17 shows expected `Total Width`. Change-Id: I79ec64c9d522a34cb44b3f575725571823048380 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58601 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
* lib: Use `smbios_bus_width_to_spd_width` for setting dimm.bus_widthSubrata Banik2021-10-301-0/+1
| | | | | | | | | | | | | | | Make use of `smbios_bus_width_to_spd_width()` for filling DIMM info. Additionally, ensures dimm_info_util.c file is getting compiled for romstage. TEST=dmidecode -t 17 output Total Width and Data Width as expected. Change-Id: I7fdc19fadc576dec43e12f182fe088707e6654d9 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58655 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* lib/cbfs: Enable cbfs_cache for x86Raul E Rangel2021-10-291-6/+12
| | | | | | | | | | | | | | | | | | | | The reason cbfs_cache was disabled on x86 was due to the lack of .data sections in the pre-RAM stages. By using ENV_STAGE_HAS_DATA_SECTION we enable x86 to start using the cbfs_cache. We still need to add a cbfs_cache region into the memlayout for it to be enabled. BUG=b:179699789 TEST=Build guybrush and verify cbfs_cache.size == 0. Suggested-by: Julius Werner <jwerner@chromium.org> Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I74434ef9250ff059e7587147b1456aeabbee33aa Reviewed-on: https://review.coreboot.org/c/coreboot/+/56577 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* src/lib/fmap.c: use le*toh() functions where neededKrystian Hebel2021-10-271-6/+8
| | | | | | | | | | | | FMAP was developed with assumption about endianness of the target machine. This broke the parsing of the structure on big endian architectures. This patch converts the endianness of the fields where applicable. Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com> Change-Id: I8784ac29101531db757249496315f43e4008de4f Reviewed-on: https://review.coreboot.org/c/coreboot/+/55038 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* lib/cbfs: Call rdev_unmap on hash mismatchRaul E Rangel2021-10-201-1/+8
| | | | | | | | | | | | | | We don't want to leak any mappings. BUG=b:179699789 TEST=none Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ibcd28ce12cbd5e221e8f4fa910fd8472bedb802f Reviewed-on: https://review.coreboot.org/c/coreboot/+/56576 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* arch/x86,cpu/x86,lib/thread: Remove usage of cpu_info from lib/threadRaul E Rangel2021-10-181-8/+15
| | | | | | | | | | | | | | | | | We only ever start and execute threads on the BSP. By explicitly checking to see if the CPU is the BSP we can remove the dependency on cpu_info. With this change we can in theory enable threads in all stages. BUG=b:194391185, b:179699789 TEST=Boot guybrush to OS and verify coop multithreading still works Suggested-by: Julius Werner <jwerner@chromium.org> Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Iea4622d52c36d529e100b7ea55f32c334acfdf3e Reviewed-on: https://review.coreboot.org/c/coreboot/+/58199 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* lib/thread: Remove thread stack alignment requirementRaul E Rangel2021-10-051-16/+5
| | | | | | | | | | | | | | | | CPU_INFO_V2 now encapsulates the cpu_info requirements. They no longer need to leak through to thread.c. This allows us to remove the alignment requirement. BUG=b:179699789 TEST=Reboot stress test guybrush 50 times. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I0af91feddcbd93b7f7d0f17009034bd1868d5aef Reviewed-on: https://review.coreboot.org/c/coreboot/+/57928 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Peers <epeers@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* lib/thread: Switch to using CPU_INFO_V2Raul E Rangel2021-10-051-22/+5
| | | | | | | | | | | | | | | | | | | | | CPU_INFO_V2 changes the behavior of cpu_info(). There is now only 1 cpu_info struct per cpu. This means that we no longer need to allocate it at the top of each threads stack. We can now in theory remove the CONFIG_STACK_SIZE alignment on the thread stack sizes. We can also in theory use threads in SMM if you are feeling venturesome. BUG=b:194391185, b:179699789 TEST=Perform reboot stress test on guybrush with COOP_MULTITASKING enabled. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I5e04d254a00db43714ec60ebed7c4aa90e23190a Reviewed-on: https://review.coreboot.org/c/coreboot/+/57628 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Peers <epeers@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* src/acpi to src/lib: Fix spelling errorsMartin Roth2021-10-054-6/+6
| | | | | | | | | | | | These issues were found and fixed by codespell, a useful tool for finding spelling errors. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I5b8ecdfe75d99028fee820a2034466a8ad1c5e63 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58080 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* coreboot tables: Add type-c port info to coreboot tableNick Vaccaro2021-10-041-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | This change adds type-c port information for USB Type-C ports to the coreboot table. This allows depthcharge to know the usb2 and usb3 port number assignments for each available port, as well as the SBU and data line orientation for the board. BUG=b:149830546 TEST='emerge-volteer coreboot chromeos-bootimage' and verify it builds successfully. Cherry-pick CL to enable this feature for volteer, flash and boot volteer2 to kernel, log in and check cbmem for type-c info exported to the payload: localhost ~ # cbmem -c | grep type-c added type-c port0 info to cbmem: usb2:9 usb3:1 sbu:0 data:0 added type-c port1 info to cbmem: usb2:4 usb3:2 sbu:1 data:0 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Change-Id: Ice732be2fa634dbf31ec620552b383c4a5b41451 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57069 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* lib/hardwaremain: change type of "complete" element in boot_state structFelix Held2021-10-041-3/+3
| | | | | | | | | | | | | | A signed bitfield with a length of 1 bit can only have the values 0 and -1. Assigning a 1 ends up behaving as expected, but it's not the semantically correct thing to do there. Changing the type of the element to an unsigned bitfield with a length of 1 would fix that, but since this is used as a boolean value, just change it to bool type. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I230804335e7a15a8a9489859b20846988ba6c5cd Reviewed-on: https://review.coreboot.org/c/coreboot/+/58076 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* lib/hardwaremain: add missing types.h includeFelix Held2021-10-041-0/+1
| | | | | | | | | | | The u8 type is used in the file, but neither stdint.h not types.h was included in the file. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ifd67aff9eba01f9618004c869f1473217b3aeae4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58075 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* lib/Makefile.inc: Generate placeholder spd.bin in lib/Makefile.incReka Norman2021-09-231-8/+12
| | | | | | | | | | | | | | | | | | | | | When a new variant is created, it needs to have a path to its SPD binary defined. Currently, this is done by setting SPD_SOURCES to a placeholder SPD file, which just contains zero bytes. To remove the need for a placeholder file, automatically generate a single-byte spd.bin in lib/Makefile.inc when SPD_SOURCES is set to the marker value 'placeholder'. BUG=b:191776301 TEST=Change cappy/memory/Makefile to `SPD_SOURCES = placeholder`. Build and check that spd.bin contains a single zero byte. Signed-off-by: Reka Norman <rekanorman@google.com> Change-Id: I11f8f9b7ea3bc32aa5c7a617558572a5c1c74c72 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57795 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
* lib/Makefile.inc: Fail build if SPD file doesn't existReka Norman2021-09-211-4/+8
| | | | | | | | | | | | | | | | Currently, if LIB_SPD_DEPS contains an SPD file which doesn't exist, the file is silently skipped when creating spd.bin. Instead, fail the build. BUG=b:191776301 TEST=Build test on brya. Build fails if a non-existent file is included in LIB_SPD_DEPS. Change-Id: I1bdadb72e087c2ee7a88fbab2f3607bd400fa2e4 Signed-off-by: Reka Norman <rekanorman@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57697 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
* Move post_codes.h to commonlib/console/Ricardo Quesada2021-08-041-9/+9
| | | | | | | | | | | | | | | | | | | | | Move post_codes.h from include/console to commonlib/include/commonlib/console. This is because post_codes.h is needed by code from util/ (util/ code in different commit). Also, it sorts the #include statements in the files that were modified. BUG=b:172210863 Signed-off-by: Ricardo Quesada <ricardoq@google.com> Change-Id: Ie48c4b1d01474237d007c47832613cf1d4a86ae1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56403 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* arch/x86,lib/thread: Enable thread support in romstageRaul E Rangel2021-07-261-2/+6
| | | | | | | | | | | | | | | | | | | | This change does the following: * Pushes the cpu_info struct into the top of the stack (just like c_start.S). This is required so the cpu_info function works correctly. * Adds the thread.c to the romstage build. I only enabled this for romstage since I haven't done any tests in other stages, but in theory it should work for other stages. BUG=b:179699789 TEST=Boot guybrush with threads enabled in romstage Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I8e32e1c54dea0d0c85dd6d6753147099aa54b9b5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56494 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* lib/thread,lib/hardwaremain: Lazy initialize threadsRaul E Rangel2021-07-262-2/+10
| | | | | | | | | | | | | | | By lazy initializing the threads, if a stage doesn't use them, they will be garbage collected. BUG=b:179699789 TEST=Boot guybrush to the OS and verify threads worked Suggested-by: Julius Werner <jwerner@chromium.org> Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I7208ffb5dcda63d916bc6cfdea28d92a62435da6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56532 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* lib/thread,arch/x86: Move thread stacks into C bssRaul E Rangel2021-07-261-3/+6
| | | | | | | | | | | | | | | | There is no reason this needs to be done in asm. It also allows different stages to use threads. If threads are no used in a specific stage, the compiler will garbage collect the space. BUG=b:179699789 TEST=Boot guybrush to the OS Suggested-by: Julius Werner <jwerner@chromium.org> Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ib5a84a62fdc75db8ef0358ae16ff69c20cbafd5f Reviewed-on: https://review.coreboot.org/c/coreboot/+/56531 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* lib/thread: Add asserts around stack size and alignmentRaul E Rangel2021-07-261-0/+7
| | | | | | | | | | | | | `cpu_info()` requires that stacks be STACK_SIZE aligned and a power of 2. BUG=b:179699789 TEST=Boot guybrush to the OS Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I615623f05bfbe2861dcefe5cae66899aec306ba2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56530 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
* lib/thread: Guard thread_run_until with ENV_RAMSTAGERaul E Rangel2021-07-261-0/+4
| | | | | | | | | | | | | | | | thread_run_until is a ramstage specific API. This change guards the API by checking ENV_RAMSTAGE. BUG=b:179699789 TEST=Boot guybrush to the OS Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I4784942070fd352a48c349f3b65f5a299abf2800 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56529 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* lib/cbfs,device/pci_rom: Move cbfs_boot_map_optionrom and modernizeRaul E Rangel2021-07-201-40/+0
| | | | | | | | | | | | | | | These methods are oprom specific. Move them out of CBFS. I also deleted the tohex methods and replaced them with snprintf. BUG=b:179699789 TEST=Boot guybrush and see oprom still loads Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I03791f19c93fabfe62d9ecd4f9b4fad0e6a6146e Reviewed-on: https://review.coreboot.org/c/coreboot/+/56393 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
* lib/prog_loaders: Add payload_preloadRaul E Rangel2021-07-192-6/+63
| | | | | | | | | | | | | | This method will allow the SoC code to start loading the payload before it is required. BUG=b:177909625 TEST=Boot guybrush and see read/decompress drop by 23 ms. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ifa8f30a0f4f931ece803c2e8e022e4d33d3fe581 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56051 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
* lib/hardwaremain: Drop boot_state_current_{block,unblock}()Raul E Rangel2021-07-181-10/+0
| | | | | | | | | | | | | | There are no more callers. BUG=b:179699789 TEST=Compile guybrush Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I522f17c0e450641c0a60496ba07800da7e39889c Reviewed-on: https://review.coreboot.org/c/coreboot/+/56389 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* lib/thread: Make thread_run not block the current stateRaul E Rangel2021-07-181-13/+1
| | | | | | | | | | | | | | | | | | | If a thread wants to block a state transition it can use thread_run_until. Otherwise just let the thread run. `thread_join` can be used to block on the thread. Boot states are also a ramstage concept. If we want to use this API in any other stage, we need a way of starting a thread without talking about stages. BUG=b:179699789 TEST=verify thread_run no longer blocks the current state Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I3e5b0aed70385ddcd23ffcf7b063f8ccb547fc05 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56351 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* lib/thread: Add thread_handleRaul E Rangel2021-07-181-16/+57
| | | | | | | | | | | | | | | | | The thread_handle can be used to wait for a thread to exit. I also added a return value to the thread function that will be stored on the handle after it completes. This makes it easy for the callers to check if the thread completed successfully or had an error. The thread_join method uses the handle to block until the thread completes. BUG=b:179699789 TEST=See thread_handle state update and see error code set correctly. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ie6f64d0c5a5acad4431a605f0b0b5100dc5358ff Reviewed-on: https://review.coreboot.org/c/coreboot/+/56229 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-18 17:37:33 +0000