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path: root/src/mainboard/asus/p5qpl-am
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* src/: Replace GPL boilerplate with SPDX headersPatrick Georgi2020-05-092-18/+2
* treewide: replace GPLv2 long form headers with SPDX headerPatrick Georgi2020-05-062-24/+2
* treewide: Move "is part of the coreboot project" line in its own commentPatrick Georgi2020-05-062-4/+2
* acpi: Move ACPI table support out of arch/x86 (3/5)Furquan Shaikh2020-05-022-2/+2
* mainboard/asus: Use SPDX for GPL-2.0-only filesAngel Pons2020-04-067-90/+14
* mb/**/gma-mainboard.ads: Use SPDX for GPL-2.0-or-laterAngel Pons2020-03-201-12/+1
* mainboard/[a-f]*: Remove copyright noticesPatrick Georgi2020-03-1813-20/+0
* mb/asus/p5g41t-m_lx: Do not set BSEL GPIOs in devicetreeAngel Pons2020-03-091-5/+0
* mb/asus/p5g41t-m_lx: Correct GPIO directionAngel Pons2020-03-091-1/+1
* mb/asus/p5qpl-am: Do not set BSEL GPIOs in devicetreeAngel Pons2020-03-091-13/+6
* mb/asus/*/acpi_tables.c: Remove unneeded includesElyes HAOUAS2020-01-131-1/+0
* mb/asus/p5qpl-am/devicetree.cb: Do minor cosmetic fixesAngel Pons2020-01-101-4/+3
* mb/*/*/acpi_tables: Remove unused includesElyes HAOUAS2020-01-021-1/+0
* mb/*/*/acpi_tables: Don't zero out gnvs againPeter Lemenkov2019-12-311-2/+0
* mb/**/dsdt.asl: Remove outdated sleepstates.asl commentAngel Pons2019-12-311-1/+0
* arch/x86: Make X86 stages select ARCH_X86Arthur Heymans2019-12-161-1/+0
* nb/intel/x4x: Move to C_ENVIRONMENT_BOOTBLOCKArthur Heymans2019-11-152-1/+5
* nb/intel/x4x: Move boilerplate romstage to a common locationArthur Heymans2019-11-151-36/+12
* mb/*/*(ich7/x4x): Use common early southbridge initArthur Heymans2019-11-141-17/+1
* sb/intel/i82801gx: Add common LPC decode codeArthur Heymans2019-11-122-14/+3
* mb/{x4x}: Remove unused 'include <northbridge/intel/x4x/iomap.h>'Elyes HAOUAS2019-11-111-1/+0
* mb/*/*{i82801gx}: Use sb/intel/common/acpi/platform.aslArthur Heymans2019-11-042-29/+1
* mb/intel/{i82801gx,x4x}: Don't select ASPM optionsArthur Heymans2019-11-031-3/+0
* soc/intel/{IA-CPU/SOC}: Move sleepstates.asl into southbridge/intel/common/acpiSubrata Banik2019-11-011-1/+1
* sb/intel/i82801gx: Move CIR init to a common placeArthur Heymans2019-10-111-5/+1
* soc/intel: Use common romstage codeKyösti Mälkki2019-08-261-1/+1
* cpu/intel: Enter romstage without BISTKyösti Mälkki2019-08-181-3/+1
* mb/*/*/gpio: Use static for const structuresPeter Lemenkov2019-07-181-7/+7
* sb/intel/i82801gx: Detect if the southbridge supports AHCIArthur Heymans2019-06-061-1/+0
* src/mainboard: Remove unneeded include <arch/io.h>Elyes HAOUAS2019-05-151-1/+0
* src: Remove unused include <halt.h>Elyes HAOUAS2019-05-061-1/+0
* src/mb: Use system_reset()Elyes HAOUAS2019-04-291-2/+2
* sb/intel/i82801gx: Use SOUTHBRIDGE_INTEL_COMMON_PMCLIBPatrick Rudolph2019-04-131-0/+1
* {mb,nb/pineview}/*.asl: Remove unneeded include i82801gx.hElyes HAOUAS2019-03-131-2/+0
* coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)Julius Werner2019-03-081-1/+1
* device/pnp: Add header files for PNP opsKyösti Mälkki2019-03-041-0/+1
* device/pci: Fix PCI accessor headersKyösti Mälkki2019-03-011-0/+1
* mb/{asrock,intel,kontron}: Include missing <arch/io.h>Elyes HAOUAS2019-02-081-8/+9
* src: Remove unused include device/pnp_def.hElyes HAOUAS2019-02-071-1/+0
* mb/asus/p5qpl-am: Add p5g41t-m_lx as a variantAngel Pons2019-01-149-95/+399
* mb: Move timestamp_add_now to northbridge x4xElyes HAOUAS2019-01-101-7/+0
* cpu/intel: Use the common code to initialize the romstage timestampsArthur Heymans2019-01-091-3/+0
* sb/intel/i82801gx: Autodisable functions based on devicetreeArthur Heymans2019-01-081-2/+0
* src/mb/asus/p5qpl-am/romstage.c: Fix commentAngel Pons2019-01-071-1/+1
* arch/x86: Drop spurious arch/stages.h includesKyösti Mälkki2018-12-281-1/+0
* mb/asus/p5qpl-am: Add mainboardArthur Heymans2018-12-2419-0/+878
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