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* Remove various .c #includes from Intel 440BX/82371EB boards.Uwe Hermann2010-10-091-6/+5
| | | | | | | | | | | | | | | | | | | | | | - Use 'romstage-y' to turn i82371eb_early_pm.c and i82371eb_early_smbus.c into distinct compilation units, and don't #include the files anymore in romstage.c files. - Ditto for lib/debug.c, northbridge/intel/i440bx/raminit.c, and northbridge/intel/i440bx/debug.c. - Add various header files which are now needed. - Make functions that need to be visible non-static. - Drop a remaining "select ROMCC" from a 4440BX board. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Idwer Vollering <vidwer@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5929 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Convert all Intel 82371AB/EB/MB based boards to TINY_BOOTBLOCK.Uwe Hermann2010-10-071-4/+0
| | | | | | | | | | | | | | | | | | | | | | | | Also: Unfortunately Intel 440BX + 82371AB/EB/MB boards can have their ISA device on various PCI bus:device.function locations. Examples we encountered: 00:07.0, 00:04.0, or 00:14.0. Thus, instead of hardcoding PCI bus:device.function numbers such as PCI_DEV(0, 7, 0), we now simply find the ISA device via PCI IDs, which works the same on all boards. As an additional benefit this patch also gets rid of one .c file include in romstage.c. Abuild-tested. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5918 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Convert all Intel 440BX boards to Cache-as-RAM (CAR).Uwe Hermann2010-10-062-10/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Add "select CACHE_AS_RAM" in src/cpu/intel/slot_1/Kconfig. - Add the following in src/cpu/intel/slot_1/Makefile.inc: cpu_incs += $(src)/cpu/intel/car/cache_as_ram.inc - Remove "select ROMCC" from all 440BX board Kconfig files. - Drop all early_mtrr_init() calls, that's done by CAR code now. Various small fixes were needed to make it build: - Drop do_smbus_recv_byte(), do_smbus_send_byte(), do_smbus_write_byte(), those were never called anyways. - Remove the "static" from the main() functions in romstage.c files. - Always call dump_spd_registers() from the 440BX debug.c, but use "#if CONFIG_DEBUG_RAM_SETUP" to only have that code if RAM debugging is enabled in menuconfig. - Drop all "lib/ramtest.c" #includes and ram_check() calls (even if commented out) from romstage.c's, as we've done for most other boards. - Add missing #includes or prototypes. Some of the prototypes will be removed later when we get rid of the #include'd .c files. Abuild-tested for all boards, and boot-tested on A-Trend ATC-6220. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Patrick Georgi <patrick@georgi-clan.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5917 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Cut the crap.Uwe Hermann2010-09-211-1/+1
| | | | | | | | | Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5823 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Restructured all vendors' Kconfig files to no longer source the boards'Jens Rottmann2010-08-302-7/+14
| | | | | | | | | | | | | | | | | | | Kconfigs from within the choice/endchoice block. This makes it possible to define user visible board specific options. Moved all vendor names and PCI ids to the vendors' Kconfigs. Now all options in each file depend on the same symbol, so replaced all "depends on"s with a single "if". Sorted boards (sort -d), cleaned whitespace. This patch also introduces a dummy option BOARD_SPECIFIC_OPTIONS, which is always "y" and never used. It it simply needed to have something to attach the boards' "select" statements to. Signed-off-by: Jens Rottmann <JRottmann@LiPPERTEmbedded.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5754 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Re-integrate "USE_OPTION_TABLE" code.Edwin Beasant2010-07-061-5/+0
| | | | | | | | | Signed-off-by: Edwin Beasant <edwin_beasant@virtensys.com> Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5653 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* license header fixes Nils Jacobs2010-05-142-4/+2
| | | | | | | | | Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5545 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Remove pc80/serial.c includes in ROMCC boards and includePatrick Georgi2010-05-091-1/+0
| | | | | | | | | | it centrally in console/console.h instead. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5538 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Drop console/console.c and pc80/serial.c from mainboards'Patrick Georgi2010-05-081-1/+1
| | | | | | | | | | romstage.c. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5528 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Rename "apic" and "apic_cluster" to "lapic" and "lapic_cluster"Patrick Georgi2010-05-051-2/+2
| | | | | | | | | | | in device trees. Adapt sconfig as necessary. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5525 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Since some people disapprove of white space cleanups mixed in regular commitsStefan Reinauer2010-04-271-1/+1
| | | | | | | | | | | | while others dislike them being extra commits, let's clean them up once and for all for the existing code. If it's ugly, let it only be ugly once :-) Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5507 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* This patch drops arch/i386/lib/console.c and arch/i386/lib/console_print.c andStefan Reinauer2010-03-311-1/+1
| | | | | | | | | | | | | | | | | | | | | | makes include/console/console.h and console/console.c usable both in __PRE_RAM__ and coreboot_ram stages. While debugging this, I removed an indirection from the e7520 ram init code (same as we did on a couple of other chipsets, removes some register pressure from romcc) Also, drop remainders of CONFIG_USE_INIT (except the one odd piece of dead code in cache_as_ram.inc) Then some ap_romstage.c fixes, at least the nvidia/l1_2pvv compiled for me with CONFIG_AP_CODE_IN_CAR set in Kconfig which it did not before. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5341 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* This drops the ASSEMBLY define from romstage.c, tooStefan Reinauer2010-03-291-3/+1
| | | | | | | | | | | | | | | | | (since it's not assembly code, this was a dirty hack anyways) Also run awk 1 RS= ORS="\n\n" < $FILE > $FILE.nonewlines mv $FILE.nonewlines $FILE on romstage.c because my perl -pi -e 's,#define ASSEMBLY 1,,g' */*/romstage.c cut some holes into the source. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5320 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* __PRE_RAM__ is now correctly specified in the Makefile. No need to hack it intoStefan Reinauer2010-03-291-1/+1
| | | | | | | | | | | romstage.c anymore Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5315 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Use CPU_INTEL_SLOT_1 for Slot 1 boards (trivial).Uwe Hermann2010-03-132-2/+2
| | | | | | | | | | | This fixes a longstanding TODO item. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5205 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* - make HAVE_HARD_RESET match what newconfig didPatrick Georgi2010-02-271-22/+0
| | | | | | | | | | | | | | | | | | | | | | | - introduce BOARD_HAS_HARD_RESET and use it if a board provides hard_reset in $(MAINBOARDDIR)/reset.c, instead of some chipset component - move a couple of rules out of the mainboards' Makefiles into src/arch/i386/Makefile.inc: initobj-y += crt0.o obj-y += mainboard.o obj-$(CONFIG_GENERATE_MP_TABLE) += mptable.o obj-$(CONFIG_GENERATE_PIRQ_TABLE) += irq_tables.o obj-$(CONFIG_BOARD_HAS_HARD_RESET) += reset.o - remove Makefile.incs that are empty (or comment-only) after these changes, incl. Makefile.romccboard.inc (and references to it) - Make include not fail if Makefile.inc doesn't exist. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Myles Watson <mylesgw@gmail.com> Acked-by: Peter Stuge <peter@stuge.se> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5168 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Move all the copies of the romstage.inc rule toPatrick Georgi2010-02-091-0/+1
| | | | | | | | | | | | | | | | | | | | src/arch/i386/Makefile.inc For that to work, I had to: - Add a CONFIG_ROMCC variable - Set that variable on all ROMCC boards - conditionally choose romcc or gcc rule based on that variable - remove those two rules from all the boards' Makefiles - switch a couple of boards to HAVE_OPTION_TABLE, as they actually have. Also remove the duplication of rules with the sole difference of if they depend on option_table.h or not. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5099 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* janitor task: unify and cleanup naming.Stefan Reinauer2010-02-081-0/+0
| | | | | | | | | | | cache_as_ram_auto.c and auto.c are both called "romstage.c" now. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Patrick Georgi <patrick.georgi@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5092 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* newconfig is no more.Patrick Georgi2010-02-072-223/+0
| | | | | | | | Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5089 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Align several kconfig options to match newconfig:Patrick Georgi2010-01-251-1/+0
| | | | | | | | | | | | | | | | | | | HT_CHAIN_UNITID_BASE HT_CHAIN_END_UNITID_BASE SB_HT_CHAIN_ON_BUS0 SB_HT_CHAIN_UNITID_OFFSET_ONLY MAX_CPUS MAX_PHYSICAL_CPUS ROM_SIZE TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 Also hook up asus/p2b-ds Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5051 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* * Explicitly add __PRE_RAM__ where it should be added.Stefan Reinauer2010-01-051-0/+1
| | | | | | | | | | | | | | * Don't implicitly add __PRE_RAM__ in romcc. Fixes intel/xe7501devkit Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Patrick Georgi <patrick.georgi@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4998 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Move files from src/cpu/x86/{fpu,mmx,sse}/ to x86/Peter Stuge2009-10-171-2/+2
| | | | | | | | Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4803 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Drop enable_mmx.inc. It reads (only) "Enabling mmx registers is a noop"Peter Stuge2009-10-161-1/+0
| | | | | | | | | | abuild tested Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4791 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Set default ROM sizes per-board to match the ROM chip that cameUwe Hermann2009-10-161-0/+1
| | | | | | | | | | | | | with the respective board. Of course, the user can still override the size in menuconfig. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4790 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add CONFIG_GENERATE_* for tables so that the user can select which tables notMyles Watson2009-10-152-6/+6
| | | | | | | | | | | | to build, but by default all the tables that are available are built. Make PIRQ table build for qemu. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4778 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Major CONFIG_IRQ_TABLE_COUNT fixing and cleanups. Some of these boardsUwe Hermann2009-10-071-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | and PIRQ tables were actually wrong, I cannot imagine they ever worked properly. - Use CONFIG_IRQ_TABLE_COUNT in all irq_tables.c files instead of hard-coded numbers. - Make all CONFIG_IRQ_TABLE_COUNT values in irq_tables.c match Options.lb. - Make all CONFIG_IRQ_TABLE_COUNT values match the actual number of entries in the irq_tables.c file. - Set all CONFIG_IRQ_SLOT_COUNT values in src/.../Options.lb for those boards where they were set to 0 (in order to be overridden in the respective targets/.../Config.lb). This is mainly done to aid Patrick's scripts for kconfig conversion. - Fix a number of comments in irq_tables.c files. - Drop CONFIG_IRQ_SLOT_COUNT usage from boards that don't have irq_tables.c: - tyan/s1846 - asus/a8v-e_se - asus/m2v-mx_se Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4739 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* UseUwe Hermann2009-10-061-1/+2
| | | | | | | | | | | | | | | | | select UDELAY_TSC select TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 for all 440BX and i810 boards as per Options.lb. The UDELAY_IO / TSC / LAPIC / HPET setup will probably be checked and improved later when the kconfig transition is done. For now we keep the same values as in Options.lb. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4729 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* PCI_ROM_RUN and CONSOLE_VGA are global options in Kconfig andUwe Hermann2009-10-051-2/+0
| | | | | | | | | | | should not be set in per-mainboard Kconfigs. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4722 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* The new CBFS based build system requires the whole ROM to be accessibleUwe Hermann2009-10-041-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | in very early stages, otherwise the boot may hang like this because the CBFS headers cannot be found/accessed: Uncompressing coreboot to RAM. Jumping to image. Check CBFS header at fffedfe0 magic is ffffffff ERROR: No valid CBFS header found! CBFS: Could not find file fallback/coreboot_ram Jumping to image. This patch enables full ROM access on all 440BX boards right after the serial init (and before CBFS headers are parsed). Build-tested and runtime-tested on ASUS P2B-F. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Patrick Georgi <patrick.georgi@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4721 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* This does away with CONFIG_ROM_PAYLOAD_START and CONFIG_PAYLOAD_SIZE.Patrick Georgi2009-10-041-2/+0
| | | | | | | | | | | | | | Both were only really used in pre-cbfs, as the payload's size isn't relevant for the build process anymore. Various calculations in {no,}failovercalculation.lb are adapted accordingly. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4720 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Remove:Patrick Georgi2009-10-031-6/+0
| | | | | | | | | | | | | | | | | | | | - CONFIG_CBFS - anything that's conditional on CONFIG_CBFS == 0 - files that were only included for CONFIG_CBFS == 0 In particular: - elfboot - stream boot code - mini-filo and filesystems (depends on stream boot code) After this commit, there is no way to build an image that is not using CBFS anymore. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Myles Watson <mylesgw@gmail.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4712 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Remove duplicate and not too useful Kconfig board comments asUwe Hermann2009-10-031-2/+0
| | | | | | | | | | | per discussion on the mailing list. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4711 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* simplify source tree hierarchy: move files from sdram/ and ram/ to lib/Stefan Reinauer2009-09-231-1/+1
| | | | | | | | | | | It's only three files. Also fix up all the paths (Gotta love included C files) Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4661 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add kconfig support for all missing Intel 440BX based boards.Uwe Hermann2009-08-263-1/+104
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This includes: soyo/sy-6ba-plus-iii a-trend/atc-6240 a-trend/atc-6220 gigabyte/ga-6bxc biostar/m6tba azza/pt-6ibd tyan/s1846 abit/be6-ii_v2_0 compaq/deskpro_en_sff_p600msi/ms6119 msi/ms6147 asus/p2b asus/p2b-d asus/p2b-ds asus/p3b-f The Makefile.inc for all of them are _exactly_ the same, so I made a common src/mainboard/Makefile.romccboard.inc (maybe needs a nicer name). I also suspect that many other romcc-based boards will be able to re-use this Makefile.inc. Apart from the board name, most boards only differ in the Super I/O that's being used and the IRQ_SLOT_COUNT value. The Tyan S1846 is a bit different as it doesn't have an irq_tables.c. I also dropped the broken MS-6178 kconfig stuff for now, I'll submit a proper config in another patch. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Myles Watson <mylesgw@gmail.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4587 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Reduce size of the romstage on various boards that fail to build on QA.Patrick Georgi2009-08-192-2/+3
| | | | | | | | | | This eliminates 56kb of padding in the bootblock. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4554 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Kconfig!Patrick Georgi2009-08-122-0/+54
| | | | | | | | | | | | | | | Works on Kontron, qemu, and serengeti. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> tested on abuild only. Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4534 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Enable CBFS everywhere. All boards compiled for me (abuild tested),Patrick Georgi2009-08-111-2/+2
| | | | | | | | | | and we will fix issues as they appear. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4531 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* the tool chain settings should not be in renamed (as they will never live inStefan Reinauer2009-06-301-2/+2
| | | | | | | | | | Kconfig) Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4384 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* This patch unifies the use of config options in v2 to all start with CONFIG_Stefan Reinauer2009-06-304-77/+77
| | | | | | | | | | | | | | | | It's basically done with the following script and some manual fixup: VARS=`grep ^define src/config/Options.lb | cut -f2 -d\ | grep -v ^CONFIG | grep -v ^COREBOOT |grep -v ^CC` for VAR in $VARS; do find . -name .svn -prune -o -type f -exec perl -pi -e "s/(^|[^0-9a-zA-Z_]+)$VAR($|[^0-9a-zA-Z_]+)/\1CONFIG_$VAR\2/g" {} \; done Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4381 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Undo my ugly commit that added uses clauses in lots of places instead of one.Myles Watson2009-06-191-1/+0
| | | | | | | | | | | | | Fix configuration of all boards. (Abuild tested) Hopefully fix compilation of PPC boards (they've never compiled for me.) Apologize profusely. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4367 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Fix configuration of boards that didn't have uses CONFIG_USE_INIT. Trivial.Myles Watson2009-06-171-0/+1
| | | | | | | | | | Abuild tested with -C. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4360 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* When I started refactoring mainboard Config.lb, I added two differentCarl-Daniel Hailfinger2009-06-061-0/+2
| | | | | | | | | | | | | | | | | | | | | | | files for targets without failover: src/config/nofailovercalculation.lb (64 kB XIP) src/config/nofailovercalculation128.lb (128 kB XIP) Targets with other XIP sizes were ignored. This patch moves XIP size back into mainboard code. Benefits from this patch: - src/config/nofailovercalculation128.lb is no longer needed - Targets with XIP sizes besides 64k and 128k benefit from refactoring - Conceptually, this makes the include files pure calculation files without settings. Abuild tested. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Patrick Georgi <patrick.georgi@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4348 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Thanks to Myles' patch adding support for include statements,Carl-Daniel Hailfinger2009-04-211-13/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | refactoring Config.lb became possible. Factor out ROM size calculation from Config.lb. This patch converts 87 boards (with and without USE_FAILOVER_IMAGE), but it has to work around a parser bug. 89 files changed, 209 insertions(+), 2415 deletions(-) A total of 2206 removed lines. Abuild works for all changed boards on khepri. Myles writes: I've tested serengeti for the failover portion and s2892 for the nofailover portion. ldoptions are exactly the same and they both boot the same. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Myles Watson <mylesgw@gmail.com> Acked-by: Peter Stuge <peter@stuge.se> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4147 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* v2/src romfs->cbfs renamePeter Stuge2009-04-141-3/+3
| | | | | | | | | | | | This also has the config tool changes in v2/util. Rename romfs.[ch]->cbfs.[ch] and sed romfs->cbfs romtool->cbfstool ROMFS->CBFS Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4113 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add the CONFIG_ROMS config variable. Ronald G. Minnich2009-03-311-0/+6
| | | | | | | | | | | Tested under abuild, causes no trouble. Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Patrick Georgi <patrick.georgi@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4035 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Carl-Daniel's part:Carl-Daniel Hailfinger2009-02-182-3/+3
| | | | | | | | | | | | | | | This patch converts mainboard_$VENDOR_$BOARD_ops to mainboard_ops and mainboard_$VENDOR_$BOARD_config to mainboard_config. Ron's part: The config change that makes the naming change not break every build. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3954 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Use -O2 and -mcpu=p2 as romcc options for all Intel 440BX boards.Uwe Hermann2008-12-101-4/+4
| | | | | | | | | | | | This should hopefully make the "too few registers" error pop up less often. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Peter Stuge <peter@stuge.se> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3810 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Remove the unnecessary memctrl[] indirection, 440BX only has oneUwe Hermann2008-11-271-10/+4
| | | | | | | | | | | | | memory controller. Also, drop some unused '#if 0' code. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3773 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Drop tons of duplicated debug.c files, move common file toUwe Hermann2008-10-121-1/+1
| | | | | | | | | | | lib/debug.c and use that one. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3653 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* The ARRAY_SIZE macro is convenient, yet mostly unused. Switch lots ofCarl-Daniel Hailfinger2008-10-011-1/+2
| | | | | | | | | | | | | code to use it. That makes the code more readable and also less error-prone. Abuild tested. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3624 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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