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* mb/clevo/l140cu: Use lower-case hex valuesFelix Singer2020-12-081-2/+2
| | | | | | | | | Change-Id: I56a905980e5ae382c3488b9fddb9fab382efc1d6 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48375 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/clevo/l140cu: Remove unnecessary device declarationsFelix Singer2020-12-081-3/+1
| | | | | | | | | | | Remove unnecessary device declarations and remove comments where SMBIOS slot descriptions are used. Change-Id: I3aa3f72de764889becdb0afeb2dac522385d70ef Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48373 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/clevo/l140cu: Use proper indentsFelix Singer2020-12-081-54/+54
| | | | | | | | | | | Use proper indents in the devicetree and align `end` keywords. Change-Id: Id6e6f4ad648a9bed35305b7a446744c6ed06a150 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48372 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/clevo/l140cu: Make PCI devices P2SB and PMC hiddenFelix Singer2020-12-081-2/+2
| | | | | | | | | | | | The PCI devices P2SB and PMC are hidden by the FSP. So instead turning them off, set their state to hidden being able to allocate ressources for them. Change-Id: Ie6e12f99b0a7ffb1c4831b3aa8705e911b677e88 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48371 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/*: Remove unnecessary selectsFelix Singer2020-12-061-1/+0
| | | | | | | | | | | Remove SOC_INTEL_COMMON_BLOCK_HDA from mainboards Kconfig since it is selected by their SoC soc/intel/cannonlake. Change-Id: I9597746a217575b42f6325998b948e16b452231a Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48289 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/clevo/kbl-u: Add a seperate method for early GPIOsFelix Singer2020-12-063-2/+3
| | | | | | | | | | | Add variant_configure_early_gpios() configuring early GPIOs to make the difference clear. Change-Id: I6e7c8c32963c9eeab4399947dac511442987cb45 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48298 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/clevo/kbl-u: Move mainboard/gpio.h to variant/gpio.hFelix Singer2020-12-066-16/+16
| | | | | | | | | | | Move mainboard/gpio.h to variant/gpio.h and rename its methods to make clear that these methods are implemented on variant level. Change-Id: Ibcb6322067285984bad70761fce34cfcb6ed8e0f Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48297 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/clevo/cml-u: Move mainboard/gpio.h to variant/gpio.hFelix Singer2020-12-066-17/+17
| | | | | | | | | | | Move mainboard/gpio.h to variant/gpio.h and rename its methods to make clear that these methods are implemented on variant level. Change-Id: I1ae9b54ed683000f65323b11747ce3280a1c7f2a Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48296 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/clevo/kbl-u: Configure GPIOs using mainboard_opsFelix Singer2020-11-241-2/+6
| | | | | | | | | | | | Hook up the mainboard_ops driver and configure the GPIOs using .init, since mainboard_silicon_init_params() is meant for the configuration of the FSP, not the GPIOs. Change-Id: I82f1eaf6693d9b117fb211776047058cdc787288 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47825 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
* mb/clevo/cml-u: Get rid of gpio.h and use C files insteadFelix Singer2020-11-236-23/+38
| | | | | | | | | | | | | | Split up gpio.h into two seperate compilation units, gpio.c and gpio_early.c, containing the complete configuration and a minimal configuration used in early stages. Tested on clevo/l140cu and it still boots. Change-Id: I5b056e8faac0c426a37501dbc175373c22dde339 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47836 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
* mb/clevo/cml-u: Get rid of cnl_configure_pads()Felix Singer2020-11-231-5/+7
| | | | | | | | | | | | | Get rid of cnl_configure_pads() since it is a hack for the FSP. Instead, hook up to the mainboard_ops driver and configure the GPIOs using .init. Tested on clevo/l140cu and it still boots. Change-Id: I75dd15ab6d2b3b72b3ad0398df87b349fd00bc3c Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47835 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
* mb/clevo/cml-u: Move bootblock.c and ramstage.c to mb levelFelix Singer2020-11-234-2/+4
| | | | | | | | Change-Id: Ifca49c656f259b08fb8ab47fe36e93c146f25266 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47834 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
* mb/clevo/cml-u: Use include folder for header filesFelix Singer2020-11-234-2/+4
| | | | | | | | Change-Id: I50be3d9b829f624cbe460060c40482047f39774c Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47833 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
* mb/clevo/cml-u: Move hda_verb.c to mainboard's MakefileFelix Singer2020-11-232-1/+1
| | | | | | | | | | | Move hda_verb.c from the variant's Makefile to the mainboard's Makefile, because every variant needs one. Change-Id: Ia94813f68620abcff48de4fdb117466c91f6863c Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47820 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/clevo/kbl-u: Add Clevo N130WU/N131WUFelix Singer2020-11-2019-0/+994
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Working: - TianoCore - NVMe, SATA3 - USB2, USB3 - Thunderbolt - Graphics (GOP and libgfxinit) - Sound - Webcam - WLAN, LAN, Bluetooth, LTE - Keyboard, touchpad - TPM - flashrom support; reading / flashing from Linux - ACPI S3 WIP: - Documentation Not working: - EC ACPI (e.g. Fn keys, battery and power information) Boots Arch Linux (Linux 5.8.12) successfully. Change-Id: I364f5849ef88f43b85efbd7a635a27e54d08c513 Signed-off-by: Felix Singer <felixsinger@posteo.net> Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/28640 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
* mb/clevo/cml-u/l140cu: Extend Kconfig option text with L141CUFelix Singer2020-11-191-1/+1
| | | | | | | | | | | | Extend the Kconfig option text of L140CU with L141CU since the hardware of both is equal. Change-Id: If0e5061fc345208688a678a4cdf7c5ecaf47c17d Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47716 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
* mb/clevo/cml-u: Add comment to board selectionFelix Singer2020-11-191-0/+2
| | | | | | | | | Change-Id: I531865416b1bf9c5a73c809590059e7d7c8f373a Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47715 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/clevo/cml-u: Fix up comment styleAngel Pons2020-11-131-1/+1
| | | | | | | | | Change-Id: Idefc15fec1d62d68d88e91c76f59e1a60a3996b6 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47564 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/clevo/l140cu: add CMOS layout and defaultsMichael Niewöhner2020-11-123-0/+66
| | | | | | | | | | | | Add CMOS layout and defaults files and enable CMOS options in Kconfig. Test: changed loglevel setting, rebooted and checked the log. Change-Id: Ia1a27818b2d12fb7578189e5748b8073c8f928e3 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46311 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/*/Kconfig: Annotate closing endif with corresponding conditionPaul Menzel2020-11-121-1/+1
| | | | | | | | | | | | It’s common to annotate the closing endif, so do it for these four files. Change-Id: Ia5d071e1f544c9dea5af9c6bc3c605d9a0c5c0f5 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47477 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
* mb, soc/intel: Reorganize CNVi device entries in devicetreeFurquan Shaikh2020-11-021-4/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | This change reorganizes the CNVi device entries in mainboard devicetree/overridetree and SoC chipset tree to make it consistent with how other SoC internal PCI devices are represented i.e. without a chip driver around the SoC controller itself. Before: chip drivers/wifi/generic register "wake" = "..." device pci xx.y on end end After: device pci xx.y on chip drivers/wifi/generic register "wake" = "..." device generic 0 on end end end Change-Id: I22660047a3afd5994400341de0ca461bbc0634e2 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46865 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
* mb/*,soc/intel: drop the obsolete dt option `speed_shift_enable`Michael Niewöhner2020-10-261-3/+0
| | | | | | | | | | | The dt option `speed_shift_enable` is obsolete now. Drop it. Change-Id: I5ac3b8efe37aedd442962234478fcdce675bf105 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46462 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
* {src/mb,util/autoport}: Use macro for DSDT revisionElyes HAOUAS2020-10-131-1/+1
| | | | | | | | Change-Id: I5a5f4e7067948c5cc7a715a08f7a5a3e9b391191 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45904 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
* mb, soc/intel: Switch to using drivers/wifi/generic for Intel WiFi devicesFurquan Shaikh2020-10-131-2/+2
| | | | | | | | | | | | | | | | | | | | This change switches all mainboard devices to use drivers/wifi/generic instead of drivers/intel/wifi chip driver for Intel WiFi devices. There is no need for two separate chip drivers in coreboot to handle Intel and non-Intel WiFi devices since the differences can be handled at runtime using the PCI vendor ID. This also allows mainboard to easily multi-source WiFi chips and still use the same firmware image without having to distinguish between the chip drivers. BUG=b:169802515 BRANCH=zork Change-Id: Ieac603a970cb2c9bf835021d1fb0fd07fd535280 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46035 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
* mb/clevo/l140cu: clean up memcfgMichael Niewöhner2020-10-121-51/+5
| | | | | | | | | | | | | | | | The DQ and DQS byte maps do not apply to DDR4 configurations, thus simply drop them. Also drop ECT, as it's already initialized to zero and can't be used on DDR4 anyway. Further, trim down all the meaningless and/or wrong comments. Change-Id: I32f1b7bb46eaaf0f0ecad1df310f5de988f64c85 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46249 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/clevo/l140cu: drop disabled SPD indicesMichael Niewöhner2020-10-121-3/+0
| | | | | | | | | | | | Drop the disabled SPD indices from memcfg, since they're already initialized to 0. Change-Id: I6d88bdac17222c2c5c35439517fe0bea46744b2b Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46248 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* mb/clevo/l140cu: drop USE_LEGACY_8254_TIMERMichael Niewöhner2020-10-121-1/+0
| | | | | | | | | | | | | | | | | | | Drop USE_LEGACY_8254_TIMER, since it's not required anymore for booting grub, despite the comment. The issue was resolved upstream five years ago: http://git.savannah.gnu.org/cgit/grub.git/commit/?id=d43a5ee65143f384357fbfdcace4258e3537c214 Test: - Boot EFI GRUB2 from TianoCore payload (Debian Live, Ubuntu installer) - Boot GRUB2 payload Change-Id: I5ce4f5168586bf305969b2e24b6ee895c8552749 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45960 Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/clevo/l140cu: set PS/2 timeout for SeaBIOSMichael Niewöhner2020-10-121-0/+5
| | | | | | | | | | | | | | | | | The keyboard only works randomly, because SeaBIOS initializes PS/2 before the EC is ready. Set the PS/2 timeout for SeaBIOS to 500 ms, to wait for the EC before initializing the keyboard. Test: keyboard works fine. Change-Id: I2be75961035f04a7ffa6f7e1dbaabb1243b857f9 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45959 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/common/block/acpi: Factor out common platform.aslSubrata Banik2020-10-051-1/+1
| | | | | | | | | | | | | | | | | This patch moves platform.asl into common block acpi directory to avoid duplicating the same ASL code block across SoC directory. TEST=Able to build and boot TGL, CNL and CML platform. 1) Dump and disassemble DSDT, verify _PIC method present inside common platform.asl is still there. 2) Verify no ACPI error seen while running 'dmesg` from console. Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: I5189b03d6abfaec39882d28b40a9bfa002128be3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45982 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* mb/clevo/l140cu: Add variant specific romstage.c to buildFelix Singer2020-10-021-0/+1
| | | | | | | | | | | | While restructuring the mainboard directory, it was forgotten to add the variant specific romstage.c to the build. Therefore, add romstage.c to the Makefile fixing the raminit. Change-Id: I7afbf1574803128f7d62592eed2398c945334757 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45928 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/clevo/l140cu: Align comment with rest of the devicetreeFelix Singer2020-10-011-2/+2
| | | | | | | | Change-Id: Idcaedd3d5b7e465644f79e5a882e42eff040fdbd Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45884 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
* mb/clevo/cml-u: drop PcieRpSlotImplemented for card readerMichael Niewöhner2020-09-291-1/+0
| | | | | | | | | | | | PcieRpSlotImplemented should only be set to 1 for PCIe ports implementing a PCIe slot. Drop it for the on-board card reader. Change-Id: I22628b4d4a7e317a01e46a61b5cd7bb9ebf548a0 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45776 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* mb/clevo/cml-u/Kconfig: Remove MAINBOARD_SMBIOS_PRODUCT_NAMEElyes HAOUAS2020-09-281-4/+0
| | | | | | | | | | MAINBOARD_SMBIOS_PRODUCT_NAME is duplicated. Change-Id: I011f83c4d4e0657256839db207bfd1517922744c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45758 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* mb/clevo/cml-u: remove the duplicate WiFi PCIe device in devicetreeMichael Niewöhner2020-09-251-4/+3
| | | | | | | | Change-Id: Ibb46bbf0c889bb8b3fd1a4c0331dc719baffc7a2 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45678 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/clevo: Rename l140cu to cml-uFelix Singer2020-09-2518-1/+1
| | | | | | | | | | | In addition to CB:45664, rename clevo/l140cu to clevo/cml-u being able to add more variants under a generic mainboard later. Change-Id: I9c16e24830ebb80752df302aa2e63d9df8edad95 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45665 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/clevo/l140cu: Make usage of variant mechanismFelix Singer2020-09-2412-13/+22
| | | | | | | | | | | | | | | Clevo mainboards can be grouped by their common platform. Therefore, restructure the mainboard directory as a first step, so that the variant mechanism is used. This moves most of the code into the variant dir, since the L140CU is the only variant at the moment. Change-Id: I9ad1c06f9db854cac1dd420c53dc0c9f010ed716 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45664 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb: Copy system76/lemp9 to clevo/l140cuFelix Singer2020-09-2418-0/+814
Copy system76/lemp9 to clevo/l140cu, since it's a Clevo notebook actually and both have the same mainboard. This commit is meant to create a working copy for clevo/l140cu. The only changes are names. Further patches will follow to make this mainboard more generic. Since system76/lemp9 is based on System76's EC firmware, EC stuff does not work correctly yet. This will be fixed in another patch. Tested on TUXEDO InfinityBook S 14 v5 and PCZ Lafité Pro 14. Change-Id: I7c2993256fd9123a8013df5ba8292ea1ead10f74 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45624 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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