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* soc/intel/cannonlake: Set MAX_CPUS based on the SoC and PCHFelix Singer2022-07-231-4/+0
| | | | | | | | | | | | Set the default value for MAX_CPUS in the SoC config and drop it from the mainboards where it is set to those values. Change-Id: Ib56fdcfe770ef736a2c5e183481d9f9966570e6d Signed-off-by: Felix Singer <felixsinger@posteo.net> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52607 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* ec/system76/ec: Provide charging thresholds by defaultTim Crawford2022-07-161-0/+3
| | | | | | | | | | | | | | Battery charging thresholds are a firmware implementation and not dependent on any hardware. It is expected that all boards using System76 EC firmware will select this option, so enable it by default. Leave it disabled on clevo/cml-u, which didn't have it selected. Change-Id: Id99d36eaf055a76b9e1eb732174017651de299a5 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65714 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
* soc/intel/tigerlake: Add enum for `DdiPortXConfig`Angel Pons2022-05-051-2/+2
| | | | | | | | | | | | | | Add an enum for `DdiPortXConfig` devicetree options. Note that setting these options to zero does not disable the corresponding DDI port, but instead indicates that no LFP (Local Flat Panel, i.e. internal LCD) is connected to it. Change-Id: I9ea10141e51bf29ea44199dcd1b55b63ec771c0a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64047 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Tim Crawford <tcrawford@system76.com>
* tpm: Refactor TPM Kconfig dimensionsJes B. Klinke2022-04-213-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Break TPM related Kconfig into the following dimensions: TPM transport support: config CRB_TPM config I2C_TPM config SPI_TPM config MEMORY_MAPPED_TPM (new) TPM brand, not defining any of these is valid, and result in "generic" support: config TPM_ATMEL (new) config TPM_GOOGLE (new) config TPM_GOOGLE_CR50 (new, implies TPM_GOOGLE) config TPM_GOOGLE_TI50 (new to be used later, implies TPM_GOOGLE) What protocol the TPM chip supports: config MAINBOARD_HAS_TPM1 config MAINBOARD_HAS_TPM2 What the user chooses to compile (restricted by the above): config NO_TPM config TPM1 config TPM2 The following Kconfigs will be replaced as indicated: config TPM_CR50 -> TPM_GOOGLE config MAINBOARD_HAS_CRB_TPM -> CRB_TPM config MAINBOARD_HAS_I2C_TPM_ATMEL -> I2C_TPM && TPM_ATMEL config MAINBOARD_HAS_I2C_TPM_CR50 -> I2C_TPM && TPM_GOOGLE config MAINBOARD_HAS_I2C_TPM_GENERIC -> I2C_TPM && !TPM_GOOGLE && !TPM_ATMEL config MAINBOARD_HAS_LPC_TPM -> MEMORY_MAPPED_TPM config MAINBOARD_HAS_SPI_TPM -> SPI_TPM && !TPM_GOOGLE && !TPM_ATMEL config MAINBOARD_HAS_SPI_TPM_CR50 -> SPI_TPM && TPM_GOOGLE Signed-off-by: Jes B. Klinke <jbk@chromium.org> Change-Id: I4656b2b90363b8dfd008dc281ad591862fe2cc9e Reviewed-on: https://review.coreboot.org/c/coreboot/+/63424 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* mb/clevo/tgl-u: add new board L14xMUMichael Niewöhner2022-04-0123-0/+888
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add new board Clevo L14xMU (TGL). GPIOs were configured based on schematics. Tested and working: - On-board RAM (M471A1G44AB0-CWE) - DIMM slot (tested Crucial CT16G4SFD8266.16FJ1 / MTA16ATF2G64HZ-2G6J1) - Graphics (GOP driver), including HDMI - Keyboard - I2C touchpad (including interrupt) - TPM (with interrupt on Windows, only polling on Linux [1]) - microSD Card reader - both NVME ports - Speakers - Microphone - Camera - WLAN/BT (CNVi) - All USB2/3 ports including Type-C - Thunderbolt detects my work laptop in TB Control Center (I couldn't test anything more due to security policy.) - TianoCore - internal flashing with flashrom on vendor firmware Note on TPM: The vendor sets Intel PTT to default-on in newer CSME images, which conflicts with the dTPM. Currently, there are two ways to make it work: 1) Boot vendor firmware once to let it disable PTT via CSME firmware feature override. 2) Use Intel Flash Image Tool (FIT) to set "initial power-up state" to disabled. Boots fine: - Debian testing, unstable (Linux 5.16.14, 5.17.0-rc6) - Windows 10 21H2 (Build 19044.1586) Untested: - Thunderbolt (see above) - Type-C DisplayPort - S-ATA Doesn't work: - TPM interrupt on Linux [1] - All EC related functions - EC driver is WIP - WLAN/BT (PCIe) - gets detected but can't be enabled - 3G/LTE (not powered without EC driver) - Fn-Keys - S0ix - UCSI - Fan control - Battery info [1] https://lkml.org/lkml/2021/5/1/103 Change-Id: I4c4bef3827da10241e9b01e12ecc4276e131a620 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59548 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* soc/intel/skl: Replace dt `HeciEnabled` by `HECI1 disable` configSubrata Banik2022-01-161-3/+1
| | | | | | | | | | | | | | | | | | | | | List of changes: 1. Drop `HeciEnabled` from dt and dt chip configuration. 2. Replace all logic that disables HECI1 based on the `HeciEnabled` chip config with `DISABLE_HECI1_AT_PRE_BOOT` config. 3. Make dt CSE PCI device `on` by default. 4. Mainboards set DISABLE_HECI1_AT_PRE_BOOT=y to make Heci1 function disable at pre-boot instead of the dt policy that uses `HeciEnabled = 0`. Mainboards that choose to make HECI1 enable during boot don't override `heci1 disable` config. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I5c13fe4a78be44403a81c28b1676aecc26c58607 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60722 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* soc/intel/skylake: switch to common GNVSMichael Niewöhner2021-10-171-1/+1
| | | | | | | | | | | | | | Switch to common GNVS. No additional fields to those being present in common GNVS are used by any SKL/KBL device. Thus, they're dropped completely. Change-Id: I87ab4ab05f6c081697801276a744d49e9e1908e0 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57946 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
* skylake DDR4 boards: Set `CaVrefConfig` to 2Angel Pons2021-09-171-0/+1
| | | | | | | | | | | | | | | | | | | | | | The `CaVrefConfig` FSP-M UPD describes how the on-die Vref generators are connected to the DRAM. With the exception of an early Skylake RVP board (which doesn't have coreboot support), mainboards using DDR3 or LPDDR3 memory should set `CaVrefConfig` to 0, whereas mainboards with DDR4 should set `CaVrefConfig` to 2. MRC uses this information during memory training, so it is important to use the correct value to avoid any issues, such as increased power usage, system instability or even boot failures. However, several Skylake DDR4 mainboards don't set `CaVrefConfig` to 2. Although they can boot successfully, it's not optimal. For boards that set `DIMM_SPD_SIZE` to 512 (DDR4 SPD size), set `CaVrefConfig` to 2. Change-Id: Idab77daff311584b3e3061e9bf107c2fc1b7bdf1 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57262 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
* src/*: Specify type of `DIMM_MAX` onceAngel Pons2021-09-032-2/+0
| | | | | | | | | | | Specify the type of the `DIMM_MAX` Kconfig symbol once. Change-Id: I2e86baaa8bd50c7b82c399fde5dcea05da6b4307 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57258 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Crawford <tcrawford@system76.com> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* src/*: Specify type of `DIMM_SPD_SIZE` onceAngel Pons2021-09-031-1/+0
| | | | | | | | | | | Specify the type of the `DIMM_SPD_SIZE` Kconfig symbol once. Change-Id: I619833dbce6d2dbe414ed9b37f43196b4b52730e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57257 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* soc/intel/common: Use CHIPSET_LOCKDOWN_COREBOOT by defaultFelix Singer2021-08-282-5/+0
| | | | | | | | | | | | | | | | | | | | | Since all mainboards use `CHIPSET_LOCKDOWN_COREBOOT`, make it the default by changing its enum value to 0 and remove its configuration from all related devicetrees. If `common_soc_config.chipset_lockdown` is not configured with something else in the devicetree, then `CHIPSET_LOCKDOWN_COREBOOT` is used. Also, add a release note for the upcoming 4.15 release. Change-Id: I369f01d3da2e901e2fb57f2c83bd07380f3946a6 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56967 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Tim Crawford <tcrawford@system76.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
* mb/*: Specify type of `VARIANT_DIR` onceAngel Pons2021-07-262-2/+0
| | | | | | | | | | | | | | | Specify the type of the `VARIANT_DIR` Kconfig symbol once instead of doing so on each and every mainboard. Change-Id: Iea2f992a59e41e00fec3cdc9d6a13b5f3ab0a437 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56558 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/*: Specify type of `FMDFILE` onceAngel Pons2021-07-261-1/+0
| | | | | | | | | | | | | | Specify the type of the `FMDFILE` Kconfig symbol once instead of doing so on each and every mainboard. Change-Id: I810bd3fe8d42102586db6c2c58b7037a60189257 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56557 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/*: Specify type of `DEVICETREE` onceAngel Pons2021-07-262-2/+0
| | | | | | | | | | | | | | Specify the type of the `DEVICETREE` Kconfig symbol once instead of doing so on each and every mainboard. Change-Id: If68f11a5ceaa67a3e8218f89e1138c247ebb9a25 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56555 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/*: Specify type of `MAINBOARD_PART_NUMBER` onceAngel Pons2021-07-262-2/+0
| | | | | | | | | | | | | | | | Specify the type of the `MAINBOARD_PART_NUMBER` Kconfig symbol once instead of doing so on each and every mainboard. Change-Id: I3692f9e82fe90af4d0da1d037018a20aa1b45793 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56554 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/*: Specify type of `MAINBOARD_DIR` onceAngel Pons2021-07-262-2/+0
| | | | | | | | | | | | | | | | Specify the type of the `MAINBOARD_DIR` Kconfig symbol once instead of doing so on each and every mainboard. Change-Id: If1cc538b0c4938dac193699897b690e402b3c1e8 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56553 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* src/*: Specify type of `CBFS_SIZE` onceAngel Pons2021-07-262-2/+0
| | | | | | | | | | | | | | | | There's no need to specify the type of the `CBFS_SIZE` Kconfig symbol more than once. This is done in `src/Kconfig`, along with its prompt. Change-Id: I9e08e23e24e372e60c32ae8cd7387ddd4b618ddc Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56552 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Kconfig: Escape variablesPatrick Georgi2021-06-292-5/+5
| | | | | | | | | | | New kconfig parsers interpret $(var) themselves, leading to empty fields. Old kconfig understands \$(var), so use that. Change-Id: I927fc9dc7a66211bfe51d4324cf7c51b555ea3a8 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55912 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/clevo/n130wu: Use device alias names in devicetreeFelix Singer2021-05-141-18/+18
| | | | | | | | | | | Switch to device alias names in devicetree. Remove unnecessary comments since the names are self-explanatory. Change-Id: Id486d9bd44bd7ba6a93a5f757af487b211e58efa Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/53939 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
* mb/clevo/cml-u/cmos.layout: Align contents with tabsAngel Pons2021-04-241-21/+21
| | | | | | | | | | | Replace spaces with tabs for consistency with other mainboards. Change-Id: Ia4042ecf7c62490b0a50bc42d5ddddd5872bf036 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52633 Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/cannonlake: Set DIMM_SPD_SIZE to 512Felix Singer2021-04-221-4/+0
| | | | | | | | | | | | | All related mainboards are setting DIMM_SPD_SIZE to 512. Therefore, default to 512 in the SoC Kconfig and drop it from related mainboard Kconfigs. Change-Id: Idb6a0e42961eeb490afd76b4aa7d940961991733 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52513 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/clevo/cml-u/Kconfig: Use BOARD_CLEVO_L140CU_BASEFelix Singer2021-04-191-6/+6
| | | | | | | | | | | | | | | To make the L140CU able to be selected by other OEMs, use BOARD_CLEVO_L140CU_BASE for OEM independent options. BOARD_CLEVO_L140CU represents the standard Clevo mainboard without any OEM modifications, while BOARD_CLEVO_L140CU_BASE is used for the baseboard. Change-Id: Iee82eadebfc851619dbb64de09283c5ee55a499f Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52241 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/clevo/cml-u: Rename `BOARD_CLEVO_L140CU_OPTIONS`Felix Singer2021-04-192-2/+2
| | | | | | | | | | | Rename `BOARD_CLEVO_L140CU_OPTIONS` to `BOARD_CLEVO_L140CU_BASE` to make clear that this option represents the baseboard. Change-Id: I76690626fddafc8e3c37ef760aeb4f064fb6b591 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52480 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/clevo/kbl-u: Move memory init config to variant levelFelix Singer2021-04-194-30/+50
| | | | | | | | | | | Memory init config is board specific. Thus, move it to variant level and hook up variant romstage.c. Change-Id: Id78788815ad9c4ed64f0172fb746ff6e50d608ef Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49132 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
* mb/clevo/kbl-u: Clean up codeFelix Singer2021-04-191-3/+2
| | | | | | | | Change-Id: I98d806ebf126522689b2c101b75add733825fcf1 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49133 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
* mb/clevo/l140cu: Move FSP-M config hook to mainboard levelFelix Singer2021-04-195-3/+22
| | | | | | | | | | | | | | Hook up FSP-M configuration on mainboard level instead of variant level being able to do common configuration there. Also, hook up variant romstage.c on mainboard level for variant specific configurations. Change-Id: Ic161f83cb629b1e70ca670e10975a25bc0949656 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49077 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
* mb/clevo/cml-u/l140cu: correct pad GPP_A11 (INTP_OUT)Michael Niewöhner2021-04-161-3/+1
| | | | | | | | | | | | | This pad is connected to INTP_OUT of the Type-C PD controller. Correct the comment. Also remove the unneeded pull-up. Checked with schematics. Change-Id: I33a5f177affc3f13d091a85073499b7283f54ada Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52169 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/clevo/cml-u: drop LPC generic range for port 80Michael Niewöhner2021-04-131-5/+3
| | | | | | | | | | | | Port 80 (actually 0x80-0x8f) is a fixed I/O range and thus does not have to be set up as generic range. Drop the entry from clevo/cml-u, which has been forgotten in commit c5f1dc9. Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: I05844db4cfe96e6075bd6526ffc242973a2082c2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52271 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* mb/*: drop LPC generic range for port 80Michael Niewöhner2021-04-121-2/+1
| | | | | | | | | | | Port 80 (actually 0x80-0x8f) is a fixed I/O range and thus does not have to be set up as generic range. Drop the entries from the devicetrees. Change-Id: I8a54d3c35a321a2d57bd846662f7339eff53e5a8 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52237 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* soc/intel/{cannonlake,icelake}: Drop unhooked `SendVrMbxCmd`Angel Pons2021-04-081-3/+0
| | | | | | | | | | | This option's value is not used anywhere. Remove it. Change-Id: I0f30cddd30d459f48b51f377b111bbc04709c5f8 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52102 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
* mb/clevo/cml-u: acpi: Remove unused EC defineTim Crawford2021-04-061-1/+0
| | | | | | | | | | | | The define for color keyboard setting has never been used, as it was added as a Kconfig selection when ec/system76/ec was introduced. Change-Id: I6c8f17b398fb4645feb830c2ad28ac98fb744280 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51945 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
* mb/{clevo/cml-u,system76/lemp9}: Clarify `gen2_dec` useAngel Pons2021-03-191-1/+1
| | | | | | | | | | | | This I/O range is for a PM channel on the EC, not the PCH PMC. Change-Id: I64422e537c1edcd0673cf87f16139fb117b10e75 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51604 Reviewed-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/clevo/cml-u/bootblock.c: Remove unused includesElyes HAOUAS2021-02-041-1/+0
| | | | | | | | | Change-Id: I048e906306bf77a941b5f731ade15292fa944390 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50219 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
* ACPI: Add top-level ASLKyösti Mälkki2021-01-272-0/+2
| | | | | | | | | | | | | | | | | | | Objects that are created with acpigen need to be declared with External () for the generation of dsdt.asl to pass iasl without errors. There are some objects that are common to all platforms, and some that should be declared only conditionally. Having a top-level ASL helps to achieve this. Change-Id: Ibaf1ab9941b82f99e5fa857c0c7e4b6192c74330 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49794 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* mb/clevo: Drop redundant `select HAVE_SMI_HANDLER`Angel Pons2021-01-272-2/+0
| | | | | | | | | | Already selected from SoC Kconfig. Change-Id: I131f435ab0a30e33a70773a99c60284f8b9c82c8 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49910 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* mb/clevo/cml-u: Drop VGA_BIOS_FILE from KconfigFelix Singer2021-01-081-4/+0
| | | | | | | | | | | | It doesn't make sense to configure that filename in Kconfig, since the filename can be changed by the user. So remove it. Change-Id: I3eed05637da29096bc1d134505d7335db5db1439 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49138 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/skylake: Move MAX_CPUS from mb to SoCFelix Singer2021-01-061-4/+0
| | | | | | | | | | | | | | | Configure MAX_CPUS in SoC Kconfig with 8 as default value and remove it from every mainboard where 8 is used. Change-Id: I825625bf842e8cd22dada9a508a7176e5cc2ea57 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49105 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/clevo/cml-u: Rework KconfigFelix Singer2021-01-052-6/+11
| | | | | | | | | | | | | | Rework Kconfig file so that each variant has its own config option with their specific selects / configuration and move common selects to a seperate config option, which is used as base for each variant. Built clevo/l140cu with BUILD_TIMELESS=1, coreboot.rom remains the same. Change-Id: I1f5b6f535597149f28dd8c8322acc2e988f11505 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49025 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
* mb/clevo/kbl-u: Rework KconfigFelix Singer2021-01-052-4/+9
| | | | | | | | | | | | | | | Rework Kconfig file so that each variant has its own config option with their specific selects / configuration and move common selects to a seperate config option, which is used as base for each variant. Built clevo/n130wu with BUILD_TIMELESS=1, coreboot.rom remains the same. Change-Id: I1f07b5851ece6d0943faa9c90fc518805880a27d Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49060 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Daniel Maslowski <info@orangecms.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/clevo/cml-u: Configure IRQ as level triggered for HID over I2CMichael Niewöhner2021-01-042-2/+2
| | | | | | | | | | | | | | | | | | | As per HID over I2C Protocol Specification[1] Version 1.00 Section 7.4, the interrupt line used by the device is required to be level triggered. Hence, this change updates the configuration of the HID over I2C devices to be level triggered. References: [1] http://download.microsoft.com/download/7/d/d/7dd44bb7-2a7a-4505-ac1c-7227d3d96d5b/hid-over-i2c-protocol-spec-v1-0.docx [2] https://review.coreboot.org/c/coreboot/+/47417/2/src/mainboard/google/hatch/variants/baseboard/gpio.c#b182 Tested successfully on Clevo L141CU. Change-Id: Ia232c0a11546aa6d17614f4cab07c255e58f2fed Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47984 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* mb/clevo/l140cu: add libgfxinit supportMichael Niewöhner2021-01-033-0/+20
| | | | | | | | | | Change-Id: Id58bb2ce5fdaeaf158d02d8c812ab2c331db352d Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48751 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/clevo/l140cu: add panel settings to the dt and hook up GMA ACPIMichael Niewöhner2021-01-032-1/+12
| | | | | | | | | | | | | | | | Add the panel settings dumped from vendor firmware and hook up drivers/intel/gma, which will be required for brightness control. Keyboard brightness control still requires ACPI code. This will be done in a separate change later. Test: Panel gets enabled when the payload starts on Clevo L141CU. Change-Id: I7977a2271da72c142b025b4631318d1a39adfb13 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48750 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* nb/intel/hsw,soc/intel/{bdw,skl,apl},mb/*: unify dt panel settingsMichael Niewöhner2021-01-011-7/+8
| | | | | | | | | | | | | | | | | | | | There are multiple different devicetree setting formats for graphics panel settings present in coreboot. Replace the ones for the platforms that already have (mostly) unified gma/graphics setup code by a unified struct in the gma driver. Hook it up in HSW, BDW, SKL, and APL and adapt the devicetrees accordingly. Always ensure that values don't overflow by applying appropriate masks. The remaining platforms implementing panel settings (GM45, i945, ILK and SNB) can be migrated later after unifying their gma/graphics setup code. Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: I445defe01d5fbf9a69cf05cf1b5bd6c7c2c1725e Reviewed-on: https://review.coreboot.org/c/coreboot/+/48885 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
* mb/clevo/n13xwu: Disable GMM PCI deviceFelix Singer2020-12-291-1/+0
| | | | | | | | | | | We don't know exactly for what the GMM PCI device is used for or how it is used. Thus, remove it to fallback to default-disable. Change-Id: I4b8b33b16527cbcc21168b995cbfdb54a2fa3cac Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48920 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
* mb/clevo/n130xu: Remove disabled devices from devicetreeFelix Singer2020-12-291-31/+0
| | | | | | | | | | | | All known on-chip PCI devices are documented in chipset devicetree now and default to disabled. There is no need to keep disabled PCI devices in the mainboard's devicetree. Thus, remove them. Change-Id: I7c537bba75d66badf854f9e7b6799303a7af018e Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48891 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
* mb/clevo/cml-u: Reorder selects alphabeticallyFelix Singer2020-12-231-2/+2
| | | | | | | | Change-Id: Idd02573e6b47c3bcbdcefa7b04fb9098b600df49 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48804 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
* mb/clevo/cml-u: move gpio early init to bootblock_mainboard_early_initMichael Niewöhner2020-12-221-1/+1
| | | | | | | | | | | Move gpio early init to bootblock_mainboard_early_init to make the bootblock console work as early as possible. Change-Id: I619f7d0e15adae284b606dd20c3c1f04f3eafd7b Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48801 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Revert "mb/clevo/cml-u: drop duplicated configuration of UART pads"Felix Singer2020-12-224-0/+31
| | | | | | | | | | | | | | This reverts commit 1a0071c7115819302c7df3fa2c07b1ca971e515d. Reason for revert: UART pad configuration should not be done in common code, since it could cause short circuits if the user configures a wrong UART index. Change-Id: I6022935eaab748f82c6330be0729ff72f4880493 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48328 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
* Revert "mb/clevo/kbl-u: drop duplicated configuration of UART pads"Felix Singer2020-12-214-0/+30
| | | | | | | | | | | | | | This reverts commit ccceb2250eeb820fccfb62d1f3ab407582d2e79f. Reason for revert: UART pad configuration should not be done in common code, since it could cause short circuits if the user configures a wrong UART index. Change-Id: Idc268debc60a027ed2f5a76e0de8ea2d1cde0fc4 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48327 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
* mb/clevo/kbl-u: drop duplicated configuration of UART padsMichael Niewöhner2020-12-204-30/+0
| | | | | | | | | | | UART pads already get configured in bootblock by the UART driver in soc code. Thus, drop the duplicated code from the mainboard. Change-Id: I95565a74e19d693a7d5ead81e72592cc4ca2038c Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48594 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-17 15:22:11 +0000