| Commit message (Collapse) | Author | Age | Files | Lines |
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All Broadwell boards only use the `mainboard_pre_raminit` function to
call `mainboard_fill_pei_data` and optionally `mainboard_fill_spd_data`.
Move the declaration and weak definition of `mainboard_fill_spd_data` to
platform code, replace the call to `mainboard_pre_raminit` in romstage.c
with calls to `mainboard_fill_pei_data` and `mainboard_fill_spd_data`,
and delete all other instances of `mainboard_pre_raminit` for Broadwell.
Finally, delete now-empty romstage.c and spd.h files from mainboards.
Change-Id: I3334b20bd7138bb753b996a137ff106e87c6e8a5
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49776
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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Replace it with `mainboard_post_raminit`.
Change-Id: I94636c775cee6c14317ecff36972e2d267d28c91
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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The code to read the SPD file and index it is not variant-specific.
Change-Id: Iaee0a77934a45c65bf32dd0dba23cec654abc0b9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49773
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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It is identical for all variants that have it.
Change-Id: Iec3a5f036d9b760d1075059f2db1480b1c76273e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49772
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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Factor out common DRAM SPD definitions and relocate SPD GPIO macros.
Also factor out common function definition. Drop now-empty headers.
Change-Id: Id05ba6c9cea27fbad5ee831f033d0de43717847e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49770
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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Stefan thinks they don't add value.
Command used:
sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool)
The exceptions are for:
- crossgcc (patch file)
- gcov (imported from gcc)
- elf.h (imported from GNU's libc)
- nvramtool (more complicated header)
The removed lines are:
- fmt.Fprintln(f, "/* This file is part of the coreboot project. */")
-# This file is part of a set of unofficial pre-commit hooks available
-/* This file is part of coreboot */
-# This file is part of msrtool.
-/* This file is part of msrtool. */
- * This file is part of ncurses, designed to be appended after curses.h.in
-/* This file is part of pgtblgen. */
- * This file is part of the coreboot project.
- /* This file is part of the coreboot project. */
-# This file is part of the coreboot project.
-# This file is part of the coreboot project.
-## This file is part of the coreboot project.
--- This file is part of the coreboot project.
-/* This file is part of the coreboot project */
-/* This file is part of the coreboot project. */
-;## This file is part of the coreboot project.
-# This file is part of the coreboot project. It originated in the
- * This file is part of the coreinfo project.
-## This file is part of the coreinfo project.
- * This file is part of the depthcharge project.
-/* This file is part of the depthcharge project. */
-/* This file is part of the ectool project. */
- * This file is part of the GNU C Library.
- * This file is part of the libpayload project.
-## This file is part of the libpayload project.
-/* This file is part of the Linux kernel. */
-## This file is part of the superiotool project.
-/* This file is part of the superiotool project */
-/* This file is part of uio_usbdebug */
Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Done with sed and God Lines. Only done for C-like code for now.
Change-Id: I890c2367799196e0b9f986d95bcda1d9090a694d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40143
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Change-Id: I91158452680586ac676ea11c8589062880a31f91
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31692
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Use of device_t is deprecated.
Change-Id: I564319506870f75eab58cce535d4e3535a64a993
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/28642
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Add google/buddy (Acer Chromeboase 24) as a variant of google/auron,
with the following changes:
- add buddy-specific variant code
- add handling to auron for buddy's lan init, which no other variants have
- add handling to auron's mainboard ACPI due buddy having different PCIe
port assigments than all other variants
Ported from Chromium branch firmware-buddy-6301.202.B, commit
ebb82ce [Buddy: Lock management engine + SPI descriptor]
Test: build/boot Linux on google/buddy using SeaBIOS and Tianocore payloads
Change-Id: Ib76eef47677b72ddaef81a2decef189a5f20c20a
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/28613
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Move inline function where they belong to. Fixes compilation
on non x86 platforms.
Change-Id: Ia05391c43b8d501bd68df5654bcfb587f8786f71
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/25720
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Combine existing boards google/auron_paine and google/samus with new
ChromeOS devices auron_yuna, gandof and lulu, using their common
reference board (auron) as a base.
Chromium sources used:
firmware-yuna-6301.59.B 6ed8b9d [CHERRY-PICK: broadwell: Update to...]
firmware-gandof-6301.155.B 666f34f [gandof: modify power limiting for...]
firmware-lulu-6301.136.B 8811714 [lulu: update RAMID table]
Additionally, some minor cleanup/changes were made:
- I2C devices set to use level (vs edge) interrupt triggering
- HDA verb entries use simplified macro entry format
- correct FADT table header version
- remove unused ACPI device entries / .asl file(s)
- clean up ACPI code (e.g., trackpad on Lulu)
- adjust _CID for trackpad on Lulu in order to not load non-functional
Windows driver (does not affect Linux)
- remove unused header includes (multiple/various)
- correct I2C addresses used for SMBIOS device entries
- correct misc typos etc
The existing auron_paine samus boards are removed.
Variant setup modeled after google/slippy
Change-Id: I53436878d141715eb18b8ea5043d71e6e8728fe8
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/17917
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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