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* mb/google/brya: Disable the Package C-state demotionZhixing Ma2022-08-011-0/+4
| | | | | | | | | | | | | | | | | | | | Disabling the Package C-state demotion feature for brya baseboard as a work around to the S0ix issue and also this doesn't have any impact on the power and performance measured and verified by the PNP team. This feature will be enabled after its functionality is verified with no issues and also based on its impact on PNP. BUG=none BRANCH=firmware-brya-14505.B TEST=Boot and verified that S0ix issue is resolved. Signed-off-by: Zhixing Ma <zhixing.ma@intel.com> Change-Id: Id3941c8870d41b25488c8ac5d38534fa94664d4a Reviewed-on: https://review.coreboot.org/c/coreboot/+/65805 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
* mb/google/brya/var/skolas: fix comment for I2C connectionsEran Mitrani2022-07-191-3/+3
| | | | | | | | | | | | | | For brya/skolas, I2C1 is cr50, and I2C3 is Touchscreen BUG=None BRANCH=firmware-brya-14505.B TEST=None Signed-off-by: Eran Mitrani <mitrani@google.com> Change-Id: I4058e0f33b2bb6227a0af92941ed4e2eb56ba542 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65792 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
* mb/google/brya/var/brya: fix comment for I2C connectionsEran Mitrani2022-07-161-3/+3
| | | | | | | | | | | | | | For brya, I2C1 is cr50, and I2C3 is Touchscreen BUG=None BRANCH=firmware-brya-14505.B TEST=None Signed-off-by: Eran Mitrani <mitrani@google.com> Change-Id: Id564d5ede43e745c607ddfd851ff03557d76ddec Reviewed-on: https://review.coreboot.org/c/coreboot/+/65793 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
* mb/google/nissa: Remove GPP_B11 PAD configurationHarsha B R2022-07-131-2/+2
| | | | | | | | | | | | | | Remove the pad configuration for GPP_B11 as this is not used in Nereid/Nivviks BUG=b:227694137 Signed-off-by: Harsha B R <harsha.b.r@intel.com> Change-Id: I3a213ffece75b9a706b96dc142a7e35c8b5973f6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65623 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
* mb/google/nissa: Confiure the unused virtual Cnvi BT GPIOs to NCV Sowmya2022-07-081-0/+21
| | | | | | | | | | | | | | | | Configure the unused virtual CNVi BT GPIOs to NC since we are using BT over USB mode for Nissa. BUG=b:233834597 TEST=Verified BT offload feature on Nivviks P1. Signed-off-by: V Sowmya <v.sowmya@intel.com> Change-Id: Id84823b9ad921ebd7ff773d6cce581563613745f Reviewed-on: https://review.coreboot.org/c/coreboot/+/65669 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
* mb/google/nissa: Disable the Package C-state demotionV Sowmya2022-07-081-0/+4
| | | | | | | | | | | | | | | | | | | | | | | Disabling the Package C-state demotion feature for nissa baseboard as a work around to the S0ix issue and also this doesn't have any impact on the power and performance measured and verified by the PNP team. This feature will be enabled after its functionality is verified with no issues and also based on its impact on PNP. BUG=b:235005582 TEST=Boot and verify that S0ix issue is resolved. Signed-off-by: V Sowmya <v.sowmya@intel.com> Change-Id: I4d586b962c27b86ee75651dcd655bc0868504646 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65664 Reviewed-by: Varshit B Pandya <varshit.b.pandya@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
* mb/google/brya: Change GPP_F17 programmingTim Wawrzynczak2022-07-071-1/+1
| | | | | | | | | | | | | | | | | | | Currently the EC's MKBP interrupt line is programmed as dual-routed to both SCI and IOAPIC. The brya EC will pulse the MKBP GPIO and also send a host event when there is an MKBP event for host to service. This causes an extra SCI to be generated, and the kernel will respond to each MKBP event with an extra unnecessary host command. Changing the pad configuration for the MKBP GPIO to APIC only fixes this issue. BUG=b:236706977 BRANCH=firmware-brya-14505.B TEST=excess GET_NEXT_EVENT host commands are gone from EC log Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ic7dd596987f6d34c69d46674bdd07785235e2d4c Reviewed-on: https://review.coreboot.org/c/coreboot/+/65480 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/nissa: Lock PLT_RST_L pinReka Norman2022-07-041-1/+1
| | | | | | | | | | | | | | | | | | | | | There is a requirement that the TPM RST signal cannot be asserted by software. On nissa this is PLT_RST_L, so lock this pin to prevent it being reconfigured as a GPIO. BUG=b:216671701 TEST=Try to change GPP_B13 from the kernel: $ echo 677 > /sys/class/gpio/export $ echo out > /sys/class/gpio/gpio677/direction $ echo 0 > /sys/class/gpio/gpio677/value $ echo 1 > /sys/class/gpio/gpio677/value GSC console doesn't show "PLT_RST_L ASSERTED" / "PLT_RST_L DEASSERTED" Change-Id: Id5d64b4b028e4f63c4acb05cd8632d0642866688 Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65591 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
* mb/google/nissa: Remove gpio lock for garage IRQ pinEric Lai2022-06-291-1/+1
| | | | | | | | | | | | | | | | Kernel driver will en/disable the IRQ when suspend/resume. If lock the pin, driver can't change the status which causes the unexpected behavior. Device will wake when insert the pen. This is workaround until we figure out the correct setting for driver. BUG=b:233159811 TEST=Pen garage wake event work as expected. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: Ifc7b1e52a24c0e7bd54664d59870cb09536ef868 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65380 Reviewed-by: Reka Norman <rekanorman@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/nissa: Change fw config override to pad_number table basedEric Lai2022-06-292-0/+2
| | | | | | | | | | | BUG=b:231690996 TEST=gpios are the same in kernel pinctrl dump. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I67a466fac478b2a3a682451174fbdcdd67816769 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64714 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
* mb/google/nissa: Change pen garage wake to EV_ACT_DEASSERTEDEric Lai2022-06-281-1/+1
| | | | | | | | | | | | | | | | | Follow google stylus spec. The Stylus-Present GPIO MUST be a wake pin that interrupts the system in active operation when the stylus is removed. After confirmed with the owner, the expect behavior is only wake when eject the pen. BUG=b:233159811 TEST=EC wake event work as expected. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I7a82e5e8935c9ea27e923661f66809e9169bc86a Reviewed-on: https://review.coreboot.org/c/coreboot/+/65379 Reviewed-by: Reka Norman <rekanorman@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
* mb/google/nissa: Apply gpio padbased table overrideEric Lai2022-06-273-0/+25
| | | | | | | | | | | | | | | In order to improve gpio merge mechanism. Change iteration override to padbased table override. And the following patch will change fw config override with ramstage gpio table override. BUG=b:231690996 TEST=check gpios in pinctrl are the same. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I3d0beabc2c185405cb0af31e5506b6df94e9522c Reviewed-on: https://review.coreboot.org/c/coreboot/+/64713 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/nissa: Skip locking for GPP_F14 GPIOMaulik V Vaghela2022-06-231-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is an existing issue for nissa boards where wake up from RTC wake is not working during suspend_stress_test. This issue was root caused to the patch which was setting GPE_EN bits for the GPIOs before locking. Reference: https://review.coreboot.org/c/coreboot/+/64089 Later issue was found to be with GPP_F14 configuration for nissa boards. When coreboot skips setting GPE_EN bit for GPP_F14, RTC wake works properly. Another way to make it work is to skip locking GPP_F14 GPIO to allow kernel to configure it properly. This patch skips the locking for GPP_F14 to allow kernel to configure it later. This fixes the issue of RTC wake not working. Note: This patch provides workaround for the existing issue and BUG will be closed once actual reason is identified and proper fix is available. BUG=b:234097956 BRANCH=None TEST=RTC wake works on Nivviks board with the patch. Change-Id: Ie8091ab8acf2b3f064cb79bdf4700f6b4c1674a5 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65086 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
* mb/google/nissa: Increase I2C bus frequency to around 390 kHzReka Norman2022-06-151-15/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Set the speed to I2C_SPEED_FAST in each speed_config so that the speed_config is actually applied. Currently, the speed_config isn't applied, so the hcnt/lcnt calculation falls back to rise_time_ns and fall_time_ns, which are 0 since they're not set. This results in frequencies around 300 kHz. - Move the data hold time to the speed_config, ensuring that the resulting sda_hold value remains the same. - For nivviks and nereid, tune scl_lcnt and scl_hcnt for each bus to give a frequency around 390 kHz. - In the baseboard, keep default scl_lcnt and scl_hcnt values. These work well for buses with a rise time around 100 ns, and can be used as a starting point before tuning them for a specific variant. BUG=b:229547183 TEST=Measure the clock frequency, tHIGH, tLOW and tVD;DAT on nivviks and nereid and check they meet the spec. nereid clock frequencies: I2C0 - 387.9 kHz I2C1 - 392.7 kHz I2C3 - 386.3 kHz I2C5 - 383.6 kHz nivviks clock frequencies: I2C0 - 387.67 kHz I2C1 - 380.47 kHz I2C2 - 388.51 kHz I2C3 - 384.03 kHz I2C5 - 389.09 kHz Change-Id: I88a6cfcc893183385eb85a89489e5d270277e537 Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64942 Reviewed-by: Kangheui Won <khwon@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/brya: Add new skolas baseboardNick Vaccaro2022-06-027-0/+885
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit adds the skolas baseboard, which is basically the brya baseboard, but using an Intel Raptor Lake-P SoC instead of an Alder Lake SoC. This commit also adds the skolas baseboard variant skolas4es. Since this baseboard is identical to the brya baseboard with the exception of the SoC used, the new baseboard and the new baseboard's first variant will be a copy of the current brya baseboard and brya0 variant. For now, the skolas baseboard and skolas4es variant will continue to use ADL-P. This allows for two benefits: 1. software to be proven out on existing hardware prior to RPL SoC support landing, and 2. allows us not to have to wait for RPL SoC changes prior to getting the mainboard changes in place Once the RPL SoC code has merged, I will update the skolas baseboard and skolas4es variant to use RPL instead of ADL. BUG=b:229134437 TEST=util/abuild/abuild -p none -t google/brya -x -a -c max Change-Id: Iec100306dca2320eaf2432797f3acc31db2543d3 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63891 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
* mb/google/brya/var/nissa: set tcc_offset value to 10Sumeet Pawnikar2022-05-281-0/+2
| | | | | | | | | | | | | | | Set tcc_offset value to 10 in devicetree for Thermal Control Circuit (TCC) activation feature as mentioned in doc #572349. BUG=b:229804441 BRANCH=None TEST=Build FW and test on Nivviks board Change-Id: Ie9533936eccbabcc9a873adcb622bb490928c9e3 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64664 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* mb/google/brya: Set eMMC dll tuning parameters for NissaUsha P2022-05-241-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for MB level dll tuning. This patch sets the eMMC dll tuning parameters to default values needed. There was issue observed on some eMMC devices which failed to boot in HS400 mode.EV team suggested the intermediate eMMC dll tuning parameters that needs to be set. We observed these values helped to fix the issue. While we get the verified default values set from FSP directly, adding it here to use it as the custom dll values needed. BUG=b:230403441 TEST=Build and boot nivviks board. Verify the eMMC dll parameters are overridden. [INFO ] usha: After override dll_params [INFO ] usha: emmc_tx_cmd_cntl=505 [INFO ] usha: emmc_tx_data_cntl1=909 [INFO ] usha: emmc_tx_data_cntl2=1c2a2828 [INFO ] usha: emmc_rx_cmd_data_cntl1=1c1b1d3c [INFO ] usha: emmc_rx_cmd_data_cntl2=10049 [INFO ] usha: emmc_rx_strobe_cntl=11515 Signed-off-by: Usha P <usha.p@intel.com> Change-Id: I27771b663ce9808e5a5ef4b36c136ad78f924376 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64203 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
* mb/google/brya/baseboard/nissa: Enable DPTF for Nissa variantsVidya Gopalakrishnan2022-05-241-0/+3
| | | | | | | | | | | | | BUG=b:224884901 BRANCH=None TEST=Build FW and test on Nivviks board Change-Id: I3f5e8dd3d2ff517e27b0b08a0173f094bc6043bd Signed-off-by: Vidya Gopalakrishnan <vidya.gopalakrishnan@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63021 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
* mb/google/nissa: Change pen garage wake to EV_ACT_ANYEric Lai2022-05-211-1/+1
| | | | | | | | | | | | | | | Follow google stylus spec. The Stylus-Present GPIO MUST be a wake pin that interrupts the system in active operation when the stylus is removed or inserted. BUG=b:233159811 TEST=EC wake event work as expected. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: Icf609c647e19914684a93c89022f2cd4888a67ef Reviewed-on: https://review.coreboot.org/c/coreboot/+/64538 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
* mb/google/nissa: Rework LTE GPIO configurationReka Norman2022-05-191-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | Currently, the LTE pins are enabled in gpio.c, then disabled in fw_config.c if LTE is not present. However, since there's a short delay between mainboard_init() and fw_config_handle(), this means that when LTE is not present GPP_H19 (SOC_I2C_SUB_INT_ODL, used for the SAR sensor) will be floating for a short period of time. Rework the GPIO config so that the LTE pins are disabled in the baseboard, then enabled in fw_config.c for variants using LTE. However, this doesn't work for WWAN_EN and WWAN_RST_L since they need to be enabled in bootblock. So these are instead enabled in the variant gpio.c, then disabled in fw_config.c if LTE is not present. BUG=None TEST=LTE still works on nivviks Change-Id: I9d8cbdff5a0dc9bdee87ee0971bc170409d925a2 Signed-off-by: Reka Norman <rekanorman@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64270 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Kangheui Won <khwon@chromium.org>
* mb/google/nissa: Change EC wake interrupt to IRQEric Lai2022-05-181-1/+1
| | | | | | | | | | | | | | | EC wake event doesn't work. Nissa has a separate EC wake pin. SCI only is not handled by EC, so we need to set dual route to wake the system. BUG=b:229142661 TEST=EC wake event work as expected. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: Ide1f4a2494bb0a64b11ab4c5135fc43d2a635f74 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64379 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
* mb/google/nissa/var/nivviks: Add support for NVMe and UFSReka Norman2022-05-161-0/+8
| | | | | | | | | | | | | | | | Enable either eMMC, NVMe or UFS based on fw_config. NVMe and UFS are only supported on nirwen, an additional nissa variant based on nivviks and sharing the nivviks coreboot target. BUG=b:218929856 TEST=Boot to OS on nivviks to check that eMMC still works. NVMe and UFS will be tested once nirwen boards are available. Change-Id: Ibdb122ef35920c962d7bd9f3f238a5d548112282 Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64211 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* mb/google/brya: Remove Rcomp resistors override for NissaUsha P2022-05-161-3/+0
| | | | | | | | | | | | | | | | | | | | | This patch sets the RComp resistor values to default values needed. BUG=b:231202733 TEST=Build and boot nivviks and nereid. Verify the Rcomp values are set to default values from debug FSP log. [SPEW ] Updating Rcomp Targets: [SPEW ] RcompTarget[RdOdt]: 48 [SPEW ] RcompTarget[WrDS]: 30 [SPEW ] RcompTarget[WrDSCmd]: 20 [SPEW ] RcompTarget[WrDSCtl]: 20 [SPEW ] RcompTarget[WrDSClk]: 20 Signed-off-by: Usha P <usha.p@intel.com> Change-Id: I2c7a54c49e282446ece77ca406951782282a009a Reviewed-on: https://review.coreboot.org/c/coreboot/+/64247 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
* mb/google/nissa/var/nivviks: Use interrupt with lock for pen detect GPIOEric Lai2022-05-161-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | With GPIO_DRIVER_LOCK kernel driver can't change to IRQ. Thus, we need to set it as INT in coreboot to make the IRQ work. BUG=b:223476974 TEST=evtest work as expected. Input driver version is 1.0.1 Input device ID: bus 0x19 vendor 0x1 product 0x1 version 0x100 Input device name: "PRP0001:00" Supported events: Event type 0 (EV_SYN) Event type 5 (EV_SW) Event code 15 (SW_PEN_INSERTED) state 0 Properties: Testing ... (interrupt to exit) Event: type 5 (EV_SW), code 15 (SW_PEN_INSERTED), value 1 Event: -------------- SYN_REPORT ------------ Event: type 5 (EV_SW), code 15 (SW_PEN_INSERTED), value 0 Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I5f9fdfb2622b4b955da216119e74c6f7d5795d36 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64091 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
* mb/google/brask: fix boot beepDtrain Hsu2022-04-191-1/+1
| | | | | | | | | | | | | | | | | Fix the issue that can't hear the boot beep at dev screen. GPP_B14 is used for PWM_PP3300_BUZZER and it should set to GPO. Modify GPP_B14 from PAD_CFG_NF_LOCK to PAD_CFG_GPO_LOCK. BUG=b:229345416 BRANCH=firmware-brya-14505.B TEST=emerge-brask coreboot and verify if the buzzer beeps. Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: I601735ab20974cd992ca5dd6dbaca1517a395aa2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63645 Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/nissa: Add gpio lock pinsEric Lai2022-04-191-48/+48
| | | | | | | | | | | | | | | | | | Followed the Brya series to lock the gpio pins in baseboard. Variant should honor locked gpios from baseboard, but not the last. Variant can add more gpios to lock if needed. BUG=b:216671701 TEST='emerge-nissa coreboot chromeos-bootimage', flash and verify that nivviks boots successfully to kernel. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: Ib34ca287596a6958407a944d0caf53f4bcc60d9b Reviewed-on: https://review.coreboot.org/c/coreboot/+/63568 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
* mb/google/brya: Add variant_init and variant_finalize callbacksTim Wawrzynczak2022-04-141-0/+3
| | | | | | | | | | | | | Some brya variants may need to initialize and finalize some variant-specific devices during ramstage, therefore add the commonly-used hooks and callbacks to support this. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Iede6dc5a5b9a7385fedd59d4eeaaba118eff0e20 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62382 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* mb/google/brya/baseboard/nissa: Configure I2C lcnt and hcntReka Norman2022-04-131-10/+20
| | | | | | | | | | | | | | | | | Configure lcnt and hcnt directly to give the required frequency, tHIGH and tLOW, instead of using rise and fall times. Aim for a frequency of 390 kHz to make sure it doesn't exceed 400 kHz on different boards. BUG=b:227517802 TEST=Probe the clock line and check that it meets the requirements for frequency, tHIGH and tLOW. Change-Id: I4d4f877c1f0cd9aacd3fa152890b7ef82e059f78 Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63562 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* mb/google/brya: Add missing parameter name to variant_generate_s0ix_hookReka Norman2022-04-131-1/+1
| | | | | | | | | | | | | | | | | | Fixes the following build error: src/mainboard/google/brya/mainboard.c: In function 'variant_generate_s0ix_hook': src/mainboard/google/brya/mainboard.c:157:40: error: parameter name omitted void __weak variant_generate_s0ix_hook(enum s0ix_entry) ^~~~~~~~~~~~~~~ BUG=None TEST=`abuild -a -x -c max -p none -t google/brya` now succeeds Change-Id: Id578766e2a3b7647e920740dde3e356a7db39d4d Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63564 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* ChromeOS: Add DECLARE_x_CROS_GPIOS()Kyösti Mälkki2022-04-073-16/+3
| | | | | | | | Change-Id: I88406fa1b54312616e6717af3d924436dc4ff1a6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58899 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/brya/var/nereid: Configure descriptor for either Type-C or HDMIReka Norman2022-04-071-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | Some bytes in the descriptor need to be set differently for Type-C and HDMI. To allow using a single firmware variant for both cases, update the descriptor at runtime based on fw_config. This is a temporary workaround while we find a better solution. The byte values were determined by changing the following CSE strap and comparing the generated descriptors: Type-C: TypeCPort2Config = "No Thunderbolt" HDMI: TypeCPort2Config = "DP Fixed Connection" The default value before updating the descriptor is Type-C, but this was chosen arbitrarily. BUG=b:226848617 TEST=Type-C and HDMI both work on nereid with fw_config set correctly. Change-Id: I2cc230e3bd35816c81989ae7e01df5d2c152062e Signed-off-by: Reka Norman <rekanorman@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63366 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Sam McNally <sammc@google.com>
* ChromeOS: Promote variant_cros_gpio()Kyösti Mälkki2022-04-061-1/+0
| | | | | | | | | | | | | | | | The only purpose of mainboard_chromeos_acpi_generate() was to pass cros_gpio array for ACPI \\OIPG package generation. Promote variant_cros_gpio() from baseboards to ChromeOS declaration. Change-Id: I5c2ac1dcea35f1f00dea401528404bc6ca0ab53c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58897 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/nissa/var/nivviks: Move WWAN power on sequence forwardEric Lai2022-03-301-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move WWAN power on sequence from OS to coreboot. This can save the WWAN initial time about 10S. Another purpose is power resource be removed because we don't power off the LTE in S0ix. BUG=b:223490884 TEST=FM101-GL work as expected. Enumerate time from [ 17.747145] usb 4-2: new SuperSpeed USB device number 2 using xhci_hcd [ 17.760192] usb 4-2: New USB device found, idVendor=2cb7, idProduct=01a2, bcdDevice= 5.04 [ 17.760210] usb 4-2: New USB device strings: Mfr=1, Product=2, SerialNumber=3 [ 17.760215] usb 4-2: Product: Fibocom FM101-GL Module [ 17.760220] usb 4-2: Manufacturer: Fibocom Wireless Inc. [ 17.760224] usb 4-2: SerialNumber: 9c88998f to [ 3.936409] usb 4-2: new SuperSpeed USB device number 2 using xhci_hcd [ 3.966695] usb 4-2: New USB device found, idVendor=2cb7, idProduct=01a2, bcdDevice= 5.04 [ 3.989989] usb 4-2: New USB device strings: Mfr=1, Product=2, SerialNumber=3 [ 4.003813] usb 4-2: Product: Fibocom FM101-GL Module [ 4.019760] usb 4-2: Manufacturer: Fibocom Wireless Inc. [ 4.019762] usb 4-2: SerialNumber: 9c88998f Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I0f3fe999ae3a109b739629948b619a389a9059b1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63129 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
* mb/google/brya/variants/baseboard/brask: set GPP_D0 to GPOZhuohao Lee2022-03-271-1/+1
| | | | | | | | | | | | | | | | | | Currently, we control the GPP_D0 in the flash_fp_mcu in order to program the component's firmware. If we set this pin to NC, then we can't control the GPP_D0 output low/high and that make the system fails to program the component's firmware. This patch sets the GPP_D0 to GPO to fix it. BUG=b:204679292 BRANCH=firmware-brya-14505.B TEST=program the component's firmware Change-Id: I2f58c324f807a067dbe338f044a33dc9622ca469 Signed-off-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63090 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* mb/google/brya: Remove mainboard.aslEric Lai2022-03-172-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Use C code to generate MS0X entry and provide variant hook. BUG=b:207144468 TEST=check SSDT table has the same entry. Scope (\_SB) { Method (MS0X, 1, Serialized) { If ((Arg0 == One)) { \_SB.PCI0.CTXS (0x148) } Else { \_SB.PCI0.STXS (0x148) } } } Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: Ic36543e5cbaf8aaa7d933dcf54badc5f40e8ef02 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62779 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/brya: Remove Pcie Generic driver for WWANCliff Huang2022-03-171-20/+0
| | | | | | | | | | | | | | | | | | | | | This was to merge PCIe ACPI code to WWAN device. But, now use recent _DSD generation changes in FM driver instead. PCie generic driver is not used for WWAN at this time. Also, RTD3 devices are moved to overridetree.cb where WWAN is present. BUG=b:221250331 BRANCH=firmware-brya-14505.B TEST= Check that _DSD is added to WWAN device in SSDT for the variants. Check that RTD3 is added to WWAN device in SSDT for the variants. Signed-off-by: Cliff Huang <cliff.huang@intel.com> Change-Id: Ia343c7545cf30bdbcd1de19e5eb84049dbb2977f Reviewed-on: https://review.coreboot.org/c/coreboot/+/62330 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/brya: set GPP_D0 to GPOMark Hsieh2022-03-161-1/+1
| | | | | | | | | | | | | | | | | | Based on the schematic carbine_adl-p_dvt_20211104.pdf, the GPP_D0 is directly connected to FP module, Set GPP_D0 to GPO, DUT can flash FP firmware successfully. BUG=b:222188263, b:223906569 TEST=USE="project_gimble emerge-brya coreboot" and run the Fingerprint Firmware Test. Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: I164ffff6bd3b4058d6e28247eb7c3ed46d3891b5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62739 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: YH Lin <yueherngl@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
* mb/google/brya: Disable C1-state auto demotion for Brya & BraskMAULIK V VAGHELA2022-03-152-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | C1-state auto demotion feature allows hardware to determine C1-state as per platform policy. Since Brya sets performance policy to balanced from hardware, auto demotion can be disabled without performance impact. Also, disabling this feature results in 110 mW power savings during video playback. Note that C1state Autodemotion feature is not applicable for ADL-P SoC. Hence recommendation is to keep it disabled. BUG=b:221876248 BRANCH=firmware-brya-14505.B TEST=Code compiles and correct value of c1-state auto demotion is passed to FSP. Also power and performance impact has been measure by respective teams. Change-Id: I41eea916cdfe4a86e4d263e3191f5cb40fa33a90 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62630 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
* soc/intel/adl/chip.h: Convert all camel case variables to snake caseMAULIK V VAGHELA2022-03-154-28/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | coreboot chip.h files mainly contains variable which allows board to fill platform configuration through devicetree. Since many of this configuration involves FSP UPDs, variable names were in camel case which aligned with UPD naming convention. By default coreboot follow snake case variable naming, so cleaning up file to align all variable names as per coreboot convention. During renaming process, this patch also removes unused variables listed below: -> SataEnable // Checked in SoC code based on PCI dev enabled status -> ITbtConnectTopologyTimeoutInMs // SoC always passes 0, so not used Note: Since separating out changes into smaller CL might break the compilation for the patch set, this is being pushed as a single big CL. BUG=None BRANCH=firmware-brya-14505.B TEST=All boards using ADL SoC compiles with the CL. Change-Id: Ieda567a89ec9287e3d988d489f3b3769dffcf9e0 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62645 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
* mb/google/brya: Set EPP to 45% for all Brya variantsCliff Huang2022-03-141-0/+4
| | | | | | | | | | | | | | | | | | | This sets EPP value to be 45% for all Brya variants. Historically, EPP Ratio has always been 50% (128) on Chrome platforms. But on Intel Alderlake EPP ratio of 45% is recommended for optimal power and performance on Chrome platforms. BUG=b:219785001 BRANCH=firmware-brya-14505.B TEST= Use 'iotools rdmsr [cpu id] 0x774' command and check field 32:24 = 0x73. Signed-off-by: Cliff Huang <cliff.huang@intel.corp-partner.google.com> Change-Id: I973cfec72a0be24c56c4cd3283d2fe6e18400d02 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62655 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/nissa/var/nivviks: Enable pen garageEric Lai2022-03-141-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Enable pen garage. Pen detect is active low. And wake system when eject. BUG=b:223476974 TEST=evtest work as expected. Input driver version is 1.0.1 Input device ID: bus 0x19 vendor 0x1 product 0x1 version 0x100 Input device name: "PRP0001:00" Supported events: Event type 0 (EV_SYN) Event type 5 (EV_SW) Event code 15 (SW_PEN_INSERTED) state 0 Properties: Testing ... (interrupt to exit) Event: type 5 (EV_SW), code 15 (SW_PEN_INSERTED), value 1 Event: -------------- SYN_REPORT ------------ Event: type 5 (EV_SW), code 15 (SW_PEN_INSERTED), value 0 Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I2f676301c3372a4760853ce9c10b75f94e22bbcd Reviewed-on: https://review.coreboot.org/c/coreboot/+/62675 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
* mb/google/brya/var/nivviks: Change bluetooth USB2 port from 8 to 10Reka Norman2022-03-081-1/+0
| | | | | | | | | | | | | | | | | When using CNVi WLAN on ADL-N, the internal USB2 port 10 is used for bluetooth. So update the nivviks overridetree to enable port 10 instead of port 8, which is the external port used for bluetooth with PCIe WLAN. BUG=b:222595137 TEST=Bluetooth works on nivviks Change-Id: Ica2067023125c04fc753eabc944ae29ff59dc864 Signed-off-by: Reka Norman <rekanorman@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62585 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com>
* mb/google/brya: Enable GPIO PM dynamically based on cr50 FW versionTim Wawrzynczak2022-03-072-20/+0
| | | | | | | | | | | | | | | | | | cr50 firmware revisions starting at 0.5.5 and later are able to extend their IRQ pulses to be a minimum of 100us long. This change will enable cr50 long interrupt pulses when it detects the feature is supported by the detected firmware version. If the capability was detected, then GPIO PM will be enabled for the device, otherwise it will be disabled. BUG=b:202246591 TEST=boot brya0, check console logs for the correct message, and verify the GPIO PM registers. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Iaf333dc0f177e17cd03b36ec7e487fc33bde2b93 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61722 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/brya: Move ACPI MPTS method from DSDT to SSDT for Brya and RedrixCliff Huang2022-03-071-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change is to move MPTS (Mainboard Prepare To Sleep) method from wwan_power.asl to SSDT. MPTS is mainboard-specific method, while wwan_power.asl is meant for WWAN from its name. Having fixed MPTS method (i.e. DSDT) can not cover the case where device only presents and certain CBI bit(s) is(are) set. In Redrix and Brya, there are SKUs with or without 5G, 4G device. For those with 4G, MPTS method should be different. For those with no WWAN device, no MPTS is needed. Having MPTS generating in SSDT also eliminates the need for introducing Kconfig flags to support different devices in the future. MPTS method is created inside mainboard_fill_ssdt function in which the corresponding variant function is called. This will generate the following for the mainboard: Scope (\_SB) { Method (MPTS, 1, Serialized) { Local0 = \_SB.PCI0.RP01.RTD3._STA () If ((Local0 == One)) { \_SB.PCI0.RP01.PXSX.DPTS (Arg0) } } } Test: Check the SSDT for MPTS method under \_SB after boot to OS Use shutdown command and check the GPIO pins from logical analyzer Signed-off-by: Cliff Huang <cliff.huang@intel.com> Change-Id: I0f0b7638e90a7862173fca99305398bb250373e9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61887 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/brya/variants: add the smbus addr for dimm1Zhuohao Lee2022-03-021-0/+2
| | | | | | | | | | | | | | Align the setting with the adlrvp BUG=b:200243989 BRANCH=firmware-brya-14505.B TEST=build pass and works correctly in the brask Change-Id: Ia4c889e7dd065632e180cf983c7c5ece0c461edd Signed-off-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62295 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/brask: Update PCH power cycle related durationsZhuohao Lee2022-02-251-0/+6
| | | | | | | | | | | | | | | | | | The power rails discharge time of brask has been measured, the longest discharge time of the power rails are smaller than 150ms so it is safe to set the pwr_cyc_dur to 1 second. Since the brask is derived from the brya, we could apply the same setting from the brya. The setting is copied from commit dee834aa. BUG=b:214454454 BRANCH=firmware-brya-14505.B TEST=`test_that firmware_ECPowerButton` passed. Change-Id: I5e5eebb79e99a52fc3e4128213c6986f20100b8d Signed-off-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62286 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/brya: Enable eMMC HS400 mode for nissaReka Norman2022-02-211-0/+3
| | | | | | | | | | | | | | | | Based on the nivviks and nereid schematics, nissa is using eMMC HS400 mode, so enable this in devicetree. BUG=b:197479026 TEST=Build test nivviks and nereid Signed-off-by: Reka Norman <rekanorman@google.com> Change-Id: Ie9772385276d3629079b95024d3ffa04438f22c2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61998 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
* mb/google/brya: remove the delay from for WWAN _ON method.Cliff Huang2022-02-181-1/+0
| | | | | | | | | | | | | | | | Remove unecessary delay in RTD3 _ON Method after PERST# dessartion. TEST: 2022-02-10T18:22:53.204391Z INFO kernel: [ 0.190287] ACPI: Power Resource [RTD3] (on) 2022-02-10T18:22:53.204395Z INFO kernel: [ 0.194252] ACPI: Power Resource [RTD3] (off) Signed-off-by: Cliff Huang <cliff.huang@intel.com> Change-Id: I9bc36af6e6c944fcd3de23b7d49640ad9d25642d Reviewed-on: https://review.coreboot.org/c/coreboot/+/61783 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
* mb/google/brya: Update memory DQ mapEric Lai2022-02-161-20/+20
| | | | | | | | | | | | | | | Follow latest schematic to update the DQ map. BUG=b:218939997 TEST=boot into OS without issue. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: If29cc22b1749fb5d602d3ce64bcc1182593d673f Reviewed-on: https://review.coreboot.org/c/coreboot/+/61843 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
* mb/google/nissa: Set half_populated trueKrishna Prasad Bhat2022-02-121-2/+9
| | | | | | | | | | | | | | | | | | | | | | Alder Lake N has single memory controller with 64-bit bus width. Alder Lake common meminit block driver considers bus width to be 128-bit and populates the meminit data accordingly. By setting half_populated to true, only the bottom half is populated. Ideally, half_populated is used in platforms with multiple channels to enable only one half of the channel. Alder Lake N has single channel, and it would require for new structures to be defined in meminit block driver for LPx memory configurations. In order to avoid adding new structures, set half_populated to true. This has the same effect as having single channel with 64-bit width. Change-Id: I414e5dc82caf47b6b96c474b3ef6e01c2ce0226e Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61764 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-15 12:53:32 +0000