| Commit message (Collapse) | Author | Age | Files | Lines |
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1. Set Type-A USB3 port0/1 tx_de_emp to 0x2B to fix the USB3 Gen2 RX
signal integrity issue.
2. Disable unused USB port.
BUG=b:238230292
TEST=build FW and check Type-A USB3 port0/port1 RX pass
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I8356ca30a965e5774a1556c5cb81e1586c55496c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66118
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Modify ddi_ports_config based on schematic.
DDI_PORT_A = DP
DDI_PORT_B = HDMI
DDI_PORT_1 = Type-C DP
DDI_PORT_3 = HDMI
BUG=b:237419696
TEST=Boot to Chrome OS and check all display port working
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I7c0458f0dbd4637b91af9e01664073e1f8a7a614
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65660
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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This patch uses ACPI _PLD macros to add custom values for USB ports.
C0 A2 A3
+----------------+
| REAR |
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| FRONT |
+----------------+
A1 A0
BUG=b:232419500
TEST=emerge-brask coreboot
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I5ada4e9b25102a9cfd3b02a2abcd956f6cbc5619
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65544
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Won Chung <wonchung@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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add fw_config probe for auido and enable BT offload support.
BUG=b:232419816 b:232419765
TEST=FW_NAME=kuldax emerge-brask coreboot
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: Id58e48cc2510d0377040d86bb9dbbb45bec7d624
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64987
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
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Update override devicetree based on schematics.
BUG=b:232419765
TEST=FW_NAME=kuldax emerge-brask coreboot
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: Ib66a97cd76cb169e3f33a4d2d2465db115939d03
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64888
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
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Based on latest schematic to update the gpio table.
BUG=b:232419765
TEST=FW_NAME=kuldax emerge-brask coreboot
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: If30d872af5d729c0ebd468ebfb099192ec682309
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64862
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
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Create the kuldax variant of the brask reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0).
BUG=b:233380254
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_KULDAX
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I95c04768bbed8657d2858bcd66fc041f56910b8a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64559
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
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