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* mb/google/brya/var/redrix{4es}: Add H54G68CYRBX248 supportWisley Chen2022-07-283-1/+3
| | | | | | | | | | | | | | Generate SPD id for Hynix H54G68CYRBX248 BUG=b:239888704 BRANCH=firmware-brya-14505.B TEST=run part_id_gen to generate SPD id Change-Id: I9412b988bcdb0c744e016f3add6dacda8185d6db Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66071 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* treewide: Unify Google brandingJon Murphy2022-07-041-1/+1
| | | | | | | | | | | | | | | | | Branding changes to unify and update Chrome OS to ChromeOS (removing the space). This CL also includes changing Chromium OS to ChromiumOS as well. BUG=None TEST=N/A Change-Id: I39af9f1069b62747dbfeebdd62d85fabfa655dcd Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65479 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* mb/google/brya: Remove Pcie Generic driver for WWANCliff Huang2022-03-171-2/+19
| | | | | | | | | | | | | | | | | | | | | This was to merge PCIe ACPI code to WWAN device. But, now use recent _DSD generation changes in FM driver instead. PCie generic driver is not used for WWAN at this time. Also, RTD3 devices are moved to overridetree.cb where WWAN is present. BUG=b:221250331 BRANCH=firmware-brya-14505.B TEST= Check that _DSD is added to WWAN device in SSDT for the variants. Check that RTD3 is added to WWAN device in SSDT for the variants. Signed-off-by: Cliff Huang <cliff.huang@intel.com> Change-Id: Ia343c7545cf30bdbcd1de19e5eb84049dbb2977f Reviewed-on: https://review.coreboot.org/c/coreboot/+/62330 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* soc/intel/adl/chip.h: Convert all camel case variables to snake caseMAULIK V VAGHELA2022-03-151-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | coreboot chip.h files mainly contains variable which allows board to fill platform configuration through devicetree. Since many of this configuration involves FSP UPDs, variable names were in camel case which aligned with UPD naming convention. By default coreboot follow snake case variable naming, so cleaning up file to align all variable names as per coreboot convention. During renaming process, this patch also removes unused variables listed below: -> SataEnable // Checked in SoC code based on PCI dev enabled status -> ITbtConnectTopologyTimeoutInMs // SoC always passes 0, so not used Note: Since separating out changes into smaller CL might break the compilation for the patch set, this is being pushed as a single big CL. BUG=None BRANCH=firmware-brya-14505.B TEST=All boards using ADL SoC compiles with the CL. Change-Id: Ieda567a89ec9287e3d988d489f3b3769dffcf9e0 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62645 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
* mb/google/brya/var/redrix{4es}: Config VR_DOMAIN_GT's slew rate to 1/8Wisley Chen2022-03-091-0/+2
| | | | | | | | | | | | | Config VR_DOMAIN_GT's slew rate to 1/8 as well. BUG=b:204009588 TEST=build and verified by Power team. Change-Id: I766b828ad83710913323cf1485e09c1e0fd5e4c2 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62632 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/brya/var/redrix{4es}: Disable TCSS PCIe port1Wisley Chen2022-03-071-0/+1
| | | | | | | | | | | | | Disable unused TCSS PCIe port1 BUG=b:217238553 TEST=FW_NAME=redrix emerge-brya coreboot chromeos-bootimage Change-Id: I2bdfdb23d010a1e24c986ab52b5cef6eedcb674e Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62589 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/brya/var/{brya*,redrix*}: Add DmaProperty for WWANTim Wawrzynczak2022-03-071-0/+1
| | | | | | | | | | | | | | | | ChromeOS considers the WWAN devices to be untrusted, therefore enable the new DmaProperty in the WWAN's _DSD to indicate to the OS that these devices should have IOMMU restrictions applied to them. BUG=b:215424986 BRANCH=brya TEST=dump SSDT Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I9c9e73b7ea0575ab87cc980fb4786338047155de Reviewed-on: https://review.coreboot.org/c/coreboot/+/62437 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
* mb/google/brya/var/redrix{4es}: Re-enable USB2 port for BluetoothWisley Chen2022-03-071-1/+0
| | | | | | | | | | | | | | | BT didn't work due to commit 03c0853f4d58c73. Commit 03c0853f4d58c73 accidentally set the Bluetooth USB2 port to "empty", therefore re-enable USB2 port 9. BUG=b:217238553, b:222238381 TEST=build and verfied BT work/suspend successfully Change-Id: Ie94ef847fc130019f1e06983fc5039f1f564cd3a Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62564 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/brya: Move ACPI MPTS method from DSDT to SSDT for Brya and RedrixCliff Huang2022-03-071-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change is to move MPTS (Mainboard Prepare To Sleep) method from wwan_power.asl to SSDT. MPTS is mainboard-specific method, while wwan_power.asl is meant for WWAN from its name. Having fixed MPTS method (i.e. DSDT) can not cover the case where device only presents and certain CBI bit(s) is(are) set. In Redrix and Brya, there are SKUs with or without 5G, 4G device. For those with 4G, MPTS method should be different. For those with no WWAN device, no MPTS is needed. Having MPTS generating in SSDT also eliminates the need for introducing Kconfig flags to support different devices in the future. MPTS method is created inside mainboard_fill_ssdt function in which the corresponding variant function is called. This will generate the following for the mainboard: Scope (\_SB) { Method (MPTS, 1, Serialized) { Local0 = \_SB.PCI0.RP01.RTD3._STA () If ((Local0 == One)) { \_SB.PCI0.RP01.PXSX.DPTS (Arg0) } } } Test: Check the SSDT for MPTS method under \_SB after boot to OS Use shutdown command and check the GPIO pins from logical analyzer Signed-off-by: Cliff Huang <cliff.huang@intel.com> Change-Id: I0f0b7638e90a7862173fca99305398bb250373e9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61887 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/brya/var/redrix{4es}: Add MT53E2G32D4NQ-046 WT:CWisley Chen2022-02-243-3/+5
| | | | | | | | | | | | | Add new memory MT53E2G32D4NQ-046 WT:C support. BUG=b:220804962 TEST=emerge-brya coreboot Change-Id: I3353d7c119798ebb0b5ee1ea32161e54b4eec826 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62267 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/brya/redrix{4es}: Disable unused USB2/TCSS portsWisley Chen2022-02-181-0/+5
| | | | | | | | | | | | | Disable unused USB2/TCSS Ports. BUG=b:217238553 TEST=FW_NAME=redrix emerge-brya coreboot Change-Id: I1cdee5b6dc56accb52ba1bf636bdf753a7bfd199 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62069 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/brya/var/{redrix, redrix4es}: Use ACPI _PLD macroSubrata Banik2022-02-181-36/+6
| | | | | | | | | | | | | This patch uses ACPI _PLD macros for USB Type A and C ports. BUG=b:216490477 TEST=emerge-brya coreboot Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I61f8f39ce7651d499756f4975840f32f89b04ca7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61829 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/brya/var/{redrix, redrix4es}: Fix PLD group orderSubrata Banik2022-02-181-4/+4
| | | | | | | | | | | | | | | | | In ec/google/chromeec: Add PLD to EC conn in ACPI table (667471b8d807da5a5a9277db47e069ad3b1351c7), PLD is added to ACPI table. This patch ensures USB _PLD group numbers are appear in order. BUG=b:216490477 TEST=build coreboot and system boot into OS. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I80d9038d1f41d65201d6bfdb808708f997d71faf Reviewed-on: https://review.coreboot.org/c/coreboot/+/62031 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
* mb/google/var/redrix4es: Add gpios to lockEric Lai2022-02-091-4/+4
| | | | | | | | | | | | | | | | Variant should honor locked gpios from baseboard, but not the last. Variant can add more gpios to lock if needed. BUG=b:216583542 TEST='emerge-brya coreboot chromeos-bootimage', flash and verify that redrix boots successfully to kernel. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ifd69a9c2f1a71aefc19adf6931e10de62d05fb2c Reviewed-on: https://review.coreboot.org/c/coreboot/+/61699 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
* mb/google/brya: Add custom PLD fields to devicetree for brya variantsWon Chung2022-02-091-6/+42
| | | | | | | | | | | | | BUG=b:216490477 TEST=emerge-brya coreboot Signed-off-by: Won Chung <wonchung@google.com> Change-Id: If610e6b3c849d982345ed1b8607ffd2af105dc51 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61571 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
* mb/google/brya: Add 5G WWAN ACPI support for Brya and RedrixCliff Huang2022-02-071-0/+10
| | | | | | | | | | | Add FM350GL 5G WWAN support using drivers/wwan/fm and addtional PM features from RTD3. Signed-off-by: Cliff Huang <cliff.huang@intel.com> Change-Id: I6413f106ce6ef6c895d4861f4dbe26ac9a507d25 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61355 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/brya: Lock TPM pin in brask and brya baseboardsSubrata Banik2022-02-021-0/+4
| | | | | | | | | | | | | | | | This applies a configuration lock to the TPM I2C and IRQ GPIO for all brya and brask variants. BUG=b:208827718 TEST=cat /sys/kernel/debug/pinctrl/INTC1055\:00/pins suggests I2C_TPM_SDL and I2C_TPM__SDA GPIO PINs are locked. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I4f2a7014faeecd4701ea35ec77ef0e1692516b9d Reviewed-on: https://review.coreboot.org/c/coreboot/+/61499 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/brya/var/redrix{4es}: Add host device event supportWisley Chen2022-01-141-0/+37
| | | | | | | | | | | | | | Adding this host event to the EC SCI event and wake masks allows the system to generate an SCI and/or wake when this event happens. BUG=b:206012072 TEST=build Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Change-Id: I4f48244a4fca750a9de2ecc20f24786034d45b8a Reviewed-on: https://review.coreboot.org/c/coreboot/+/61072 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/brya/var/redrix{4es}: Set tcc_offset value to 3Wisley Chen2022-01-141-0/+1
| | | | | | | | | | | | | | | | The redrix thermal team has determined that the TCC circuit trip temperature should be set to 97C, therefore, because the offset is subtracted from 100C, set the `tcc_offset` register in the devicetree to 3. BUG=b:200134784 TEST=build and verified by thermal team Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Change-Id: Ifb63d63bc741b2a402328f256b43bc83e0a88a9e Reviewed-on: https://review.coreboot.org/c/coreboot/+/61003 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/brya: Move gpio_pm settings for brya variants to baseboardsTim Wawrzynczak2022-01-121-10/+0
| | | | | | | | | | | | | | | The factory versions (minor version 22) of cr50 FW have an issue with producing short interrupt pulses, which can be missed by the ADL PCH if autonomous GPIO power management is enabled, therefore instead of continually adding the setting to all the variants, move it to the baseboard instead. Change-Id: I337f1e9e8f958c02bb73e6701a06c0b88a4757d7 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60872 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
* mb/google/brya/var/redrix: Add new memory supportWisley Chen2022-01-043-4/+12
| | | | | | | | | | | | | | | | | Add the new memory support: Hynix H54G46CYRBX267 Samsung K4U6E3S4AB-MGCL Hynix H54G56CYRBX247 Samsung K4UBE3D4AB-MGCL BUG=b:212330664 TEST=FW_NAME=redrix emerge-brya coreboot Change-Id: I32491f86813c8e6566774d4b3d7d82295f906bd3 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60410 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* drivers/intel/pmc_mux/conn: Change usb{23}_port_number fields to device pointersReka Norman2021-12-231-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, the pmc_mux/conn driver uses integer fields to store the USB-2 and USB-3 port numbers from the SoC's point of view. Specifying these as integers in the devicetree is error-prone, and this information can instead be represented using pointers to the USB-2 and USB-3 devices. The port numbers can then be obtained from the paths of the linked devices, i.e. dev->path.usb.port_id. Modify the driver to store device pointers instead of integer port numbers, and update all devicetrees using the driver. These are the mainboards affected (all are Intel TGL or ADL based): google/brya google/volteer intel/adlrvp intel/shadowmountain intel/tglrvp system76/darp7 system76/galp5 system76/lemp10 Command used to update the devicetrees: git grep -l "usb._port_number" src/mainboard/ | \ xargs sed -i \ -e 's/register "usb2_port_number" = "\(.*\)"/use usb2_port\1 as usb2_port/g' \ -e 's/register "usb3_port_number" = "\(.*\)"/use tcss_usb3_port\1 as usb3_port/g' BUG=b:208502191 TEST=Build test all affected boards. On brya0, boot device and check that the ACPI tables generated with and without the change are the same. Change-Id: I5045b8ea57e8ca6f9ebd7d68a19486736b7e2809 Signed-off-by: Reka Norman <rekanorman@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60143 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Crawford <tcrawford@system76.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* mb/google/brya/var/*: Add disable_gpio_export_in_crs to all devicetreesTim Wawrzynczak2021-12-201-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | None of the touchscreens used in the brya program (any brya board) should require exporting of GPIOs in the ACPI _CRS method for any i2c device. This can cause i2c devices to malfunction or cause timing sequence violations if: 1) ACPI exports a PowerResource for the device that uses GPIOs that are also exported in _CRS 2) The kernel driver for the device uses the GPIOs exported in _CRS for its own purposes. This means the state of the pin is out of sync between platform firmware and the kernel. The Linux ELAN I2C touchcsreen driver (https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/third_party/kernel/upstream/drivers/input/touchscreen/elants_i2c.c;l=1429) is one example of this. Therefore, add disable_gpio_export_in_crs to all brya variants that use the drivers/i2c/generic or drivers/i2c/hid chip drivers. Change-Id: Ib4475bd0dc885e230911de6298fd95baa868ef29 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60175 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* mb/google/brya/var/redrix4es: sync change from redrixYH Lin2021-12-091-0/+2
| | | | | | | | | | | | | | | | | | | | | The original change was for mb/google/redrix (commit 0167f5adbb), "The ChromeOS kernel platform driver is adding support for a ChromeOS privacy screen device, and in order to locate that device, the driver uses the GOOG0010 reserved HID for this" But it was merged before redrix4es is available. As redrix4es is forked from redrix, relevant change in redrix need to be brought into redrix4es as well. BUG=b:206850071 TEST=build Signed-off-by: YH Lin <yueherngl@google.com> Change-Id: I5ac90c249273bf4e75cccb5889844a7f196f56fc Reviewed-on: https://review.coreboot.org/c/coreboot/+/59987 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* brya: add various ES variantsYH Lin2021-11-3010-0/+822
Fork multiple "4ES" variants off some brya devices to properly support ES SoC. BRANCH=none BUG=b:201767461 TEST=emerge-brya coreboot and check the artifacts Signed-off-by: YH Lin <yueherngl@google.com> Change-Id: Ic9516fec591429238bde1478eca2522d8ed10127 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59728 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-17 06:13:34 +0000