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* mb/google/brya/var/vell: Set GPP_B2 NC for RGB keybaordRobert Chen2022-08-051-1/+1
| | | | | | | | | | | | | | | When GPP_B2 output high, there is a leakage path. This patch fix it by setting the pin NC. BUG=b:233959105 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot Change-Id: I3c833d5d62c715960dcb27494a0b9b93c91e8f2f Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66382 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
* treewide: Unify Google brandingJon Murphy2022-07-041-1/+1
| | | | | | | | | | | | | | | | | Branding changes to unify and update Chrome OS to ChromeOS (removing the space). This CL also includes changing Chromium OS to ChromiumOS as well. BUG=None TEST=N/A Change-Id: I39af9f1069b62747dbfeebdd62d85fabfa655dcd Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65479 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* mb/google/brya/vell: Implement variant_devtree_update() for audioeddylu@ami.corp-partner.google.com2022-06-162-2/+55
| | | | | | | | | | | | | | | | | Different board versions have different audio layouts, therefore support both layouts by enabling only the appropriate devices in the devicetree via board_id(). BUG=b:207333035 BRANCH=none TEST='FW_NAME=vell emerge-brya coreboot' Change-Id: If053b8f85933f8fc75589ae175e225cc9c1e3991 Signed-off-by: Eddy Lu <eddylu@ami.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65124 Reviewed-by: Shon Wang <shon.wang@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/brya/var/vell: Add new LP5 RAM IDShon2022-06-073-0/+3
| | | | | | | | | | | | | | | | Add the support LP5 RAM parts for vell: DRAM Part Name ID to assign Vendor H58G56AK6BX069 2 (0010) Hynix BUG=b:227595062 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot Change-Id: Ibe09285c15b28ceeb6ab0d6c94f90e00584ac07d Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64852 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* mb/google/brya/var/vell: Move SPK0/SPK1 to I2C7eddylu@ami.corp-partner.google.com2022-05-301-21/+38
| | | | | | | | | | | | | | | | To support speaker AMP CS35L53-CWZR'S I2C needs to split to two I2C ports BUG=b:207333035 BRANCH=none TEST=built and verified speaker Signed-off-by: Eddy Lu <eddylu@ami.corp-partner.google.com> Change-Id: I8095abc4fc3233b21b818a508c84cd59b39fc1d6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63756 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com> Reviewed-by: Shon Wang <shon.wang@quanta.corp-partner.google.com>
* Revert "mb/google/brya/var/vell: Remove unused i2c7 settings"Shon Wang2022-05-302-5/+15
| | | | | | | | | | | | | | | | | This reverts commit bd9cec8ae5755e898d107fd061fc2e2f983552b9. Reason for revert: Enable i2c7 for amp changing to 2 channel because vell setting amp on i2c0 and i2c7 on next phase BUG=b:229334701 TEST=emerge-brya coreboot chromeos-bootimage && $powerd_dbus_suspend && checks EC log and ensures the DUT could enter s0ix. Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com> Change-Id: I5988cd9926b2c9ced1d111774abaa897bef91537 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64627 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/brya/var/vell: Set empty on USB2_9/USB32_1Shon2022-05-281-0/+4
| | | | | | | | | | | The baseboard uses port USB2 #9, and USB3 #1, but vell does not, therefore set the port configuration to EMPTY. Change-Id: I0d03b967fd2a051205ad5807f0bd8916bad7c036 Signed-off-by: Shon <shon.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64628 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/brya/var/vell: Remove unused i2c7 settingsGaggery Tsai2022-05-052-15/+5
| | | | | | | | | | | | | | | | This patch removes unused i2c7 settings. Accroding to EVT schematic, i2c7 is reserved for AMP but resistors are unstuffing. BUG=b:229334701 TEST=emerge-brya coreboot chromeos-bootimage && $powerd_dbus_suspend && checks EC log and ensures the DUT could enter s0ix. Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com> Change-Id: Ifc1e0085064a13149ebc7e70184d1f40462e0fff Reviewed-on: https://review.coreboot.org/c/coreboot/+/63892 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/brya/var/vell: Enable TBT PCIe root port 3Gaggery Tsai2022-04-271-0/+2
| | | | | | | | | | | | | | This patch enables TBT PCIe root port 3. BUG=b:230464233 TEST=emerge-brya coreboot chromeos-bootimage and $lspci -t and ensure 07.3 is in the list. Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com> Change-Id: I118facd45f54c8ed2843a85c0aa61b6571077a5d Reviewed-on: https://review.coreboot.org/c/coreboot/+/63850 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/brya/var/vell: Fix camera LED flicker problemShon Wang2022-04-271-10/+10
| | | | | | | | | | | | | | | | | | | Camera LED flicker 3 times or so as sensor is being probed during kernel boot. Configure _DSC to ACPI_DEVICE_SLEEP_D3_COLD so that driver skips initial probe during kernel boot preventing camera LED flicker. Corrects that by explicitly sequencing the reset GPIO and power GPIO BUG=b:219644184 TEST=Build and boot on vell, observe whether camera LED flickers Change-Id: I846ec4cb5c4527f5664699b31d0d561d390d938c Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63441 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/brya/var/vell: increase RFI Spread Spectrum to 6%Robert Chen2022-04-201-0/+3
| | | | | | | | | | | | | | | Increase RFI Spread Spectrum to 6% for Vell as RF team request. The default of Spread Spectrum in FSP is 1.5%, and set 1.5% in baseboard as default. BUG=b:228929196 TEST=emerge-brya coreboot and pass RF test as before Change-Id: I7cdca8f51ad18f4ab03e4e6c744b60da68263ce2 Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63440 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/brya/var/vell: add WWAN power sequence setting for vellRobert Chen2022-04-122-3/+16
| | | | | | | | | | | | | | Add WWAN power sequence setting to meet spec BUG=b:220084872 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot Change-Id: If6d3f965b8f6b6753446f55a8bd47d3b0c1ae7be Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61847 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/brya/var/vell: Tune I2C1/I2C7 bus speed for 1 MHzEddy Lu2022-04-041-0/+20
| | | | | | | | | | | | | | Tune I2C parameters to make sure I2C1 and I2C7 bus speed is around 1MHz. BUG=b:207333035 BRANCH=none TEST=built and verified adjusted I2C speed around 1MHz Change-Id: I09a9edf723bb1198bbf5d71248abc07276cd94ff Signed-off-by: Eddy Lu <eddylu@ami.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63241 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/brya/vell: Move WWAN devices for vellRobert Chen2022-03-211-0/+25
| | | | | | | | | | | | | | | This was to merge PCIe ACPI code to WWAN device. Also, RTD3 devices are add to overridetree.cb where WWAN is present for vell. BUG=none BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Change-Id: If27abcf31ed948899bfaecbe8ef494fe8a80609b Reviewed-on: https://review.coreboot.org/c/coreboot/+/62771 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/brya/var/vell: Change AMP driver settingShon Wang2022-03-182-30/+42
| | | | | | | | | | | | 1.Change I2S GPP_Sx (S0-S3) Native PAD Configuration from NF2 to NF4 2.Select CS35l53 AMP driver for Vell variant. Change-Id: I96d49bd1a2ba061c4fd52b450b31d0885f49552c Signed-off-by: Shon.Wang <shon.wang@quanta.corp-partner.google.com> Signed-off-by: Vitaly Rodionov <vitaly.rodionov@cirrus.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60331 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* soc/intel/adl/chip.h: Convert all camel case variables to snake caseMAULIK V VAGHELA2022-03-151-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | coreboot chip.h files mainly contains variable which allows board to fill platform configuration through devicetree. Since many of this configuration involves FSP UPDs, variable names were in camel case which aligned with UPD naming convention. By default coreboot follow snake case variable naming, so cleaning up file to align all variable names as per coreboot convention. During renaming process, this patch also removes unused variables listed below: -> SataEnable // Checked in SoC code based on PCI dev enabled status -> ITbtConnectTopologyTimeoutInMs // SoC always passes 0, so not used Note: Since separating out changes into smaller CL might break the compilation for the patch set, this is being pushed as a single big CL. BUG=None BRANCH=firmware-brya-14505.B TEST=All boards using ADL SoC compiles with the CL. Change-Id: Ieda567a89ec9287e3d988d489f3b3769dffcf9e0 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62645 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
* mb/google/brya/vell: Enable USB2 port for KBD MCUDaisuke Nojiri2022-03-071-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Vell has a keyboard MCU connected to USB2 port 7. This patch enables the port. localhost# usb_updater2 -f Found device. found interface 0 endpoint 1, chunk_len 64 READY ------- start target running protocol version 6 (type 1) maximum PDU size: 4096 Flash protection status: 0000 version: prism_v2.0.12137+c4ae1432f5 key_version: 1 min_rollback: 0 offset: writable at 0xc000 Current versions: Writable prism_v2.0.12137+c4ae1432f5 BUG=b:203664745,b:211496726 TEST=Run 'usb_updater2 -f' on Vell. Change-Id: Iad2140dbdf5e34332388f3f43b3ede3d22e73087 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62505 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/brya/var/vell: Change to ELAN touchpanel driverShon Wang2022-03-031-24/+9
| | | | | | | | | | | | | | | | | Disabled G2touch driver and add ELAN touchpanel driver for vell. Due to incorrect BIOS setting, touch screen IC FW can't update and work. According to ELAN's recommendations, we coreect the ELAN2513 driver's setting and change I2C address to 0x10 BUG=b:221340736 TEST=emerge-brya coreboot and can flash touch screen FW Change-Id: I22f04fa21b542e21e88c46547779cfb55beb5c12 Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62317 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: YH Lin <yueherngl@google.com>
* mb/google/brya/var/vell: Remove Rcomp settingsGaggery Tsai2022-03-021-7/+1
| | | | | | | | | | | | | | | | | | | | | | | This patch removes Rcomp settings. In MRC design, it checks if the Rcomp settings from the board is 0 or null, if so, it uses the recommended Rcomp values. Otherwise, it uses the Rcomp settings passed from the UPD. From the change history of MRC, we're chasing a moving target. This RCOMP setting in coreboot is an old setting while the Rcomp settins in MRC are optimized settings. Moving forward, if there is a new stepping, it might be changed again which increases the maintenance effort in coreboot. IMHO, we should let MRC to set the optimized RCOMP values for the design. BUG=b:219378758 TEST=emerge-byra coreboot chromeos-bootimage and boots up with QS and PRQ CPUs. Checks with MRC log and ensure the RCOMP settings are filled properly by MRC. Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com> Change-Id: I8547e187b74f9b2cee57ddad2883d60c05d0b9fb Reviewed-on: https://review.coreboot.org/c/coreboot/+/62201 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/brya/var/vell: Corrects ACPI _PLD macro settingRobert Chen2022-02-241-8/+8
| | | | | | | | | | | | | | | | | | | | | | | This patch is to denote the correct side of ACPI _PLD usb C ports. +-------------------------+ | LCD | | | | | +-------------------------+ PORT_C2 | | PORT_C1 PORT_C3 | DB MB | PORT_C0 | | +-------------------------+ BUG=b:220634230 TEST=emerge-brya coreboot Change-Id: I84515f98b6cdab5768df75690b0f5ca1bb9ad96d Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62252 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/brya/var/vell: Correct MIPI camera infoShon Wang2022-02-181-1/+1
| | | | | | | | | | | | | The CIO2 port was incorrectly set to 2, while the correct port is 1 BUG=b:210801553 TEST=Build and boot on vell, camera works correctly now Change-Id: I53d8448ed0e12777456af9b0bc65a04595b47e37 Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61946 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/brya/var/vell: Use ACPI _PLD macroSubrata Banik2022-02-181-8/+16
| | | | | | | | | | | | | This patch uses ACPI _PLD macros for USB Type A and C ports. BUG=b:216490477 TEST=emerge-brya coreboot Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I9e4837489d90c2edd7deaa2af0533085f1ff5ae6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62049 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/brya/var/vell: Fix PLD group orderSubrata Banik2022-02-181-2/+2
| | | | | | | | | | | | | | | | | In ec/google/chromeec: Add PLD to EC conn in ACPI table (667471b8d807da5a5a9277db47e069ad3b1351c7), PLD is added to ACPI table. This patch ensures USB _PLD group numbers are appear in order. BUG=b:216490477 TEST=build coreboot and system boot into OS. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ib0d1be34775c5eacf6cd9b0ec400bd42a93c59e9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62034 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
* mb/google/brya/var/vell: Add Wifi SAR for vellRobert Chen2022-02-172-0/+9
| | | | | | | | | | | | | Add wifi sar for vell BUG=b:218992598 TEST=emerge-brya coreboot-private-files-baseboard-brya coreboot chromeos-bootimage Change-Id: I74fddd1dbcb7019fd5fe394da291f125f0d4960f Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61761 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/brya/var/vell: Correct the DQ mappingGaggery Tsai2022-02-171-11/+11
| | | | | | | | | | | | | | | | | This patch corrects the DQ mapping and enable ECT. In Vell design, the DQS is swapped in Mc0.ch1, Mc0.ch3, Mc1.ch0, Mc1.ch1 and Mc1.ch2 but the DQ mappings are not swapped and that causes ECT training failure. BUT=b:208719081 TEST=emerge-brya coreboot chromeos-bootimage && ensure the system passes ECT training and all the way booting to the OS. Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com> Change-Id: Idd2ad16151f0b2b93b00295b75a66ba65cba23cd Reviewed-on: https://review.coreboot.org/c/coreboot/+/61981 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/brya/var/vell: update gpio for DMICShon Wang2022-02-141-4/+4
| | | | | | | | | | | | | | | | | Data on channel 0 & 1 are normal (from DMIC) but there is noise on channel 2 & 3, so change to NF PAD_CFG_NF(GPP_R6, NONE, DEEP, NF4) to PAD_NC(GPP_R6, NONE), PAD_CFG_NF(GPP_R7, NONE, DEEP, NF4) to PAD_NC(GPP_R7, NONE), BUG=b:210802722 TEST=FW_NAME=vell emerge-brya coreboot Change-Id: I1b5ccd2c239e526e4f1ce2d5ed6c1386303590c8 Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61033 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/var/vell: Add gpios to lockEric Lai2022-02-091-11/+11
| | | | | | | | | | | | | | | | Variant should honor locked gpios from baseboard, but not the last. Variant can add more gpios to lock if needed. BUG=b:216583542 TEST='emerge-brya coreboot chromeos-bootimage', flash and verify that vell boots successfully to kernel. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I0c39d06e3b2f39db88d924205786bfa1b27df3fe Reviewed-on: https://review.coreboot.org/c/coreboot/+/61704 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
* mb/google/brya/var/vell: Enable SaGvGaggery Tsai2022-02-021-0/+1
| | | | | | | | | | | | | | | | This patch enables SaGv since somehow it was accidently removed by commit a52b9c3. BUG=b:208719081 TEST=FW_NAME=vell emerge-brya coreboot Fixes:a52b9c3 ("mb/google/brya: Move gpio_pm settings for brya variants to baseboards") Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com> Change-Id: Ideae3dbd9746590db104d93afadbd8d574298b83 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61464 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/brya: Lock TPM pin in brask and brya baseboardsSubrata Banik2022-02-021-0/+4
| | | | | | | | | | | | | | | | This applies a configuration lock to the TPM I2C and IRQ GPIO for all brya and brask variants. BUG=b:208827718 TEST=cat /sys/kernel/debug/pinctrl/INTC1055\:00/pins suggests I2C_TPM_SDL and I2C_TPM__SDA GPIO PINs are locked. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I4f2a7014faeecd4701ea35ec77ef0e1692516b9d Reviewed-on: https://review.coreboot.org/c/coreboot/+/61499 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/brya/variants/*: Add cpu pcie rp flagsTracy Wu2022-01-171-0/+1
| | | | | | | | | | | | | | | | | | Along with commit f94405219c (soc/intel/alderlake: Hook up FSP-S CPU PCIe UPDs), we need to set cpu pcie rp flags in devicetree now. This CL is to add proper cpu pcie flags (PCIE_RP_LTR and PCIE_RP_AER) in all intel projects or system will be blocked at PKGC2R with root port LTR not enable. BUG=b:214009181 TEST=Build and DUT (Kano) can enter deeper PKGC state normally. Signed-off-by: Tracy Wu <tracy.wu@intel.corp-partner.google.com> Change-Id: I0d8721bf1454448b7fc14655f0e4513001469a18 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61073 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/brya: Move gpio_pm settings for brya variants to baseboardsTim Wawrzynczak2022-01-121-12/+0
| | | | | | | | | | | | | | | The factory versions (minor version 22) of cr50 FW have an issue with producing short interrupt pulses, which can be missed by the ADL PCH if autonomous GPIO power management is enabled, therefore instead of continually adding the setting to all the variants, move it to the baseboard instead. Change-Id: I337f1e9e8f958c02bb73e6701a06c0b88a4757d7 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60872 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
* src/mainboard/google: Remove unused <console/console.h>Elyes HAOUAS2022-01-101-1/+0
| | | | | | | | | | | Found using: diff <(git grep -l '#include <console/console.h>' -- src/) <(git grep -l 'console_time_report\|console_time_get_and_reset\|do_putchar\|vprintk\|printk\|console_log_level\|console_init\|get_log_level\|CONSOLE_ENABLE\|get_console_loglevel\|die_notify\|die_with_post_code\|die\|arch_post_code\|mainboard_post\|post_code\|RAM_SPEW\|RAM_DEBUG\|BIOS_EMERG\|BIOS_ALERT\|BIOS_CRIT\|BIOS_ERR\|BIOS_WARNING\|BIOS_NOTICE\|BIOS_INFO\|BIOS_DEBUG\|BIOS_SPEW\|BIOS_NEVER' -- src/) |grep "<" Change-Id: I3a6a64273e3883942655272a544c41e90ef519fd Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60916 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/brya/var/vell: Enable SaGvRobert Chen2022-01-102-1/+3
| | | | | | | | | | | | | Enable SaGv support for vell BUG=b:208719081 TEST=FW_NAME=vell emerge-brya coreboot Change-Id: I01e3da449e2cf53278f625ca265d09f7a1869ef7 Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60811 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
* mb/google/brya/var/vell: Add MIPI camera infoShon Wang2022-01-072-0/+71
| | | | | | | | | | | | | | Add OVTI8856 information for vell: BUG=b:210801553 TEST=Build and boot on vell Change-Id: I43de859cd0cdd9fe21c16cabfad511ed0b368ee3 Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60276 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
* mb/google/brya/var/vell: Swap TPM I2C with touchscreen I2CShon Wang2022-01-072-7/+28
| | | | | | | | | | | | | | | | According to the latest schematic for the next build phase, exchange I2C port for TPM/touchscreen. TPM: I2C3 -> I2C1 Touchscreen: I2C1 -> I2C3 BUG=b:210572663 TEST=FW_NAME=vell emerge-brya coreboot Change-Id: If72717a2c073f5b871c3109399f466a04a9d2484 Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60106 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/brya/var/vell: update overridetree for DPShon Wang2022-01-041-34/+38
| | | | | | | | | | | | | update override devicetree for type-c display based on schematics BUG=b:209489126 TEST=emerge-brya coreboot Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com> Change-Id: Icd2f5de38df0eb89fb92ea2abe25851c0d6ec53f Reviewed-on: https://review.coreboot.org/c/coreboot/+/60251 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/taniks,vell;mb/intel/adlrvp_n_ext_ec: fix build errorFelix Held2021-12-241-4/+4
| | | | | | | | | | | | | | | | | | | | | Commit d448f8ce0fe9955e7792f54cc278897152d53590 (drivers/intel/pmc_mux/ conn: Change usb{23}_port_number fields to device pointers) changed the way the pmc_mux/conn driver gets the corresponding USB ports from the devicetree. This change didn't include the corresponding change for the Taniks and Vell variants of the Google Brya project and the Intel adlrvp_n_ext_ec board which probably weren't in the tree at the time the patch referenced above was created. This patch ports the needed change forward to those boards to fix the build of the upstream tree. TEST=None Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id295cd11fbbfe038534b154215a6de7c1ac13e0e Reviewed-on: https://review.coreboot.org/c/coreboot/+/60329 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
* mb/google/brya/var/vell: Add Hynix LP5 DRAM supportKevin Chiu2021-12-233-1/+3
| | | | | | | | | | | | | | | | Add Hynix H9JCNNNCP3MLYR-N6E LP5 DRAM part for vell: DRAM Part Name ID to assign H9JCNNNCP3MLYR-N6E 1 (0001) BUG=b:204284866 TEST=emerge-brya coreboot Change-Id: I1ec2985fa1f1c488ee3a9c5e34f7b370d16cf98e Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60288 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/brya/var/vell: update overridetree for SSD setting=2021-12-231-2/+2
| | | | | | | | | | | | | Change CLKSRC#3 to CLKSRC#1 in override devicetree based on schematics BUG=b:208756696 TEST=emerge-brya coreboot Change-Id: I4d452eaa690a91814739cc1b80966fc3a9f1be37 Signed-off-by: = <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60099 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/brya/var/vell: update overridetree for touchpad=2021-12-231-6/+16
| | | | | | | | | | | | | update override devicetree for touchpad based on schematics BUG=b:209554950 TEST=emerge-brya coreboot Change-Id: I835958349537ed490191db7c8e35847630de64ed Signed-off-by: = <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60098 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/brya/var/vell: update memory settingsShon Wang2021-12-202-0/+104
| | | | | | | | | | | | | | | | DQ/DQS info from Intel_Platform_DQ_DQS_RCOMP_Info_Utility GPIO_MEN_CONFIG_0 GPP_E11 to GPP_E3 GPIO_MEN_CONFIG_3 GPP_E12 to GPP_E7 GPIO_MEM_CH_SEL_GPP_E5 GPP_E13 to GPP_E5 BUG=b:205908918 TEST=emerge-brya coreboot Change-Id: Ic0bbac5eaebc77639be6c1bc399658ac90e72fbb Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59334 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/brya/var/vell: update gpio overrideKevin Chiu2021-12-202-0/+181
| | | | | | | | | | | | | Configure GPIOs according to schematics BUG=b:205908918 TEST=emerge-brya coreboot Change-Id: Icc91866f7555c294af7eed9e5d1550e73d8059d0 Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59305 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/brya/var/*: Add disable_gpio_export_in_crs to all devicetreesTim Wawrzynczak2021-12-201-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | None of the touchscreens used in the brya program (any brya board) should require exporting of GPIOs in the ACPI _CRS method for any i2c device. This can cause i2c devices to malfunction or cause timing sequence violations if: 1) ACPI exports a PowerResource for the device that uses GPIOs that are also exported in _CRS 2) The kernel driver for the device uses the GPIOs exported in _CRS for its own purposes. This means the state of the pin is out of sync between platform firmware and the kernel. The Linux ELAN I2C touchcsreen driver (https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/third_party/kernel/upstream/drivers/input/touchscreen/elants_i2c.c;l=1429) is one example of this. Therefore, add disable_gpio_export_in_crs to all brya variants that use the drivers/i2c/generic or drivers/i2c/hid chip drivers. Change-Id: Ib4475bd0dc885e230911de6298fd95baa868ef29 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60175 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* mb/google/brya/var/vell: update overridetreeKevin Chiu2021-12-161-3/+336
| | | | | | | | | | | | | Init basic override devicetree based on initial schematics BUG=b:205908918 TEST=emerge-brya coreboot Change-Id: Ibaa910eb1c5584197907963781258035c668298e Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59304 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/brya/var/vell: Generate LP5 RAM IDKevin Chiu2021-11-163-4/+16
| | | | | | | | | | | | | | | | | Add the support LP5 RAM parts for vell: DRAM Part Name ID to assign MT62F512M32D2DR-031 WT:B 0 (0000) MT62F1G32D4DR-031 WT:B 1 (0001) BUG=b:204284866 TEST=emerge-brya coreboot Change-Id: I49745948ebdb25fd98e285defd75714f80271968 Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59288 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
* mb/google/brya: Create vell variantShon Wang2021-11-156-0/+39
Create the vell variant of the brya0 reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:205908918 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_VELL Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com> Change-Id: Ide8ba1c0dd9b5d9ad90556053abf2a597136a10c Reviewed-on: https://review.coreboot.org/c/coreboot/+/59242 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-15 16:45:46 +0000