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The Kingler board has an SD card reader connected via USB and can be
enabled by setting GPIO EN_PP3300_SDBRDG_X to output mode and activated.
BUG=b:211385131
TEST=boot kernel using SD card.
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I903731ea4906328b2f0f5a7c6c06bd9c964d24ec
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60780
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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ANX7625 is used on Kingler board as the eDP bridge IC. Enable ANX7625
and configure display in mainboard_init() to support display in
firmware screen.
BUG=b:209930699
TEST=saw firmware display on eDP panel of kingler board.
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: Ie8de5d8ba150d3ae086c7635601dbc0846aebe91
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60398
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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To save the S3 power, USB3_HUB_RST_L is externally pulled up to a weak
resistor, so we have to reset the hub as early as possible.
Otherwise the USB3 hub may be not usable. Therefore, move USB3 HUB
reset function to bootblock.
BUG=b:210065282
TEST=build pass
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I92feb2316302fda32478b24c014bcd380d0ac55d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60088
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Set open-drain GPIOs for ChromeOS as input and high-z mode.
After applying this patch, we can measure these pins from 1.0V to
correct voltage (1.8V) to prevent wrong judgement of low/high.
Reference document:
MT8186_SoC_Pinmux_V1_1
BUG=b:209342636
TEST=measure pins voltage 1.8V on kingler board
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: Ib55a773bb63404a1b952f7e7645eb7aba6638b00
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60002
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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Configure Chromebook specific GPIOs, including EC_AP_INT,
EC_IN_RW, GSC_AP_INT, EN_SPK, GPIO_AP, and GPIO_RESET.
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I76bde75788889111c0a051eed731dadc9898c0e1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59565
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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