summaryrefslogtreecommitdiffstats
path: root/src/mainboard/google/corsola
Commit message (Collapse)AuthorAgeFilesLines
* mb/google: Replace some strings in regulator.cRex-BC Chen2022-07-213-7/+6
| | | | | | | | | | | | | | | | From comments of CB:65875, we replace *_vol to *_voltage. s/mainboard_set_regulator_vol/mainboard_set_regulator_voltage/ s/mainboard_get_regulator_vol/mainboard_get_regulator_voltage/ TEST=build pass BUG=b:233720142 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: Iadf0408e8914d6e32915464f93979978c4634eaf Reviewed-on: https://review.coreboot.org/c/coreboot/+/65994 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* mg/google/corsola: Enable TI50_FIRMWARE_VERSION_NOT_SUPPORTEDYu-Ping Wu2022-07-211-0/+2
| | | | | | | | | | | | | | | | | | | | | Ti50 hasn't implemented version reading yet. To avoid the confusing error message Did not recognize Cr50 version format enable TI50_FIRMWARE_VERSION_NOT_SUPPORTED to make clear that this feature is not supported. BUG=b:234533588 TEST=emerge-corsola coreboot BRANCH=none Change-Id: I18dd4b5bc05c2af06627275968e49aba048ba05e Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65839 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@chromium.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
* treewide: Unify Google brandingJon Murphy2022-07-041-1/+1
| | | | | | | | | | | | | | | | | Branding changes to unify and update Chrome OS to ChromeOS (removing the space). This CL also includes changing Chromium OS to ChromiumOS as well. BUG=None TEST=N/A Change-Id: I39af9f1069b62747dbfeebdd62d85fabfa655dcd Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65479 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* mb/google/corsola: Decide EC-is-trusted logic by board revYu-Ping Wu2022-06-301-1/+16
| | | | | | | | | | | | | | | | Kingler and Krabby's rev 0 boards both have Cr50 instead of Ti50. In order to support them with the new firmware where TPM_GOOGLE_TI50 is selected, use the board rev to determine the EC-is-trusted logic. BUG=b:237355198 TEST=emerge-corsola coreboot BRANCH=none Change-Id: I7797eafaa7a35355d241c4ea425a4716a35a7817 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65472 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
* mb/google/corsola: Add new board TentacruelKane Chen2022-06-272-1/+7
| | | | | | | | | | | | | | Add a new board 'Tentacruel', and enable SDCARD_INIT for it. BUG=b:234409654 BRANCH=corsola TEST=none Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com> Change-Id: Ia10efeead575b4e193a73562275a78839415a706 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65192 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/corsola: Fix PS8640 power-on T6 sequenceRuihai Zhou2022-06-121-0/+2
| | | | | | | | | | | | | | | | | | | The T6 of PS8640 power on sequence should be larger than 0ms, but it's -0.062ms now. Add 100us delay between VRF12 and VCN33. The PS8640 power-on sequence is described in the "PS8640_DS_V1.4_20200210.docx". BUG=b:235448279 BRANCH=None TEST=The sequence T6 is larger than 0ms when power on. Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com> Change-Id: I0b8a37d6119dc027a9d1c0a62c087b0a7ef14cac Reviewed-on: https://review.coreboot.org/c/coreboot/+/65084 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: zanxi chen <chenzanxi@huaqin.corp-partner.google.com> Reviewed-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Reviewed-by: Yidi Lin <yidilin@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* mb/google/corsola: Correct EC-is-trusted logicYu-Ping Wu2022-06-081-0/+4
| | | | | | | | | | | | | | | | | | | | | | | With Cr50, the GPIO EC_IN_RW_ODL is used to determine whether EC is trusted. However, with Ti50 where corsola has been switched to, it is determined by Ti50's boot mode. If the boot mode is TRUSTED_RO, the VB2_CONTEXT_EC_TRUSTED flag will be set in check_boot_mode(). Therefore in the Ti50 case get_ec_is_trusted() can just return 0. The current code of get_ec_is_trusted() only checks the GPIO, which causes the EC to be always considered "trusted". Therefore, correct the return value to 0 for TPM_GOOGLE_TI50. BUG=b:235053870 TEST=emerge-corsola coreboot TEST=firmware-DevMode passed in kingler (with Ti50) BRANCH=none Change-Id: I59b16238bfb487832ef618668c0f9addc1ee7937 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64998 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/corsola: Enable ps8640 for steelixZanxi Chen2022-06-082-6/+6
| | | | | | | | | | | | | | | | Currently, the display does not work in steelix. Steelix uses ps8640 eDP bridge IC, which is different from its reference board kingler. So we should enable ps8640 for steelix. BUG=b:232195941 TEST=firmware bootsplash is shown on eDP panel of steelix. Change-Id: I8c6310794c89fc8aa0e69e114c1f7ebd5479c549 Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64790 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: wen zhang <zhangwen6@huaqin.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* mb/google/corsola: Add new board 'steelix'Zanxi Chen2022-06-012-0/+5
| | | | | | | | | | | | | | Add a new kingler follower 'steelix'. BUG=b:232195941 TEST=make # select steelix Change-Id: Idd2ed1404cde72ecdb6cc3a262e793a6272aa871 Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64789 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: wen zhang <zhangwen6@huaqin.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* mainboard/google/corsola: Fix incorrect timestamps in the eventlogYidi Lin2022-05-241-0/+1
| | | | | | | | | | | | | | | Timestamp '2000-00-00 00:00:00' is considered as the invalid format. Enable RTC to fix incorrect timestamp format in the eventlog. BUG=b:232035991 TEST=check the timestamp field in /var/log/eventlog.txt Change-Id: I8d9822075377734ef4a609ddeee79385fe7af0f0 Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64585 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
* mb/google/corsola: Enable TPM_GOOGLE_TI50Yu-Ping Wu2022-05-121-1/+1
| | | | | | | | | | | | | | Replace TPM_GOOGLE_CR50 with TPM_GOOGLE_TI50. BUG=b:232066387 TEST=emerge-corsola coreboot BRANCH=none Change-Id: I0cc787b3104bc47f6f856497bbc0870e0519dc28 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64252 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/corsola: Add RO_GSCVD area to FMAPYu-Ping Wu2022-04-271-0/+1
| | | | | | | | | | | | | | | This area is used for storing AP RO verification data. BUG=b:229670703 TEST=emerge-corsola coreboot TEST=cbfstool /build/corsola/firmware/kingler/coreboot.rom layout BRANCH=none Change-Id: Id0a3304920c80987319d8072b8e443c41c1f1c47 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63781 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
* tpm: Refactor TPM Kconfig dimensionsJes B. Klinke2022-04-211-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Break TPM related Kconfig into the following dimensions: TPM transport support: config CRB_TPM config I2C_TPM config SPI_TPM config MEMORY_MAPPED_TPM (new) TPM brand, not defining any of these is valid, and result in "generic" support: config TPM_ATMEL (new) config TPM_GOOGLE (new) config TPM_GOOGLE_CR50 (new, implies TPM_GOOGLE) config TPM_GOOGLE_TI50 (new to be used later, implies TPM_GOOGLE) What protocol the TPM chip supports: config MAINBOARD_HAS_TPM1 config MAINBOARD_HAS_TPM2 What the user chooses to compile (restricted by the above): config NO_TPM config TPM1 config TPM2 The following Kconfigs will be replaced as indicated: config TPM_CR50 -> TPM_GOOGLE config MAINBOARD_HAS_CRB_TPM -> CRB_TPM config MAINBOARD_HAS_I2C_TPM_ATMEL -> I2C_TPM && TPM_ATMEL config MAINBOARD_HAS_I2C_TPM_CR50 -> I2C_TPM && TPM_GOOGLE config MAINBOARD_HAS_I2C_TPM_GENERIC -> I2C_TPM && !TPM_GOOGLE && !TPM_ATMEL config MAINBOARD_HAS_LPC_TPM -> MEMORY_MAPPED_TPM config MAINBOARD_HAS_SPI_TPM -> SPI_TPM && !TPM_GOOGLE && !TPM_ATMEL config MAINBOARD_HAS_SPI_TPM_CR50 -> SPI_TPM && TPM_GOOGLE Signed-off-by: Jes B. Klinke <jbk@chromium.org> Change-Id: I4656b2b90363b8dfd008dc281ad591862fe2cc9e Reviewed-on: https://review.coreboot.org/c/coreboot/+/63424 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* mb/google: Remove unused cpu deviceYu-Ping Wu2022-03-211-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | The cpu device listed in MediaTek platforms' devicetree.cb doesn't actually do anything, except causing an error during device initialization: CPU: 00 missing read_resources Therefore, remove it from the devicetree. BUG=b:224419346 TEST=emerge-corsola coreboot TEST=Krabby booted up successfully BRANCH=none Change-Id: Ibf9f7cf65da6a0dd0a0e1f556d5772573ba3e930 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62805 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/corsola: Revise power-on sequence of PS8640Rex-BC Chen2022-03-211-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Although the panel initializes fine and the fw recovery screen is displayed without issues, the current power-on sequence of the PS8640 violates the spec of the PS8640, which can be confirmed by measuring it with an oscilloscope. The sequence is: - set VDD12 to be 1.2V - set VDD33 to be 3.3V - pull hign PD# - pull down RST# - delay 2ms - pull high RST# - delay more than 50ms (55ms for margin) - pull down RST# - delay more than 50ms (55ms for margin) - pull high RST# This flow will increase 110ms if firmware display is enabled in krabby. For normal booting flow, the firmware will not be enabled, so it will meet boot time requirements of Chrome OS. (Less than 1s.) Datasheet name: PS8640_DS_V1.4_20200210.docx. Chapter: 14. BUG=b:222650141 TEST=show fw display normally in krabby. TEST=result of waveform meets the spec. Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I7706c56dc7fc13ac84c0d52a6e534bc0988e8fd3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62893 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* mb/google/corsola: Enable the SD card readerRex-BC Chen2022-01-073-2/+9
| | | | | | | | | | | | | | The Kingler board has an SD card reader connected via USB and can be enabled by setting GPIO EN_PP3300_SDBRDG_X to output mode and activated. BUG=b:211385131 TEST=boot kernel using SD card. Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I903731ea4906328b2f0f5a7c6c06bd9c964d24ec Reviewed-on: https://review.coreboot.org/c/coreboot/+/60780 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/corsola: Configure audioRex-BC Chen2022-01-061-0/+13
| | | | | | | | | | | | | | | | | | | According schematics, we configure audio by turning on setting of audio power and selecting I2S pin-mux. Schematics references: kingler: schematic_kingler_proto0_gerber_20211115.pdf krabby: crab_proto 0_20211112_final.pdf BUG=b:204164695 TEST=Verified by CLI command(badusbbeep/devbeep) on kingler and krabby Signed-off-by: Jiaxin Yu <jiaxin.yu@mediatek.com> Change-Id: Ia6374d0e5535b7cff4df8759312786fef8b94b6b Reviewed-on: https://review.coreboot.org/c/coreboot/+/60738 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
* mb/google/corsola: Initialize krabby displayRex-BC Chen2022-01-013-25/+89
| | | | | | | | | | | | | | | PS8640 is used on Krabby board as the eDP bridge IC. Enable PS8640 and configure display in mainboard_init() to support display in firmware screen. BUG=b:210806060 TEST=saw firmware display on eDP panel of krabby and kingler. Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I314d5407c40429bb7bc50f36fece58e396b27548 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60447 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/corsola: Remove 'corsola' from Kconfig board namesRex-BC Chen2022-01-012-7/+0
| | | | | | | | | | | | | | | | The 'Corsola' (MT8186 Chromebooks) family has two reference designs (Krabby and Kingler) and all real implementations should follow either one of the two. To prevent confusion, we should remove the 'corsola' configuration from Kconfig board names. BUG=b:210806060 TEST=emerge-corsola coreboot Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: Ib354054e358c0783f6221c2e2a1730b5c6ddba33 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60515 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/mediatek/mt8186: Add support for regulator VRF12/VCN33Rex-BC Chen2022-01-011-0/+2
| | | | | | | | | | | | | | To provide power to PS8640, the eDP bridge IC on krabby, add control of VRF12 and VCN33 to set voltage from MT6366. TEST=measure 1.2V from VRF12 and 3.3V from VCN33. BUG=b:210806060 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I55a9ca16e1e335e9355d0a1b30c278a9969db197 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60446 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* mb/google/corsola: Initialize kingler displayRex-BC Chen2021-12-296-1/+145
| | | | | | | | | | | | | | | ANX7625 is used on Kingler board as the eDP bridge IC. Enable ANX7625 and configure display in mainboard_init() to support display in firmware screen. BUG=b:209930699 TEST=saw firmware display on eDP panel of kingler board. Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: Ie8de5d8ba150d3ae086c7635601dbc0846aebe91 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60398 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* mb/google/corsola: Add board common config for kingler and krabbyRex-BC Chen2021-12-292-2/+14
| | | | | | | | | | | | | | Add common configs to help implementing board-specific logic (for example using different eDP bridge IC drivers). BUG=b:209930699 TEST=build pass Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: If775532c1a262f3e8b3f11b24cae555844f2bfec Reviewed-on: https://review.coreboot.org/c/coreboot/+/60395 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* mb/google/corsola: Fully calibrate DRAMRyan Chuang2021-12-293-0/+18
| | | | | | | | | | | | | | | | | Initialize and calibrate DRAM in romstage. DRAM full calibration logs: dram_init: dram init end (result: 1) DRAM-K: Full calibration passed in 20014 msecs TEST=DRAM full calibration pass. BUG=b:202871018 Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.corp-partner.google.com> Change-Id: I80a18a8be5b1d47a5f0f7afed9601c0884e69035 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60386 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* mb/google/corsola: move USB3 HUB reset funtion to bootblockRex-BC Chen2021-12-152-0/+8
| | | | | | | | | | | | | | | | To save the S3 power, USB3_HUB_RST_L is externally pulled up to a weak resistor, so we have to reset the hub as early as possible. Otherwise the USB3 hub may be not usable. Therefore, move USB3 HUB reset function to bootblock. BUG=b:210065282 TEST=build pass Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I92feb2316302fda32478b24c014bcd380d0ac55d Reviewed-on: https://review.coreboot.org/c/coreboot/+/60088 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/corsola: set up open-drain ChromeOS pinsRex-BC Chen2021-12-143-19/+46
| | | | | | | | | | | | | | | | | | Set open-drain GPIOs for ChromeOS as input and high-z mode. After applying this patch, we can measure these pins from 1.0V to correct voltage (1.8V) to prevent wrong judgement of low/high. Reference document: MT8186_SoC_Pinmux_V1_1 BUG=b:209342636 TEST=measure pins voltage 1.8V on kingler board Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: Ib55a773bb63404a1b952f7e7645eb7aba6638b00 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60002 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* mb/google/corsola: Pass reset gpio parameter to BL31Rex-BC Chen2021-12-091-0/+18
| | | | | | | | | | | | | | | To support gpio reset SoC, we need to pass the reset gpio parameter to BL31. TEST=build pass BUG=b:202871018 Cq-Depend: chromium:3188686 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I48d8d004ea92e950d0040a11133c57c121b86af3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59824 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* mb/google/corsola: correct NOR flash configuration in GPIO setRex-BC Chen2021-12-091-1/+1
| | | | | | | | | | | | | | | | | | | | The reference design has changed to use GPIO SET1 for NOR flash. There are no devices already built using SET0 so we can safely change the implementation without conditional configs. Reference document: kingler_mt8186_mt6366_lpddr4x_e.pdf, page 11. crab_proto 0_2021112.pdf, page 11. BUG=b:202871018 TEST=flash verify pass on kingler on bootblock stage Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I031686ccddcf789f3fa966d113ee48949e454b8f Reviewed-on: https://review.coreboot.org/c/coreboot/+/59945 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
* mb/google/corsola: get SKU IDRex-BC Chen2021-12-092-0/+25
| | | | | | | | | | | | | | Retrieve the SKU ID for Corsola via CBI interface. If that failed (or no data found), fallback to ADC channels for SKU ID. TEST=build pass BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I2888190d498df28b5ae13cf92cc41d088e8f8ee7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59944 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* mb/google/corsola: Configure TPMRex-BC Chen2021-12-083-0/+14
| | | | | | | | | | | | | Initialize SPI bus 2 for TPM control. TEST=build pass BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I8ede68d6eb594890195e8464151c1c0f88aeee43 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59943 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* mb/google/corsola: implement get_ec_is_trustedRex-BC Chen2021-12-081-0/+6
| | | | | | | | | | | | | Set VB2_CONTEXT_EC_TRUSTED in verstage_main. TEST=build pass BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: If2837f5db52f91f5418d222d4dcd1af2aebcc105 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59942 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* mb/google/corsola: Enable Chrome ECRex-BC Chen2021-12-084-6/+17
| | | | | | | | | | | | | Initialize SPI bus 1 for Chrome EC control. TEST=build pass BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I7d032d595f7ca1dbed3de4dfe308ff4be64333cd Reviewed-on: https://review.coreboot.org/c/coreboot/+/59941 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* mb/google/corsola: Add an option for SD card initializationRex-BC Chen2021-11-262-1/+10
| | | | | | | | | | | | | | | There is no support for SD card on Corsola reference board, so we add a configuration to disable SD card initialization to prevent setting GPIOs in a mistaken way. TEST=build pass BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: Ia05fd046335c6ce6f9198ddbb7cbda2afc6ae3cc Reviewed-on: https://review.coreboot.org/c/coreboot/+/59571 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* mb/google/corsola: Get RAM code from ADCRex-BC Chen2021-11-262-0/+70
| | | | | | | | | | | | | | | On Chromebooks the RAM code is implemented by the resistor straps that we can read and decode from ADC. For Corsola the RAM code can be read from ADC channel 2 and 3. TEST=build pass BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I485c32dec7b425b604b4063d742a0e37d3961513 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59570 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* mb/google/corsola: Raise little CPU frequencyRex-BC Chen2021-11-261-0/+18
| | | | | | | | | | | | | Raise little CPU to 2GHz at romstage. TEST=check little core cpu frequency is 2GHz BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: If4c983d15beb2b588230f3db7416cb767b29978d Reviewed-on: https://review.coreboot.org/c/coreboot/+/59569 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* mb/google/corsola: Add VPROC12/VSRAM_PROC12 to regulator interfaceRex-BC Chen2021-11-261-0/+2
| | | | | | | | | | | | | | Add VPROC12/VSRAM_PROC12 to adjust power for raising little CPU frequency. TEST=build pass BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I59b4627220022a51a116716036a8ba0048039508 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59568 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* mb/google/corsola: configure GPIOsRex-BC Chen2021-11-263-1/+42
| | | | | | | | | | | Configure Chromebook specific GPIOs, including EC_AP_INT, EC_IN_RW, GSC_AP_INT, EN_SPK, GPIO_AP, and GPIO_RESET. Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I76bde75788889111c0a051eed731dadc9898c0e1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59565 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* soc/mediatek/mt8186: Add RTC and clkbuf driversYuchen Huang2021-11-171-0/+2
| | | | | | | | | | | | | Add support for RTC and clkbuf. TEST=boot to kernel and check log ok BUG=b:202871018 Signed-off-by: Yuchen Huang <yuchen.huang@mediatek.corp-partner.google.com> Change-Id: Ia02a74f685feb2466c113a77cbfa3a7d8fedb595 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59344 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* mb/google/corsola: Initialize SPMRex-BC Chen2021-11-171-0/+5
| | | | | | | | | | | | | | Initialize SPM (System Power Management) in RAM stage. This adds 55ms to the boot time. TEST=program counter of SPM is correct value(0x250) after booting up BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I822417f7a679107760b202dd43fb79d1934940bd Reviewed-on: https://review.coreboot.org/c/coreboot/+/59342 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* soc/mediatek/mt8186: add early initialization for eMMCRex-BC Chen2021-11-161-1/+1
| | | | | | | | | | | | | | | Some eMMCs need 80+ms for CMD1 to complete. And the payload may need to access eMMC in the very early stage (for example, depthcharge needs it 20ms after started) so we have to start initialization in coreboot. TEST=boot kernel from eMMC ok BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I3bc06b1fc506b1d6f54f7f456117d22477a87e29 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59294 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* mb/google/corsola: Configure eMMC and SD CardWenbin Mei2021-11-161-0/+3
| | | | | | | | | | | | | | The Corsola reference design has both eMMC and SD Card interfaces so we have to configure both in RAM stage. TEST=boot kernel from eMMC and SDCard ok BUG=b:202871018 Signed-off-by: Wenbin Mei <wenbin.mei@mediatek.com> Change-Id: I0fa8712eb61685a305dc5dd49cc2e55f1f0eecd4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59293 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* soc/mediatek/mt8186: Configure eMMC and SD CardWenbin Mei2021-11-161-0/+2
| | | | | | | | | | | | | | The Corsola reference design has both eMMC and SD Card interfaces so we have to configure both in RAM stage. TEST=build pass BUG=b:202871018 Signed-off-by: Wenbin Mei <wenbin.mei@mediatek.com> Change-Id: I2f26a8a11edd29a80a7195e3a324151d66ecb293 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59292 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* mb/google/corsola: Add VMCH and VMC for regulator interfaceRex-BC Chen2021-11-151-0/+2
| | | | | | | | | | | | | Add VMCH and VMC for providing power of SDCard. TEST=build pass BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I50fc87415086eb22ff35d157dba38cfd7594cc40 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59255 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* soc/mediatek/mt8186: add USB supportRex-BC Chen2021-11-151-0/+2
| | | | | | | | | | | | | | | 1. Enable and setup USB drivers. 2. Pull up to a weak resistor for USB3_HUB_RST_L and we reset the hub via GPIO149. TEST=boot kernel from USB ok BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: Ifcc11d51b0c1e495477957111e6021ef8275f629 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59251 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* mb/google/corsola: Implement regulator interfaceRex-BC Chen2021-11-152-0/+46
| | | | | | | | | | | | | Use regulator interface to use regulator more easily. TEST=build pass BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: Ied43cba51036c62a120df2afffeb63b5d73f012b Reviewed-on: https://review.coreboot.org/c/coreboot/+/59250 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* mb/google/corsola: add configuration for kingler and krabbyRex-BC Chen2021-11-152-0/+10
| | | | | | | | | | | | | | The 'corsola' reference design will include two implementations with different BOM selections - 'krabby' and 'kingler'. TEST=none BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: Iaf9c6af1a395030937a9a5c00e95d7246ddcb6eb Reviewed-on: https://review.coreboot.org/c/coreboot/+/59249 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* soc/mediatek/mt8186: Add support for PMIC MT6366James Lo2021-11-151-0/+2
| | | | | | | | | | | | | Add basic support for VCORE/VDRAM1/VDDQ of MT6366. TEST=build pass BUG=b:202871018 Signed-off-by: James Lo <james.lo@mediatek.corp-partner.google.com> Change-Id: I22e30421560a32f4a9e15899e8150376b1414494 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59245 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* mb/google/corsola: Add NOR-Flash supportRex-BC Chen2021-11-052-0/+6
| | | | | | | | | | | | | Add NOR-Flash drivers to pass verification of flash at verstage. TEST=boot to romstage BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: Iee3dd336632b0cf998f5f7c1d118e01e8270e815 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58838 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* mb/google/corsola: Add MediaTek MT8186 reference boardRex-BC Chen2021-11-0312-0/+161
Add mainboard folder and drivers for new reference board 'Corsola'. TEST=build pass BUG=b:200134633 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I2d701c03c97d3253effb6e93a2d55dcf6cf02db6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58648 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-10 00:46:25 +0000