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* soc/intel/jasperlake: Drop redundant PcieRpEnableNico Huber2024-02-1911-55/+14
| | | | | | | | | | | | | | | | The PcieRpEnable option is redundant to our on/off setting in the devicetrees. Let's use the common coreboot infrastructure instead. Thanks to Nicholas for doing all the mainboard legwork! Change-Id: Iea7f616f6db579c06722369c08de7cf7261dece8 Signed-off-by: Nico Huber <nico.h@gmx.de> Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79919 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/dedede/var/beadrix: Disable un-used C1 port by daughterboardKevin Yang2024-02-191-0/+18
| | | | | | | | | | | | | | | Probe usb ports by FW_CONFIG setting to disable C1 port on beadrix poin2 new daughterboard without C1 port. BUG=b:316365055 BRANCH=firmware-dedede-13606.B TEST=emerge-dedede coreboot Change-Id: I494a922d2b04dcf7bd35680f5d95f8463e225f2d Signed-off-by: Kevin Yang <kevin.yang@ecs.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80573 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com>
* mb/google/dedede/var/beadrix: Generate SPD ID for supported memory partKevin Yang2024-02-193-2/+5
| | | | | | | | | | | | | | | | Add beadrix supported memory parts in mem_parts_used.txt, generate SPD id for this part. 1. CXMT CXDB4CBAM-ML-A BUG=b:321830738 TEST=Use part_id_gen to generate related settings Change-Id: I3a6925395b52dc7aa5c0f93b8820099369db4dbf Signed-off-by: Kevin Yang <kevin.yang@ecs.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79887 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com>
* soc/intel/jasperlake: select SOC_INTEL_COMMON_BLOCK_DTTMatt DeVillier2024-02-181-1/+0
| | | | | | | | | | | | | Select this at the SoC level (like other modern Intel SoCs), and drop it from individual boards which selected it. Change-Id: I8ebb915fbc21f82e39304473b0fcaa620559b5d5 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80558 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/getac to mb/intel: Add SPDX license headers to Kconfig filesMartin Roth2024-02-182-0/+4
| | | | | | | | | Change-Id: Id859c981d0bf5dcf90bf6858607a9fe726516309 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80592 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
* mb/google/dedede/Kconfig.name: Alphabetize board listingMatt DeVillier2024-02-141-54/+54
| | | | | | | | Change-Id: I7230bb8f9883f186c10f41132a2919c3fd99f8c1 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80492 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
* mb/google/dedede/Kconfig: Alphabetize selections for baseboardsMatt DeVillier2024-02-141-8/+8
| | | | | | | | Change-Id: I245eb8a9961e3e0025c0275f306a4d989b532331 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80491 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/dedede/Kconfig: Alphabetize variant board listingsMatt DeVillier2024-02-141-139/+139
| | | | | | | | Change-Id: I2909375d38c37332293bd7928ae33d5bb502694f Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80490 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/dedede: Add VBTs and select INTEL_GMA_HAVE_VBTMatt DeVillier2024-02-1420-0/+19
| | | | | | | | | | Vbt data files extracted from dedede recovery image 120.0.6099.272. Change-Id: I28485d501e519cdaa06c55c20eba07190c5c6b6f Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80489 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
* mb/google/dedede/var/galtic: Support for Samsung K4U6E3S4AB-MGCLDaniel Peng2024-01-263-3/+5
| | | | | | | | | | | | | | | | | | | | Add the new memory support: Samsung K4U6E3S4AB-MGCL BUG=b:320137193 BRANCH=firmware-dedede-13606.B TEST=Run command "go run ./util/spd_tools/src/part_id_gen/\ part_id_gen.go JSL lp4x \ src/mainboard/google/dedede/variants/galtic/memory/ \ src/mainboard/google/dedede/variants/galtic/memory/\ mem_parts_used.txt" Change-Id: I3f6c784a194e141a3dd1e5a37b3cf12106e692d6 Signed-off-by: Daniel Peng <Daniel_Peng@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80150 Reviewed-by: Daniel Peng <daniel_peng@pegatron.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com>
* mb/google/dedede/var/metaknight:Add fw_config probe for multi codecMorris Hsu2024-01-251-1/+23
| | | | | | | | | | | | | | | and amplifier Compatible headphone codec "ALC5682I-VS" and speaker amplifier "ALC1015Q-VB" BUG=b:183305590 TEST=ALC5682I-VD and ALC1015Q-VB can work normally Change-Id: I4f212f063a1180d7a1c14769f61b0afef7565cad Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79831 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* */mem_parts_used.txt: Change Makefile.inc to Makefile.mkMartin Roth2024-01-2414-14/+14
| | | | | | | | | | | | Now that the files are renamed, make sure all references to Makefile.inc are updated as well. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I09e235eecf0c32c80a41bfcbbd3580cce6555e10 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80112 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Eric Lai <ericllai@google.com>
* mb/google/daisy to foster: Rename Makefiles from .inc to .mkMartin Roth2024-01-2463-0/+0
| | | | | | | | | | | | | | | | The .inc suffix is confusing to various tools as it's not specific to Makefiles. This means that editors don't recognize the files, and don't open them with highlighting and any other specific editor functionality. This issue is also seen in the release notes generation script where Makefiles get renamed before running cloc. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I134acc26c0a79d974a6dd0a3b257f961db7e2d86 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80106 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
* mb/google/dedede/var/galtic: Correct name for mem-part K4U6E3S4AA-MGCRDaniel Peng2024-01-223-4/+4
| | | | | | | | | | | | | | | | | | | | | | Repo sync code recently, run command as memtioned in TEST and found the changed for the auto-gen files. Then correct the memory typo from K4UBE3D4AA-MGCR to K4U6E3S4AA-MGCR, and no new for the used hex file. BUG=b:320181366 BRANCH=firmware-dedede-13606.B TEST=Run command "go run ./util/spd_tools/src/part_id_gen/\ part_id_gen.go JSL lp4x \ src/mainboard/google/dedede/variants/galtic/memory/ \ src/mainboard/google/dedede/variants/galtic/memory/\ mem_parts_used.txt" Change-Id: I7c158eb7b4455cde839a335913e6a18895c12b41 Signed-off-by: Daniel Peng <Daniel_Peng@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79976 Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Daniel Peng <daniel_peng@pegatron.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/dedede/var/pirika: Add initial fw_config configuration settingDaniel Peng2024-01-182-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | 1. Describe the FW_CONFIG probe for the settings for Palutena. - WIFI_SAR_ID_0 for AW Wi-Fi module AW-CM421NF - WIFI_SAR_ID_1 for Intel Wi-Fi module AX211NGW 2. In contrast to the AW Wi-Fi module, the Intel Wi-Fi module needs to load a SAR table in dedede platform. 3. For Palutena project, the SKU ID segment of Palutena is set for "0x350000~0x35FFFF". BUG=b:319792428 BRANCH=firmware-dedede-13606.B TEST=build pass Change-Id: Ic4f38928d24c4398d90df226cfe0788a30075bf2 Signed-off-by: Daniel Peng <Daniel_Peng@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79930 Reviewed-by: Daniel Peng <daniel_peng@pegatron.corp-partner.google.com> Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com>
* tree: Remove duplicated includesElyes Haouas2024-01-131-1/+0
| | | | | | | | | | Change-Id: I09dd5871cb366ef95410efc1ca6c4337f23b52fd Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79912 Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* mb/google/dedede: Create dita variantSheng-Liang Pan2023-12-3112-0/+524
| | | | | | | | | | | | | | | | | Create the dita variant of the taranza project by copying the files to a new directory named for the variant. BUG=b:317292413 BRANCH=dedede TEST=util/abuild/abuild -p none -t google/dedede -x -a make sure the build includes GOOGLE_DITA Signed-off-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com> Change-Id: I843e33f30cd356e4f12330bdfe2d53a0b3920ef3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79655 Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
* mb/google: Reduce DA7219 mic detect threshold to 200ohmTerry Cheong2023-12-155-5/+5
| | | | | | | | | | | | | | | | | The original DA7219 is designed to use a 500ohm mic detection threshold. Some headset mics (e.g. Logitech H111) have a lower DC impedance that is lower than the threshold and thus cannot be detected. Lower the threshold to 200ohm to match the new default value provided by Renasas as in https://patchwork.kernel.org/project/alsa-devel/patch/20231201042933.26392-1-David.Rau.opensource@dm.renesas.com/ to support such headsets. BUG=b:314062160,b:308207450 Change-Id: I6415e84a4622e0c61bc74b94536fe734048a043f Signed-off-by: Terry Cheong <htcheong@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79436 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
* mb/google/dedede/var/pirika: Add support for new memory CXMT CXDB4CBAM-ML-ADaniel_Peng2023-11-153-2/+5
| | | | | | | | | | | | | | | | | | | | | | Add support for the new memory CXMT CXDB4CBAM-ML-A. BUG=b:304932936 BRANCH=firmware-dedede-13606.B TEST=Run command "go run \ ./util/spd_tools/src/part_id_gen/part_id_gen.go \ JSL lp4x src/mainboard/google/dedede/variants/pirika/memory/ \ src/mainboard/google/dedede/variants/pirika/memory/\ mem_parts_used.txt" And confirm the mainboard boot normally with CXMT CXDB4CBAM-ML-A memory. Change-Id: Iff2ed16bcbc9b0755e60a284246aa928625fa26a Signed-off-by: Daniel_Peng <Daniel_Peng@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78892 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Daniel Peng <daniel_peng@pegatron.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* mb/{google,intel}: Update FMD to support CBFS verificationAnil Kumar2023-11-012-12/+8
| | | | | | | | | | | | | | | | | This patch adds the required FMD changes to support the change in cse_lite 'commit Ie0266e50463926b8d377825 ("remove cbfs_unverified_area_map() API in cse_lite")' for CBFS verification. With the change in cse_lite the ME_RW_A/B blobs are now part of FW_MAIN_A/B and corresponding entries in FMD can be removed for boards that currently use them. BUG=b:284382452 Signed-off-by: Anil Kumar <anil.kumar.k@intel.com> Change-Id: I3ca88fee181f059852923d50292b24c0e5b9fd6d Reviewed-on: https://review.coreboot.org/c/coreboot/+/78502 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* devicetrees: Remove trailing backslash from multiline valuesFelix Singer2023-10-253-26/+26
| | | | | | | | | | | | It's not needed to put a backslash at the end of a line for quoted multiline values. Thus, remove it. Change-Id: I1b83d53598ba2adeed853a96d6c2c1a21f01a9f7 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78576 Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* mb/google/dedede: Add HPD GPIOs on dexi variantKenneth Chan2023-10-231-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some Type-C monitors do not immediately assert HPD. If we enter FSP-S before HDP is asserted, display initialisation may fail. So wait for HPD. This is similar to commit b40c6009141e ("mainboard/hatch: Fix puff DP output on cold boots") on puff, except we don't use google_chromeec_wait_for_displayport() since that EC command was removed for TCPMv2 (https://crrev.com/c/4221975). Instead we use the HPD signals only. By waiting for any HPD signal (Type-C or HDMI), we skip waiting if HDMI is connected, which is the same behaviour as puff and fizz. BUG=b:303533815 BRANCH=dedede TEST=On dexi, connect a display via a Type-C to HDMI dongle and check the dev and recovery screens are now displayed correctly. Also check the logs in the following cases: Cold reboot in dev mode, Type-C to HDMI dongle: HPD ready after 800 ms Warm reboot in dev mode, Type-C to HDMI dongle: HPD ready after 0 ms Cold/warm reboot in dev mode, direct Type-C: HPD ready after 0 ms Cold/warm reboot in dev mode, direct HDMI: HPD ready after 0 ms Cold/warm reboot in dev mode, no display: HPD not ready after 3000 ms. Abort. Change-Id: Ib4fc071cac98a542072ffbeb6943bff4c988554c Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78450 Reviewed-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com> Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/dedede/var/cret: Modify Goodix touchpad HIDDtrain Hsu2023-10-231-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update Goodix touchpad HID to GDIX0000 for GXTP7288 and GXTP7863. BUG=b:305118852 BRANCH=firmware-dedede-13606.B TEST=Build and touchpads are workable # evtest for GXTP7863 No device specified, trying to scan all of /dev/input/event* Available devices: /dev/input/event0: Lid Switch /dev/input/event1: Power Button /dev/input/event2: AT Translated Set 2 keyboard /dev/input/event3: cros_ec_buttons /dev/input/event4: Elan Touchscreen /dev/input/event5: GDIX0000:00 27C6:0D51 Mouse /dev/input/event6: GDIX0000:00 27C6:0D51 Touchpad # evtest for GXTP7288 No device specified, trying to scan all of /dev/input/event* Available devices: /dev/input/event0: Lid Switch /dev/input/event1: Power Button /dev/input/event10: GDIX0000:00 27C6:01F5 Touchpad /dev/input/event11: sof-da7219max98360a Headset Jack /dev/input/event12: sof-da7219max98360a HDMI/DP,pcm=2 /dev/input/event13: sof-da7219max98360a HDMI/DP,pcm=3 /dev/input/event14: sof-da7219max98360a HDMI/DP,pcm=4 /dev/input/event2: AT Translated Set 2 keyboard /dev/input/event3: cros_ec_buttons /dev/input/event4: ELAN900C:00 04F3:2E5D /dev/input/event5: ELAN900C:00 04F3:2E5D UNKNOWN /dev/input/event6: ELAN900C:00 04F3:2E5D UNKNOWN /dev/input/event7: ELAN900C:00 04F3:2E5D Stylus /dev/input/event8: ELAN900C:00 04F3:2E5D Stylus /dev/input/event9: GDIX0000:00 27C6:01F5 Mouse Change-Id: Id2a6223bdbb2f0693149136baa853ca2efb57815 Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78503 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
* mb/google/dedede: Wait for HPD on dibbi variantsReka Norman2023-10-106-0/+105
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some Type-C monitors do not immediately assert HPD. If we enter FSP-S before HDP is asserted, display initialisation may fail. So wait for HPD. This is similar to commit b40c6009141e ("mainboard/hatch: Fix puff DP output on cold boots") on puff, except we don't use google_chromeec_wait_for_displayport() since that EC command was removed for TCPMv2 (https://crrev.com/c/4221975). Instead we use the HPD signals only. By waiting for any HPD signal (Type-C or HDMI), we skip waiting if HDMI is connected, which is the same behaviour as puff and fizz. TEST=On dibbi, connect a display via a Type-C to HDMI dongle and check the dev and recovery screens are now displayed correctly. Also check the logs in the following cases: Cold reboot in dev mode, Type-C to HDMI dongle: HPD ready after 800 ms Warm reboot in dev mode, Type-C to HDMI dongle: HPD ready after 0 ms Cold/warm reboot in dev mode, direct Type-C: HPD ready after 0 ms Cold/warm reboot in dev mode, direct HDMI: HPD ready after 0 ms Cold/warm reboot in dev mode, no display: HPD not ready after 3000 ms. Abort. Change-Id: Id4657b5d5a95a68ecbd9efcf3585cf96ad1e13e1 Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78294 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com>
* mb/google/dedede: Create dexi variantKenneth Chan2023-10-0912-0/+509
| | | | | | | | | | | | | | | | Create the dexi variant of the taranza project by copying the files to a new directory named for the variant. BUG=b:303533815 BRANCH=dedede TEST=util/abuild/abuild -p none -t google/dedede -x -a make sure the build includes GOOGLE_DEXI Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com> Change-Id: I708a16cb864dca7309cb0201e7887af7456a4885 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78249 Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/dedede/var/boxy:Enable wake on USB2/3 (un)plugJoey Peng2023-10-041-0/+10
| | | | | | | | | | | | | | Set USB port which corresponds PORTSCN/PORTSCXUSB3 register bits for enable USB wake. BUG=b:302230434 TEST=Verify USB-A device could wake up Boxy Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Change-Id: I0f6300dc6bbb6fb8226151e49e38f0450b1e71b7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78144 Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/dedede/var/taranza: Enable wake on USB2/3 (un)plugSheng-Liang Pan2023-10-041-0/+14
| | | | | | | | | | | | | | | Set USB port which corresponds PORTSCN/PORTSCXUSB3 register bits for enable USB wake. The physical USB slot is 6, USB2 port5 for Bluetooth, total USB2 port num is 7, USB3 keep 6. BUG=b:300844110 TEST=Verify USB-A device could wake up Taranza Signed-off-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com> Change-Id: Ied92c4a70bc594bd189dcb942f1a445412509464 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78068 Reviewed-by: Ricky Chang <rickytlchang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
* mb/google/dedede: Move selects from Kconfig.name to KconfigFelix Singer2023-10-032-125/+183
| | | | | | | | | | | Selects should be done in the Kconfig file instead of Kconfig.name and not mixed over both files. Change-Id: I5527d5968be35f52b912d9d6e1d9f46f24569bbc Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78127 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
* treewide: convert to tpm_result_tJon Murphy2023-09-281-2/+2
| | | | | | | | | | | | | | | | Convert TPM functions to return TPM error codes(referred to as tpm_result_t) values to match the TCG standard. BUG=b:296439237 TEST=build and boot to Skyrim BRANCH=None Change-Id: Ifdf9ff6c2a1f9b938dbb04d245799391115eb6b1 Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77666 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* treewide: convert to %#x hex printsJon Murphy2023-09-281-1/+1
| | | | | | | | | | | | | | | Convert hex print values to use the %#x qualifier to print 0x{value}. BUG=b:296439237 TEST=build and boot to Skyrim BRANCH=None Change-Id: I0d1ac4b920530635fb758c5165a6a99c11b414c8 Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78183 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/dedede/var/taranza: Add power limits for JSL N4500 and N5100Sheng-Liang Pan2023-09-263-0/+49
| | | | | | | | | | | | | | | | Add PLx from JSL PDG (ID: 613095) in taranza devicetree. Add ramstage.c in Makefile.inc and update Taranza power limits in taranza ramstage.c. BUG=b:296004956 TEST=emerge-dedede coreboot and check psys and PLx value on taranza Signed-off-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com> Change-Id: Id43bb91bc9efb91cb074b075122cce4f22e0716c Reviewed-on: https://review.coreboot.org/c/coreboot/+/77857 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ricky Chang <rickytlchang@google.com> Reviewed-by: Reka Norman <rekanorman@chromium.org>
* mb/google/dedede: Fix SOF config for unprovisioned audio ampMatt DeVillier2023-09-221-8/+1
| | | | | | | | | | | | | | Dedede boards which select AUDIO_AMP_UNPROVISIONED via fw_config use rt1015 for the speaker topology, not max98360a. TEST=build/boot Win11 on google/magpie, verify correct audio profile selected. Change-Id: I5b75bd8fd37d2837de3c5bd25a02411a6982103b Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77741 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
* drivers/tpm: Make temp test value naming consistentJon Murphy2023-09-181-4/+4
| | | | | | | | | | | | | | | | Make naming convention consistent across all functions return values. BUG=b:296439237 TEST=Boot to OS on Skyrim BRANCH=None Change-Id: If86805b39048800276ab90b7687644ec2a0d4bee Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77536 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* mb/google/dedede/var/taranza: Update USB PLDsReka Norman2023-09-181-16/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update PLDs to match the port layout: Front (left to right): A4, A3, A2 Back (left to right): C0, A0, A1 BUG=b:264960828 TEST=USB2 and USB3 ports are peered correctly in the kernel: Before: $ cd /sys/devices/pci0000:00/0000:00:14.0 $ ls -l $(find . -name peer) ./usb1/1-0:1.0/usb1-port1/peer -> ../../../usb2/2-0:1.0/usb2-port1 ./usb1/1-0:1.0/usb1-port2/peer -> ../../../usb2/2-0:1.0/usb2-port2 ./usb1/1-0:1.0/usb1-port3/peer -> ../../../usb2/2-0:1.0/usb2-port3 ./usb1/1-0:1.0/usb1-port4/peer -> ../../../usb2/2-0:1.0/usb2-port4 ./usb1/1-0:1.0/usb1-port5/peer -> ../../../usb2/2-0:1.0/usb2-port5 ./usb1/1-0:1.0/usb1-port6/peer -> ../../../usb2/2-0:1.0/usb2-port6 ./usb2/2-0:1.0/usb2-port1/peer -> ../../../usb1/1-0:1.0/usb1-port1 ./usb2/2-0:1.0/usb2-port2/peer -> ../../../usb1/1-0:1.0/usb1-port2 ./usb2/2-0:1.0/usb2-port3/peer -> ../../../usb1/1-0:1.0/usb1-port3 ./usb2/2-0:1.0/usb2-port4/peer -> ../../../usb1/1-0:1.0/usb1-port4 ./usb2/2-0:1.0/usb2-port5/peer -> ../../../usb1/1-0:1.0/usb1-port5 ./usb2/2-0:1.0/usb2-port6/peer -> ../../../usb1/1-0:1.0/usb1-port6 After: $ cd /sys/devices/pci0000:00/0000:00:14.0 $ ls -l $(find . -name peer) ./usb1/1-0:1.0/usb1-port1/peer -> ../../../usb2/2-0:1.0/usb2-port1 ./usb1/1-0:1.0/usb1-port2/peer -> ../../../usb2/2-0:1.0/usb2-port3 ./usb1/1-0:1.0/usb1-port3/peer -> ../../../usb2/2-0:1.0/usb2-port4 ./usb1/1-0:1.0/usb1-port4/peer -> ../../../usb2/2-0:1.0/usb2-port6 ./usb1/1-0:1.0/usb1-port5/peer -> ../../../usb2/2-0:1.0/usb2-port5 ./usb1/1-0:1.0/usb1-port7/peer -> ../../../usb2/2-0:1.0/usb2-port2 ./usb2/2-0:1.0/usb2-port1/peer -> ../../../usb1/1-0:1.0/usb1-port1 ./usb2/2-0:1.0/usb2-port2/peer -> ../../../usb1/1-0:1.0/usb1-port7 ./usb2/2-0:1.0/usb2-port3/peer -> ../../../usb1/1-0:1.0/usb1-port2 ./usb2/2-0:1.0/usb2-port4/peer -> ../../../usb1/1-0:1.0/usb1-port3 ./usb2/2-0:1.0/usb2-port5/peer -> ../../../usb1/1-0:1.0/usb1-port5 ./usb2/2-0:1.0/usb2-port6/peer -> ../../../usb1/1-0:1.0/usb1-port4 Change-Id: I682a153d6b757e1b66373c622a6fcfbf389184e3 Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77877 Reviewed-by: Sam McNally <sammc@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/dedede/var/boxy: Update USB PLDsReka Norman2023-09-181-7/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update PLDs to match the port layout: Front (left to right): C0, A1, A0 Left side: C1 Also enable the usb 3.1 device. BUG=b:264960828 TEST=USB2 and USB3 ports are peered correctly in the kernel: Before: $ cd /sys/devices/pci0000:00/0000:00:14.0 $ ls -l $(find . -name peer) ./usb1/1-0:1.0/usb1-port1/peer -> ../../../usb2/2-0:1.0/usb2-port1 ./usb1/1-0:1.0/usb1-port3/peer -> ../../../usb2/2-0:1.0/usb2-port3 ./usb1/1-0:1.0/usb1-port4/peer -> ../../../usb2/2-0:1.0/usb2-port4 ./usb1/1-0:1.0/usb1-port5/peer -> ../../../usb2/2-0:1.0/usb2-port5 ./usb1/1-0:1.0/usb1-port6/peer -> ../../../usb2/2-0:1.0/usb2-port6 ./usb2/2-0:1.0/usb2-port1/peer -> ../../../usb1/1-0:1.0/usb1-port1 ./usb2/2-0:1.0/usb2-port3/peer -> ../../../usb1/1-0:1.0/usb1-port3 ./usb2/2-0:1.0/usb2-port4/peer -> ../../../usb1/1-0:1.0/usb1-port4 ./usb2/2-0:1.0/usb2-port5/peer -> ../../../usb1/1-0:1.0/usb1-port5 ./usb2/2-0:1.0/usb2-port6/peer -> ../../../usb1/1-0:1.0/usb1-port6 After: $ cd /sys/devices/pci0000:00/0000:00:14.0 $ ls -l $(find . -name peer) ./usb1/1-0:1.0/usb1-port1/peer -> ../../../usb2/2-0:1.0/usb2-port1 ./usb1/1-0:1.0/usb1-port2/peer -> ../../../usb2/2-0:1.0/usb2-port3 ./usb1/1-0:1.0/usb1-port3/peer -> ../../../usb2/2-0:1.0/usb2-port4 ./usb1/1-0:1.0/usb1-port4/peer -> ../../../usb2/2-0:1.0/usb2-port2 ./usb1/1-0:1.0/usb1-port5/peer -> ../../../usb2/2-0:1.0/usb2-port5 ./usb1/1-0:1.0/usb1-port6/peer -> ../../../usb2/2-0:1.0/usb2-port6 ./usb2/2-0:1.0/usb2-port1/peer -> ../../../usb1/1-0:1.0/usb1-port1 ./usb2/2-0:1.0/usb2-port2/peer -> ../../../usb1/1-0:1.0/usb1-port4 ./usb2/2-0:1.0/usb2-port3/peer -> ../../../usb1/1-0:1.0/usb1-port2 ./usb2/2-0:1.0/usb2-port4/peer -> ../../../usb1/1-0:1.0/usb1-port3 ./usb2/2-0:1.0/usb2-port5/peer -> ../../../usb1/1-0:1.0/usb1-port5 ./usb2/2-0:1.0/usb2-port6/peer -> ../../../usb1/1-0:1.0/usb1-port6 (Ports 5 and 6 are not used on boxy but are peered by default) Change-Id: I1563d9eaa27353c8c97225a0a6ecc238e9275ce2 Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77876 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com>
* mb/google/dedede/var/dibbi: Swap USB3 ports for A2 and A3Reka Norman2023-09-151-5/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | BUG=b:264960828 TEST=USB2 and USB3 ports are peered correctly in the kernel: Before: $ cd /sys/devices/pci0000:00/0000:00:14.0 $ ls -l $(find . -name peer) ./usb1/1-0:1.0/usb1-port1/peer -> ../../../usb2/2-0:1.0/usb2-port1 ./usb1/1-0:1.0/usb1-port2/peer -> ../../../usb2/2-0:1.0/usb2-port3 ./usb1/1-0:1.0/usb1-port3/peer -> ../../../usb2/2-0:1.0/usb2-port4 ./usb1/1-0:1.0/usb1-port4/peer -> ../../../usb2/2-0:1.0/usb2-port5 ./usb1/1-0:1.0/usb1-port5/peer -> ../../../usb2/2-0:1.0/usb2-port6 ./usb2/2-0:1.0/usb2-port1/peer -> ../../../usb1/1-0:1.0/usb1-port1 ./usb2/2-0:1.0/usb2-port3/peer -> ../../../usb1/1-0:1.0/usb1-port2 ./usb2/2-0:1.0/usb2-port4/peer -> ../../../usb1/1-0:1.0/usb1-port3 ./usb2/2-0:1.0/usb2-port5/peer -> ../../../usb1/1-0:1.0/usb1-port4 ./usb2/2-0:1.0/usb2-port6/peer -> ../../../usb1/1-0:1.0/usb1-port5 After: $ cd /sys/devices/pci0000:00/0000:00:14.0 $ ls -l $(find . -name peer) ./usb1/1-0:1.0/usb1-port1/peer -> ../../../usb2/2-0:1.0/usb2-port1 ./usb1/1-0:1.0/usb1-port2/peer -> ../../../usb2/2-0:1.0/usb2-port3 ./usb1/1-0:1.0/usb1-port3/peer -> ../../../usb2/2-0:1.0/usb2-port4 ./usb1/1-0:1.0/usb1-port4/peer -> ../../../usb2/2-0:1.0/usb2-port6 ./usb1/1-0:1.0/usb1-port5/peer -> ../../../usb2/2-0:1.0/usb2-port5 ./usb2/2-0:1.0/usb2-port1/peer -> ../../../usb1/1-0:1.0/usb1-port1 ./usb2/2-0:1.0/usb2-port3/peer -> ../../../usb1/1-0:1.0/usb1-port2 ./usb2/2-0:1.0/usb2-port4/peer -> ../../../usb1/1-0:1.0/usb1-port3 ./usb2/2-0:1.0/usb2-port5/peer -> ../../../usb1/1-0:1.0/usb1-port5 ./usb2/2-0:1.0/usb2-port6/peer -> ../../../usb1/1-0:1.0/usb1-port4 Change-Id: I5fe8066e361da62b747464b2ec09bcc6e7dda0fe Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77867 Reviewed-by: Sam McNally <sammc@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* mb/google/dedede: Update dibbi ec.h settingsReka Norman2023-09-141-35/+7
| | | | | | | | | | | | | | | | | | | | | | Update the dibbi ec.h so that it's correct for a chromebox. Remove everything related to: - Lid - Battery - Built-in keyboard - AC connect/disconnect - Mode changes BUG=b:294963793 TEST=Boot dibbi and check the APCI tables no longer contain lid and PS/2 keyboard devices. Change-Id: Idfa5adcec308d68555d292fddc1db43c9a64d649 Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77863 Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/dedede: Use a separate ec.h for dibbi variantsReka Norman2023-09-144-3/+87
| | | | | | | | | | | | | | | | | | | Dibbi variants are chromeboxes, so they need different settings in ec.h. Add a new dibbi baseboard ec.h and use it for dibbi variants. For now it's identical to the dedede baseboard ec.h. It will be updated in the following CL. BUG=b:294963793 TEST=With the following CL, boot dibbi and check the APCI tables no longer contain lid and PS/2 keyboard devices. Change-Id: I4075041ab8f02026623d1a26a555bee5eb09e77b Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77782 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Sam McNally <sammc@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com>
* mb/google/dedede/var/pirika: Add FW_CONFIG probe for EXT_VRDaniel_Peng2023-08-312-0/+18
| | | | | | | | | | | | | | | Add FW_CONFIG probe for absent FIVR bypass mode on peezer. BUG=b:296982082 BRANCH=firmware-dedede-13606.B TEST=emerge-dedede coreboot chromeos-bootimage Change-Id: I0b2053b2d732fd9462686ed7b0c9225539b28fb2 Signed-off-by: Daniel_Peng <Daniel_Peng@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77396 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/dedede/var/taranza: Add Wifi SAR for taranzaSheng-Liang Pan2023-08-263-0/+11
| | | | | | | | | | | | | | | | | BUG=b:297276380 BRANCH=dedede TEST=enable CHROMEOS_WIFI_SAR in config of coreboot, emerge-dedede coreboot-private-files-baseboard-dedede coreboot chromeos-bootimage Cq-Depend: chrome-internal:6373154 Signed-off-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com> Change-Id: If21c7a7d329b0b1cc2c73dadb0c5b8a5b8ab27e2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77399 Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
* mb/google/dedede/var/boxy: Enable 100M mode blink in RTL8111H LAN LED configStanley Wu2023-08-241-1/+1
| | | | | | | | | | | | | | | | Enable bit 9 for 100M mode green LED blink. Reference: - RTL8111H-CG Datasheet 1.92 section 7.2 for customizable led configuration BUG=b:293983804 TEST=emerge-dedede coreboot and verify LAN LED behavior Change-Id: Ice5686affcc014a2dfd35b7f579c8eaa38c2d3fe Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77393 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com>
* mb/google/dedede/var/pirika: Add USB2 PHY parameters for Type-A/Type-CDaniel_Peng2023-08-231-1/+11
| | | | | | | | | | | | | | | | | This change are added fine-tuned USB2 PHY parameters to improve the USB2 eye diagram result. BUG=b:296493887 BRANCH=firmware-dedede-13606.B TEST=Local build bios successfully. And verified the USB2 eye diagram test result. Change-Id: I915fe689883267901e8faba28632345d8c227c28 Signed-off-by: Daniel_Peng <Daniel_Peng@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77359 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/dedede: Add ACPI display brightness supportMatt DeVillier2023-08-182-1/+4
| | | | | | | | | | | | | | Add support for ACPI display brightness controls, so that panel adjustment is available under Windows. TEST=build/boot Win11 on google/magpie, verify panel brightness controls available and functional. Change-Id: I66daa6bbca15046994dff83bee6e7cf99aae0b33 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77271 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/dedede/var/boxy: update DPTF thermal settingsStanley Wu2023-08-151-7/+7
| | | | | | | | | | | | | | | | | Update DPTF thermal settings from thermal team suggestion: 1. Modify CPU passive policy to 95. 2. Modify TS0/TS1/TS2 passive policy to 90 for CPU. 3. Modify TS1 passtve policy watt to 6w. 4. Modify TS0/TS1/TS2 critical policy to 100. BUG=b:294479707 TEST=Build and verify DPTF value by thermal team on Boxy system Change-Id: Ic34e44f218ff980c54bf93841880fab5e21b3fca Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77108 Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/dedede/var/boxy: Generate new SPD ID for CXDB4ABAM-MLStanley Wu2023-08-093-0/+3
| | | | | | | | | | | | | | | | | | Generate RAM ID for CXMT CXDB4ABAM-ML DRAM Part Name ID to assign CXDB4ABAM-ML 1 (0001) BUG=b:290154780 BRANCH=dedede TEST=FW_NAME=boxy emerge-dedede coreboot chromeos-bootimage Change-Id: Ide44acf6bb8e5d5023c76d9e5e48ef113f7c6ec6 Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76825 Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
* mb/google/dedede/var/boxy: Update power limitsStanley Wu2023-08-072-0/+36
| | | | | | | | | | | | | | Add ramstage.c in Makefile.inc and update boxy power limits in Boxy ramstage.c. BUG=b:290293153 TEST=emerge-dedede coreboot and check psys and PLx value on boxy Change-Id: I4257dab358f066ebd13b6f251e8a5258a72fbd39 Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76877 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mainboard: Add SPDX license headers to MakefilesMartin Roth2023-08-062-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | To help identify the licenses of the various files contained in the coreboot source, we've added SPDX headers to the top of all of the .c and .h files. This extends that practice to Makefiles. Any file in the coreboot project without a specific license is bound to the license of the overall coreboot project, GPL Version 2. This patch adds the GPL V2 license identifier to the top of all makefiles in the mainboard directory that don't already have an SPDX license line at the top. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ic451e68b1ad9ccdf34484dd98bd7fca7e177ef22 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68982 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Tim Crawford <tcrawford@system76.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
* mb/google/dedede: Enable wake from S0ix on EC_HOST_EVENT_HANG_DETECTReka Norman2023-08-051-1/+2
| | | | | | | | | | | | | | | | BUG=b:279097356 TEST=On dibbi: - flash OS 15449.0.0 (where suspend is broken due to b:274531972) - run `suspend_stress_test --count=1 --suspend_max=30 --suspend_min=28` - check the AP wakes up immediately when the EC detects a sleep hang Change-Id: I24a2aa5de1f76e6dd1c1ce726b648583756e5e55 Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76938 Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* mb/google/dedede/var/boxy: Add power limits for N4500/N5100Stanley Wu2023-08-051-0/+13
| | | | | | | | | | | | | | | | | Add PLx from JSL PDG(ID: 613095) in boxy devicetree. BUG=b:290293153 TEST=emerge-dedede coreboot and read correct value on boxy CPU log: CPU TDP = 6 Watts, CPU PL4 = 60 Watts Change-Id: I7b063dc235fb714ba47eb620b914f2f9e92a2715 Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76876 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* mb/google/dedede/var/pirika: Support for Samsung K4U6E3S4AB-MGCLDaniel_Peng2023-08-043-3/+5
| | | | | | | | | | | | | | | | | | | | | Add the new memory support: Samsung K4U6E3S4AB-MGCL BUG=b:294151054 BRANCH=firmware-dedede-13606.B TEST=Run command "go run ./util/spd_tools/lp4x/gen_part_id.go JSL lp4x \ src/mainboard/google/dedede/variants/pirika/memory/ \ src/mainboard/google/dedede/variants/pirika/memory/\ mem_parts_used.txt" Change-Id: Ief9bbf11fc05c8155f1da7188926a29dbbfbe488 Signed-off-by: Daniel_Peng <Daniel_Peng@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76542 Reviewed-by: Daniel Peng <daniel_peng@pegatron.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-10-03 13:10:25 +0000