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* mb/getac to mb/intel: Add SPDX license headers to Kconfig filesMartin Roth2024-02-181-0/+2
| | | | | | | | | Change-Id: Id859c981d0bf5dcf90bf6858607a9fe726516309 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80592 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
* device/device.h: Rename busses for clarityArthur Heymans2024-01-312-2/+2
| | | | | | | | | | This renames bus to upstream and link_list to downstream. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I80a81b6b8606e450ff180add9439481ec28c2420 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78330 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* soc/amd: use common ACPI_SCI_IRQ definitionFelix Held2024-01-271-0/+1
| | | | | | | | | | | | ACPI_SCI_IRQ is defined as 9 for all AMD SoCs, so move the definition to the common amdblocks/acpi.h. Since all but Stoneyridge's soc/acpi.h are now empty, delete those files too. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8210c98dc4cf2c6001d5273d132053278ff7fea5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80222 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/gale to nyan_blaze: Rename Makefiles from .inc to .mkMartin Roth2024-01-2412-0/+0
| | | | | | | | | | | | | | | | The .inc suffix is confusing to various tools as it's not specific to Makefiles. This means that editors don't recognize the files, and don't open them with highlighting and any other specific editor functionality. This issue is also seen in the release notes generation script where Makefiles get renamed before running cloc. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I92f8bd7e1c9fc6e4120fb94c2299a266304e19de Reviewed-on: https://review.coreboot.org/c/coreboot/+/80107 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google: Reduce DA7219 mic detect threshold to 200ohmTerry Cheong2023-12-151-1/+1
| | | | | | | | | | | | | | | | | The original DA7219 is designed to use a 500ohm mic detection threshold. Some headset mics (e.g. Logitech H111) have a lower DC impedance that is lower than the threshold and thus cannot be detected. Lower the threshold to 200ohm to match the new default value provided by Renasas as in https://patchwork.kernel.org/project/alsa-devel/patch/20231201042933.26392-1-David.Rau.opensource@dm.renesas.com/ to support such headsets. BUG=b:314062160,b:308207450 Change-Id: I6415e84a4622e0c61bc74b94536fe734048a043f Signed-off-by: Terry Cheong <htcheong@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79436 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
* mb/google/kahlee: Alphabetize Kconfig selectionsMatt DeVillier2023-10-251-17/+17
| | | | | | | | | | Change-Id: I72ef272e48db7683a3170e157edd0a782143e8aa Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78431 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Eric Lai <ericllai@google.com>
* mb/google/kahlee: Select SOC_AMD_COMMON_BLOCK_GRAPHICS_ACPCoolStar2023-10-251-0/+1
| | | | | | | | | | | | | Select ACP audio for kahlee since it's located on the GPU. TEST: build/boot careena to Win10. Observe audio device shows up Change-Id: I51527a1bfae3e12ce5cf1da8a3465bbc9ddfa76e Signed-off-by: CoolStar <coolstarorganization@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78406 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* devicetrees: Remove trailing backslash from multiline valuesFelix Singer2023-10-251-1/+1
| | | | | | | | | | | | It's not needed to put a backslash at the end of a line for quoted multiline values. Thus, remove it. Change-Id: I1b83d53598ba2adeed853a96d6c2c1a21f01a9f7 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78576 Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* mb/google/kahlee: Enable display backlight control in WindowsCoolStar2023-10-241-0/+1
| | | | | | | | | | | | | | | | | Utilize the SOC_AMD_COMMON_BLOCK_GRAPHICS_ATIF to provide the Windows driver with information on backlight settings. TEST: Boot google/careena to Win10. Observe display brightness controls functional after driver loads (immediately with patched driver, 30 minutes with unpatched). Change-Id: I6792a91f26a5f6e4dc478cdde776ff749f08946f Signed-off-by: CoolStar <coolstarorganization@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78429 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
* mb/google/kahlee: Hide Linux machine audio devices from WindowsCoolStar2023-10-202-0/+8
| | | | | | | | | | | Windows does not use these devices for audio. Hide these so they don't clutter device manager. Change-Id: Ic85eff7f7ff68e25cc005bbb822bf99374c96532 Signed-off-by: CoolStar <coolstarorganization@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78418 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/kahlee: Move selects from Kconfig.name to KconfigFelix Singer2023-09-212-6/+18
| | | | | | | | | | | Selects should be done in the Kconfig file instead of Kconfig.name and not mixed over both files. Change-Id: Id060f781b87567da2756c89275002b9ea4f4976c Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75015 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* util/amdfwtool: Deal with psp position in flash offset directlyZheng Bao2023-09-011-4/+1
| | | | | | | | | | | | | | | | | | | It is based on work by Arthur Heymans, 69852. Get rid of the confusing "position index" and use the relative flash offset as the Kconfig setting instead. TEST=binary identical on amd/birman amd/majolica amd/gardenia amd/mayan amd/bilby amd/mandolin amd/chausie amd/pademelon pcengines/apu2 google/skyrim google/guybrush google/zork google/kahlee google/myst (The test should be done with INCLUDE_CONFIG_FILE=n) Change-Id: I26bde0b7c70efe9f5762109f431329ea7f95b7f2 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72939 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* mb/google/kahlee: enable uart0 for console in devicetreeMatt DeVillier2023-08-091-0/+3
| | | | | | | | | | | | | Kahlee selects AMD_SOC_CONSOLE_UART causing UART0 to be used as console, so enable uart_0 in the devicetree to make sure that the UART will be marked as enabled in the SSDT that will be generated with the next patch applied. This also matches the other AMD SoC based Chromebooks. Change-Id: Ibe18f87d8bf63603fb2eb87728395e45e9a9ef69 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77094 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google: AMD: move tpm_tis to AMD common codeGrzegorz Bernacki2023-07-143-14/+4
| | | | | | | | | | | | | | | | | | It moves cr50_plat_irq_status() to common code and adds Kconfig option to specify GPIO used for interrupt. BUG=b:277787305 TEST=Build all affected platform and confirm using right GPIO number. Tested on Skyrim. Change-Id: I775c4e24cffee99b6ac3e05b58a75425029a86c8 Signed-off-by: Grzegorz Bernacki <bernacki@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75621 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Martin L Roth <gaumless@gmail.com>
* drivers/tpm: Move tis_plat_irq_status to cr50 driverGrzegorz Bernacki2023-07-061-2/+2
| | | | | | | | | | | | | | | | | tis_plat_irq_status() function is used only by Google TPM. It should be moved to drivers/tpm/cr50.c. The name of the function was changed to cr50_plat_irq_status(). BUG=b:277787305 TEST=Build all affected platforms Change-Id: I78dc39f2c7b44232b06947d3dfe6afa52807ced8 Signed-off-by: Grzegorz Bernacki <bernacki@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75917 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* mb/google/kahlee: Add EC_HOST_EVENT_PANIC to SCI maskRob Barnes2023-07-031-1/+2
| | | | | | | | | | | | | | | | | | | | Adding EC_HOST_EVENT_PANIC to SCI mask allows the EC to interrupt the Kernel when an EC panic occurs. If system safe mode is also enabled on the EC, the kernel will have a short period to extract and save info about the EC panic. BUG=b:283245785 BRANCH=firmware-grunt-11031.B TEST=Observe kernel ec panic handler run when ec panics Change-Id: I8eeb5c0935d0531c21bcf4cd3d4fd9dc80b54f79 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75323 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward Hill <ecgh@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* mb/google/kahlee: Enable Secure OSJon Murphy2023-07-031-2/+4
| | | | | | | | | | | | | | | | | | Secure OS was disabled on Grunt devices since it isn't used. This reduces the attack surface and is meant to mitigate potential security risks. However, this prevents users from using an alternate OS. Enable Secure OS upstream to allows users to use Windows, and ensure that it is still disabled in the chromium repo. BUG=b:287630343 TEST=Builds with Secure OS included. Cq-Depend: chromium:4620881 Change-Id: I213aebc41cae300ecee8c01fc5c7687f7e7f5ee3 Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75874 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* mb/google/kahlee/mainboard: use ACPI_SCI_IRQ definitionFelix Held2023-02-281-1/+2
| | | | | | | | | | Use the ACPI_SCI_IRQ definition instead of a magic value. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia860668b5c93b1b8882459d9f983cf3a23d16392 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73321 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/stoneyridge: remove LIDS field from global NVSFelix Held2023-02-061-0/+2
| | | | | | | | | | | | | | | | | Since the LIDS field is only used in the ACPI code and not in the C code of any mainboard using the Stoneyridge SoC, remove it form the global NVS and add an ACPI object for this in the DSDT of the mainboards that use it in their ACPI code. Eventually the LIDS object should probably be moved to the EC's ACPI code, but that's out of scope for this patch. TEST=google/liara doesn't show ACPI errors in Linux' dmesg Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I778c4189607035b4765c6cb8b2e74030dcf9069f Reviewed-on: https://review.coreboot.org/c/coreboot/+/72182 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
* drivers/i2c/generic: Drop 'disable_gpio_export_in_crs' flagMatt DeVillier2023-01-156-11/+0
| | | | | | | | | | | | | | | | | | | | | | | Exposing the GPIOs via an ACPI PowerResource and the _CRS results in the OS driver and ACPI thinking they own the GPIO. This can cause timing problems because it's not clear which system should be controlling the GPIO. Previously, we flagged as an error any device which set the 'has_power_resource' flag but did not set 'disable_gpio_export_in_crs.' There's no reason to require explicit disablement however, so drop the superfluous 'disable' flag, and change the _CRS generation to check if the GPIOs will be exported via the 'has_power_resource' flag instead. BUG=b:265055477 TEST=build/boot skyrim, dump SSDT and verify touchscreen GPIOs only listed under PRx, not under _CRS. Change-Id: I837ae6c6fe4b8e1c4e10686406cba06bdb7759d2 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71849 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
* mainboard/acpi: Replace constant "Zero" with actual numberFelix Singer2022-12-271-1/+1
| | | | | | | | | Change-Id: I4f2f02623b060ef0ebefc5aceb713c77a8b1e9a6 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71523 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* mb/google/kahlee: update ACPI HID/CID for Synaptics touchpadsMatt DeVillier2022-12-224-4/+8
| | | | | | | | | | | | | | | | The currently assigned ACPI HID 'PNP0C50' is not a valid per Windows WHQL validation tests. To ensure compatibility with both Windows and Linux, set the HID to 'SYNA0000' and CID to 'ACPI0C50' as previously done for other boards (eg, google/lulu). TEST=boot Linux 5.1x, Windows 10 on liara, verify all touchpad functions work correctly. Change-Id: I89ca02629803882e7ed2048a5a26868fc2de41a9 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71073 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* mb/google/kahlee/acpi: Replace Store(a,b) with ASL 2.0 syntaxFelix Singer2022-12-142-7/+7
| | | | | | | | | | | Replace `Store (a, b)` with `b = a`. Change-Id: Ib2ba6b5c14f6699dc6c0734724a6784e3400a467 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70643 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* mb/google/kahlee: use gpio.h includeFelix Held2022-12-086-7/+6
| | | | | | | | | | | | | | Replace the amdblocks/gpio.h, amdblocks/gpio_defs.h and soc/gpio.h includes with the common gpio.h which will include soc/gpio.h which will include amdblocks/gpio.h which will include amdblocks/gpio_defs.h in the AMD SoC case. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I13bc33b91f6e6d52867da9043bb386f3befac5fb Reviewed-on: https://review.coreboot.org/c/coreboot/+/70433 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
* ec/google/chromeec: Remove EC_HOST_EVENT_USB_CHARGERCaveh Jalali2022-11-191-1/+0
| | | | | | | | | | | | | | | | | EC_HOST_EVENT_USB_CHARGER is no longer defined by the EC, so remove all references. BUG=b:216485035,b:258126464 BRANCH=none TEST=none Change-Id: I9e3e0e9b45385766343489ae2d8fc43fb0954923 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69374 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Jon Murphy <jpmurphy@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* mb/google/kahlee: Implement touchscreen power sequencingMatt DeVillier2022-11-161-0/+5
| | | | | | | | | | | | | | | | | | As all variants have a touchscreen option, in baseboard table set the enable GPIO high and hold in reset during romstage, then release reset in ramstage. This will allow the touchscreen to make use of the runtime I2C detect feature (enabled in a subsequent commit) so that an ACPI device entry is created only for the touchscreen actually present. This mirrors similar changes made for skyrim, guybrush, and zork. TEST=tested with rest of patch train Change-Id: Id235815904dfc093549a1ed529e19974010977c7 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69547 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/kahlee: Use detect vs probed flag for touchscreensMatt DeVillier2022-11-166-11/+11
| | | | | | | | | | | | | | | | | | | | | Now that coreboot performs the necessary power sequencing, switch from using the 'probed' flag to 'detect' for all I2C touchscreens. This alleviates ChromeOS from having to probe to see which touchscreen model is actually present, prevents breaking ACPI spec by generating device entries with status 'enabled and present' which aren't actually present, and improves compatibility with upstream Linux and Windows. BUG=b:121309055 TEST=build/boot ChromeOS and Linux on barla/liara, ensure touchscreen is functional, and ACPI device entry generated for correct touchscreen model. Change-Id: I142a6cdb6e8cef51fd925d34362a19a8736982a5 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69548 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/kahlee: rename baseboard GPIO table getter for clarityMatt DeVillier2022-11-163-4/+4
| | | | | | | | | | | | | | | | Rename variant_romstage_gpio_table() to baseboard_romstage_gpio_table() since the GPIO table comes from the baseboard (and is not overridden by any variant). Drop the __weak qualifier as this function is not overridden. This mirrors similar changes made for skyrim, guybrush, and zork. Change-Id: I772bd2d74fd6778ffaa1e0809cc53f8d43b153f3 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69546 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/kahlee: Disable touchscreen GPIO export in CRSMatt DeVillier2022-11-166-0/+7
| | | | | | | | | | | | | | | Disable GPIO export in ACPI _CRS for touchscreens which set the register "have_power_resource." This eliminates the error: [ERROR] I2C: <bus:addr>: Exposing GPIOs in Power Resource and _CRS TEST=build/boot barla/liara, verify touchscreen functional, no error in cbmem log. Change-Id: Ifa8248755f346df37faf7a3182651bf190b0c33d Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69549 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd: commonize generation of the PIC/APIC mapping tablesFelix Held2022-11-151-38/+3
| | | | | | | | | | | | | | | | Now that we have a common init_tables in all mainboards using AMD SoCs, both the population of the fch_pic_routing and fch_apic_routing arrays and the definition of those arrays can be moved to the common AMD SoC code to not have the code duplicated in all mainboards. BUG=b:182782749 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Suggested-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Change-Id: I8c65eca258272f0ef7dec3ece6236f5d00954c66 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68853 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/kahlee/mainboard: rewrite IRQ mapping handlingFelix Held2022-11-151-42/+65
| | | | | | | | | | | | | | | | | | | | | | | | | | Rewrite the Kahlee IRQ mapping handling to be in line with the newer AMD SoCs to allow making the largest part of the corresponding code common for all AMD SoCs in the coreboot tree. The PIC-mode IRQ numbers for both PIRQ_ASF and PIRQ_SDIO were 0 in the data tables which is the PIT IRQ which looks very wrong to me, so it was changed to PIRQ_NC. Since the ASF and likely also the SDIO controller are unused, this shouldn't change runtime behavior. The data tables also had non 0 and non 0x1f entries in the following locations the internal BKDG #55072 revision 3.04 describes as unused: 0x31, 0x33, 0x35-0x37, 0x40, 0x50-0x53. The entry at 0x32 is also non 0 and non 0x1f and the description in the BKDG says that it controls the IRQ mapping of another internal PCI device, but that PCI device doesn't exist in the SoC. TEST=No obvious IRQ-related breakage on google/liara Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Change-Id: I9b3bfca33d88ef3989b63f4fe6c301e0e485b7e9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68851 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/common/include: introduce and use FCH_IRQ_ROUTING_ENTRIESFelix Held2022-10-261-2/+2
| | | | | | | | | | | | | | | | Instead of using magic constants for the fch_pic_routing and fch_apic_routing array sizes, define FCH_IRQ_ROUTING_ENTRIES in the common code headers and use this definition. This also allows to drop the static assert for the array sizes. In the Stoneyridge mainboard code the equivalent arrays are named mainboard_picr_data and mainboard_intr_data; also use FCH_IRQ_ROUTING_ENTRIES as fixed array size there. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I2d7ee46bd013ce413189398a144e46ceac0c2a10 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68818 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/kahlee/liara/devicetree: move Raydium touchscreen to baseboardFelix Held2022-10-252-14/+12
| | | | | | | | | | | | | | | | | | Move the Raydium touchscreen to the baseboard devicetree. Since only the liara variant uses a level IRQ as I2C devices are supposed to, all other board variants still override this to use an edge IRQ which were added as a workaround to make the touchscreen work on the other devices. Right now it's unclear to me if that edge IRQ workaround was only needed temporarily and can now be removed, so I'll keep it as it was for now. If this turns out to be no longer needed on the other variants, the overrides can be dropped in the future. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic621c1a5856e9e280a25b0668010a1ee5bbb61e4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68770 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
* mb/google/kahlee: always detect ELAN touchpadFelix Held2022-10-245-32/+1
| | | | | | | | | | | | Always detecting the presence of the ELAN touchpad doesn't affect the functionality, but allows dropping the override for all variants that have multiple touchpad options. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id5d14eedd5d95dd0990ae56775daed9284c03717 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68672 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
* mb/google/kahlee: use override devicetrees for variantsFelix Held2022-10-2410-576/+204
| | | | | | | | | | | This helps with deduplicating the identical parts of the variants' devicetrees. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie050c4624327b904e8cb0959b40421339e43f825 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68634 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
* mb/google/kahlee: Fix audio ACPI inclusionMatt DeVillier2022-10-228-32/+38
| | | | | | | | | | | | | | | Not all kahlee variants use the RT5682 audio codec, so split the baseboard audio ACPI into two parts and only include the asl for the codec(s) actually needed for a given variant. TEST=build/boot aleena, liara variants and verify no ACPI present for RT5682 codec (which is not present on the boards). Change-Id: Icb7df4f8e51495ad3cb40113cd00810fd27dcd00 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68583 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* mb/google/kahlee/*/devicetree: disable unused PCIe root portsFelix Held2022-10-146-24/+6
| | | | | | | | | | | | | | | | | | Disable the unused PCIe root ports that are disabled in the PCIe port corresponding descriptor list passed to AGESA/binaryPI. This descriptor list is in src/mainboard/google/kahlee/variants/baseboard/OemCustomize.c and it only has B0D2F2 (gpp_bridge_1) and B0D2F4 (gpp_bridge_3) enabled. Since the PCIe engines marked as unused in the port descriptor list won't show up as PCI devices, don't enable those PCI devices in the devicetree so that coreboot won't complain about static PCI devices not being found on the PCI bus. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: If8378e343a2eb13de66171cf4f38d77ae3401016 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68382 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
* mb/google/kahlee/*/devicetree: use device aliasesFelix Held2022-10-146-192/+120
| | | | | | | | Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I63b1053d36b284ed95b015c0b4b26bdf8e162e67 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68381 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/amd,google/*/devicetree: drop CPU cluster device for StoneyridgeFelix Held2022-10-136-18/+0
| | | | | | | | | | | | | | | Since commit 60e9114c6210 ("include/device: ensure valid link/bus is passed to mp_cpu_bus_init"), no dummy LAPIC device is required under the CPU cluster device. Since the CPU cluster device is already present in the Stoneyridge chipset devicetree, drop the whole CPU cluster part from the mainboard's devicetrees. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8918c14be25ac9756926a9c6a2806a3dceced42a Reviewed-on: https://review.coreboot.org/c/coreboot/+/68317 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/kahlee: drop unused and incorrect irq_tables.cFelix Held2022-09-141-86/+0
| | | | | | | | | | | | This file is neither included in the build nor correct, since the Stoneyridge SoC doesn't have a legacy PCI bridge on bus 0 bridge 0x14 function 4. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I0daed891984faed9fbc36f0215edfc56e0ae14a7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67633 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
* mb/google/kahlee/irq_tables.c: Use ALIGN_UP macroElyes Haouas2022-09-121-2/+2
| | | | | | | | Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I4ccdd370d3e9aef938fae4c4690ec0bf4c53c500 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67517 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* mb/*/{device,override}tree: Set touchpads to use detect (vs probed) flagMatt DeVillier2022-09-094-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | Historically, ChromeOS devices have worked around the problem of OEMs using several different parts for touchpads/touchscreens by using a ChromeOS kernel-specific 'probed' flag (rejected by the upstream kernel) to indicate that the device may or may not be present, and that the driver should probe to confirm device presence. Since c636142b, coreboot now supports detection for i2c devices at runtime when creating the device entries for the ACPI/SSDT tables, rendering the 'probed' flag obsolete for touchpads. Switch all touchpads in the tree from using the 'probed' flag to the 'detect' flag. Touchscreens require more involved power sequencing, which will be done at some future time, after which they will switch over as well. TEST: build/boot at least one variant for each baseboard in the tree. Verify touchpad works under Linux and Windows. Verify only a single touchpad device is present in the ACPI tables. Change-Id: I47c6eed37eb34c044e27963532e544d3940a7c15 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67305 Reviewed-by: Sean Rhodes <sean@starlabs.systems> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/grunt: Enable AC wakeDaisuke Nojiri2022-09-081-1/+3
| | | | | | | | | | | | | | This patch enables AC plug/unplug for resume. BUG=b:188457962 BRANCH=grunt TEST=Verified AC plug/unplug wakes up Treeya. Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Change-Id: I10480f8224b909fefe42d46d7c03fc9d3fe5abfe Reviewed-on: https://review.coreboot.org/c/coreboot/+/67389 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/**/dsdt.asl: Drop superfluous commentsAngel Pons2022-08-161-2/+0
| | | | | | | | | | | | | | These comments don't add much value, so remove them. Change-Id: I7e9692e3fe82345cb7ddcb11c32841c69768cd36 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66713 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
* src/mb: Add SPDX identifiers to files missing themMartin Roth2022-08-111-0/+2
| | | | | | | | | | | | | This adds SPDX identifiers to the remaining source files in the mainboard directory that don't already have them. Change-Id: I1adc204624f3ab6fcafd8fbb239e6d69e057973a Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66498 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
* mb/google/kahlee: Increase VRAM from 16 to 32 MiBMatt DeVillier (AMD)2022-07-226-6/+6
| | | | | | | | | | | | | | | | | | | | | | While adequate for ChromeOS, 16MiB VRAM is insufficient for current mainline Linux and Windows amdgpu drivers to operate properly. Under Linux, the driver fails to allocate a framebuffer and causes multiple kernel panics. Under Windows, the driver fails to load due to insufficient resources available. Revert the VRAM allocation to the previous amount of 32MiB. This change reverts commit 87dcd0061af4 ("mainboard/google/kahlee: Reduce VRAM to 16MB") Test: build/boot Linux 5.17.x on google/liara, verify framebuffer allocation succeeds and no kernel panic reported. Change-Id: I1967a203fed80456a20af00943eba21bc1c0577b Signed-off-by: Matt DeVillier (AMD) <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66022 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* treewide: Unify Google brandingJon Murphy2022-07-041-1/+1
| | | | | | | | | | | | | | | | | Branding changes to unify and update Chrome OS to ChromeOS (removing the space). This CL also includes changing Chromium OS to ChromiumOS as well. BUG=None TEST=N/A Change-Id: I39af9f1069b62747dbfeebdd62d85fabfa655dcd Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65479 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* mb/google/kahlee: Replace Multiply(a,b,c) with ASL 2.0 syntaxFelix Singer2022-06-091-1/+1
| | | | | | | | | | Replace `Multiply (a, b, c)` with `c = a * b`. Change-Id: I19835510b89cd243277f0c9701209c81bdf6ea29 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60651 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
* mb/google/kahlee/acpi: Replace LGreaterEqual(a,b) with ASL 2.0 syntaxFelix Singer2022-06-091-1/+1
| | | | | | | | | | Replace `LGreaterEqual(a, b)` with `a >= b`. Change-Id: Id7975a8cad4078a523de2466919982ad540f5dd3 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60693 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
* tpm: Refactor TPM Kconfig dimensionsJes B. Klinke2022-04-211-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Break TPM related Kconfig into the following dimensions: TPM transport support: config CRB_TPM config I2C_TPM config SPI_TPM config MEMORY_MAPPED_TPM (new) TPM brand, not defining any of these is valid, and result in "generic" support: config TPM_ATMEL (new) config TPM_GOOGLE (new) config TPM_GOOGLE_CR50 (new, implies TPM_GOOGLE) config TPM_GOOGLE_TI50 (new to be used later, implies TPM_GOOGLE) What protocol the TPM chip supports: config MAINBOARD_HAS_TPM1 config MAINBOARD_HAS_TPM2 What the user chooses to compile (restricted by the above): config NO_TPM config TPM1 config TPM2 The following Kconfigs will be replaced as indicated: config TPM_CR50 -> TPM_GOOGLE config MAINBOARD_HAS_CRB_TPM -> CRB_TPM config MAINBOARD_HAS_I2C_TPM_ATMEL -> I2C_TPM && TPM_ATMEL config MAINBOARD_HAS_I2C_TPM_CR50 -> I2C_TPM && TPM_GOOGLE config MAINBOARD_HAS_I2C_TPM_GENERIC -> I2C_TPM && !TPM_GOOGLE && !TPM_ATMEL config MAINBOARD_HAS_LPC_TPM -> MEMORY_MAPPED_TPM config MAINBOARD_HAS_SPI_TPM -> SPI_TPM && !TPM_GOOGLE && !TPM_ATMEL config MAINBOARD_HAS_SPI_TPM_CR50 -> SPI_TPM && TPM_GOOGLE Signed-off-by: Jes B. Klinke <jbk@chromium.org> Change-Id: I4656b2b90363b8dfd008dc281ad591862fe2cc9e Reviewed-on: https://review.coreboot.org/c/coreboot/+/63424 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-27 00:01:51 +0000