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* google/*: Clean up Kconfg board selection for Google MTK boardsJulius Werner2023-11-221-64/+21
| | | | | | | | | | | | | This patch tries to standardize and simplify the Kconfig option layout for Google boards with MediaTek SoCs and align them to the scheme used with other Arm-based Google boards. Change-Id: I40880e7609ba703d0053ad01da742871e54d4e7a Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79063 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com>
* mb/google/kukui: Move selects from Kconfig.name to KconfigFelix Singer2023-09-212-20/+60
| | | | | | | | | | | Selects should be done in the Kconfig file instead of Kconfig.name and not mixed over both files. Change-Id: I866333a234203dc2da3d4dd8c4f87e4cfa332787 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75027 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
* mainboard: Add SPDX license headers to MakefilesMartin Roth2023-08-062-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | To help identify the licenses of the various files contained in the coreboot source, we've added SPDX headers to the top of all of the .c and .h files. This extends that practice to Makefiles. Any file in the coreboot project without a specific license is bound to the license of the overall coreboot project, GPL Version 2. This patch adds the GPL V2 license identifier to the top of all makefiles in the mainboard directory that don't already have an SPDX license line at the top. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ic451e68b1ad9ccdf34484dd98bd7fca7e177ef22 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68982 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Tim Crawford <tcrawford@system76.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
* drivers/tpm: Move tis_plat_irq_status to cr50 driverGrzegorz Bernacki2023-07-061-2/+2
| | | | | | | | | | | | | | | | | tis_plat_irq_status() function is used only by Google TPM. It should be moved to drivers/tpm/cr50.c. The name of the function was changed to cr50_plat_irq_status(). BUG=b:277787305 TEST=Build all affected platforms Change-Id: I78dc39f2c7b44232b06947d3dfe6afa52807ced8 Signed-off-by: Grzegorz Bernacki <bernacki@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75917 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* mb/google/kukui: Change Juniper/Willow RAM table offset to 0x30Sheng-Liang Pan2023-06-061-1/+1
| | | | | | | | | | | | | | | | All the DRAM module for Juniper/Willow can reuse the RAM ID in offset 0x30 table, so change Juniper/Willow RAM table offset to 0x30 for introducing more DRAM modules. BUG=b:284423187 BRANCH=kukui TEST=emerge-jacuzzi coreboot Signed-off-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com> Change-Id: I92740275dcc27061a94b7db7ce095655c0bd7cf5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75563 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com>
* Convert literal uses of CONFIG_MAINBOARD_{VENDOR,PART_NUMBER}Kyösti Mälkki2023-05-051-1/+2
| | | | | | | | | | | | Only expand these strings in lib/identity.o. Change-Id: I8732bbeff8cf8a757bf32fdb615b1d0f97584585 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74907 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* mb/google/kukui: Add sdram configs for RAM code 0x33 and 0x34Sheng-Liang Pan2023-04-191-0/+2
| | | | | | | | | | | | | | | | | | | Add sdram configs: - RAM code 0x33: sdram-lpddr4x-K4UBE3D4AA-MGCL-4GB SPD for K4UBE3D4AB-MGCL 4GB - RAM code 0x34: sdram-lpddr4x-H9HCNNNFAMMLXR-NEE-8GB for H54G68CYRBX248 8GB BUG=b:278644249 BRANCH=kukui TEST=emerge-jacuzzi coreboot Signed-off-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com> Change-Id: If5b484b5324ba39dbb220f12bdb8344ecb5c4da5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73469 Reviewed-by: Lucas Chen <lucas.chen@quanta.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mainboard: Remove duplicated <soc/gpio.h>Elyes Haouas2023-01-131-1/+0
| | | | | | | | | | <gpio.h> chain-include <soc/gpio.h>. Change-Id: Ia57d5cd33c70b6a755babd4db56c64c0e3666f9f Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71817 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* src: De-conflict CALIBRATION_REGION definitionsMartin Roth2022-09-081-6/+6
| | | | | | | | | | | | Change the name of the CALIBRATION_REGION definitions used in two separate locations. This conflict was causing an error for the lint-001-no-global-config-in-romstage test. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: If6734f2a7d9be669586ea350fb9979fcd422b591 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67382 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* soc/mediatek: a common implementation to register BL31 resetHung-Te Lin2022-09-071-15/+3
| | | | | | | | | | | | | | | The implementations of register_reset_to_bl31() are the same for MedaiTek platforms, so we extract them to soc/common/bl31.c. BUG=None TEST=build pass Change-Id: I297ea2e18a6d7e92236cf415844b166523616bdf Signed-off-by: Hung-Te Lin <hungte@chromium.org> Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67359 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* treewide: Unify Google brandingJon Murphy2022-07-041-1/+1
| | | | | | | | | | | | | | | | | Branding changes to unify and update Chrome OS to ChromeOS (removing the space). This CL also includes changing Chromium OS to ChromiumOS as well. BUG=None TEST=N/A Change-Id: I39af9f1069b62747dbfeebdd62d85fabfa655dcd Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65479 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* mb/google/kukui: Add LPDDR4X MT53E2G32D4NQ-046 WT:C supportKevin Chiu2022-05-252-2/+17
| | | | | | | | | | | | | | | | | Separate and add LPDDR4X MT53E2G32D4NQ-046 WT:C support for burnet/esche ID#1: MICRON - MT53E2G32D4NQ-046 WT:C BUG=b:225121354 BRANCH=none TEST=1. emerge-jacuzzi coreboot 2. power on test ok Change-Id: If720d7bcf185c5c0149a82125ec068fc75e5b3cd Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64069 Reviewed-by: Chen-Tsung Hsieh <chentsung@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* tpm: Refactor TPM Kconfig dimensionsJes B. Klinke2022-04-211-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Break TPM related Kconfig into the following dimensions: TPM transport support: config CRB_TPM config I2C_TPM config SPI_TPM config MEMORY_MAPPED_TPM (new) TPM brand, not defining any of these is valid, and result in "generic" support: config TPM_ATMEL (new) config TPM_GOOGLE (new) config TPM_GOOGLE_CR50 (new, implies TPM_GOOGLE) config TPM_GOOGLE_TI50 (new to be used later, implies TPM_GOOGLE) What protocol the TPM chip supports: config MAINBOARD_HAS_TPM1 config MAINBOARD_HAS_TPM2 What the user chooses to compile (restricted by the above): config NO_TPM config TPM1 config TPM2 The following Kconfigs will be replaced as indicated: config TPM_CR50 -> TPM_GOOGLE config MAINBOARD_HAS_CRB_TPM -> CRB_TPM config MAINBOARD_HAS_I2C_TPM_ATMEL -> I2C_TPM && TPM_ATMEL config MAINBOARD_HAS_I2C_TPM_CR50 -> I2C_TPM && TPM_GOOGLE config MAINBOARD_HAS_I2C_TPM_GENERIC -> I2C_TPM && !TPM_GOOGLE && !TPM_ATMEL config MAINBOARD_HAS_LPC_TPM -> MEMORY_MAPPED_TPM config MAINBOARD_HAS_SPI_TPM -> SPI_TPM && !TPM_GOOGLE && !TPM_ATMEL config MAINBOARD_HAS_SPI_TPM_CR50 -> SPI_TPM && TPM_GOOGLE Signed-off-by: Jes B. Klinke <jbk@chromium.org> Change-Id: I4656b2b90363b8dfd008dc281ad591862fe2cc9e Reviewed-on: https://review.coreboot.org/c/coreboot/+/63424 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* mb/google: Remove unused cpu deviceYu-Ping Wu2022-03-211-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | The cpu device listed in MediaTek platforms' devicetree.cb doesn't actually do anything, except causing an error during device initialization: CPU: 00 missing read_resources Therefore, remove it from the devicetree. BUG=b:224419346 TEST=emerge-corsola coreboot TEST=Krabby booted up successfully BRANCH=none Change-Id: Ibf9f7cf65da6a0dd0a0e1f556d5772573ba3e930 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62805 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/kukui: Add DRAM support for burnet/escheKevin Chiu2022-01-271-0/+4
| | | | | | | | | | | | | | | | | 0x18 MICRON 4GB LP4X MT53E1G32D2NP-046 WT:B 0x19 HYNIX 4GB LP4X H54G56CYRBX247 0x1a SAMSUNG 4GB LP4X K4UBE3D4AB-MGCL 0x1b HYNIX 8GB LP4X H54G68CYRBX248 BUG=b:165768895 BRANCH=kukui TEST=emerge-jacuzzi coreboot Change-Id: Ib1c09ff2b88bf121de702985680b2388c0fb8427 Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61265 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* mb/google/kukui: Add dedicated memory map for kappaKevin Chiu2022-01-272-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | Add a dedicated memory mapping table starting at index 0x40: 0x40 SAMSUNG 4GB LP4X K4UBE3D4AA-MGCR 0x41 HYNIX 4GB QDP LP4X H9HCNNNCPMALHR-NEE 0x42 MICRON 4GB LP4X MT53E1G32D4NQ-046 WT:E 0x43 MICRON 4GB LP4X MT53E1G32D2NP-046 WT:A 0x44 MICRON 4GB LP4X MT53E1G32D2NP-046 WT:B 0x45 HYNIX 4GB LP4X H54G56CYRBX247 0x46 SAMSUNG 4GB LP4X K4UBE3D4AB-MGCL 0x48 SAMSUNG 4GB LP4X K4UBE3D4AA-MGCL 0x49 MICRON 8GB LP4X MT53E2G32D4NQ-046 WT:A 0x4A HYNIX 4GB QDP LP4X H9HCNNNCPMMLXR-NEE 0x4B Micron MT29VZZZAD9GQFSM BUG=b:162379736 BRANCH=kukui TEST=emerge-jacuzzi coreboot Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Change-Id: I97f296cb8c35fd2f979a05d0b97a0562c1b472f3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57442 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* Reland "vboot_logic: Set VB2_CONTEXT_EC_TRUSTED in verstage_main"Hsuan-ting Chen2021-11-151-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit adb393bdd6cd6734fa2672bd174aca4588a68016. This relands commit 6260bf712a836762b18d80082505e981e040f4bc. Reason for revert: The original CL did not handle some devices correctly. With the fixes: * commit 36721a4 (mb/google/brya: Add GPIO_IN_RW to all variants' early GPIO tables) * commit 3bfe46c (mb/google/guybrush: Add GPIO EC in RW to early GPIO tables) * commit 3a30cf9 (mb/google/guybrush: Build chromeos.c in verstage This CL also fix the following platforms: * Change to always trusted: cyan. * Add to early GPIO table: dedede, eve, fizz, glados, hatch, octopus, poppy, reef, volteer. * Add to both Makefile and early GPIO table: zork. For mb/intel: * adlrvp: Add support for get_ec_is_trusted(). * glkrvp: Add support for get_ec_is_trusted() with always trusted. * kblrvp: Add support for get_ec_is_trusted() with always trusted. * kunimitsu: Add support for get_ec_is_trusted() and initialize it as early GPIO. * shadowmountain: Add support for get_ec_is_trusted() and initialize it as early GPIO. * tglrvp: Add support for get_ec_is_trusted() with always trusted. For qemu-q35: Add support for get_ec_is_trusted() with always trusted. We could attempt another land. Change-Id: I66b8b99d6e6bf259b18573f9f6010f9254357bf9 Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58253 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* mb/google: Add OEM product names for various boardsMartin Roth2021-11-041-6/+6
| | | | | | | | | | | All of these names came from public sources. Signed-off-by: Martin Roth <martin@coreboot.org> Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Change-Id: I1ed9cc0c1ff63dc415e0cc63fa9d2dcd429a093b Reviewed-on: https://review.coreboot.org/c/coreboot/+/57392 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* Revert "vboot_logic: Set VB2_CONTEXT_EC_TRUSTED in verstage_main"Hsuan-ting Chen2021-10-151-6/+0
| | | | | | | | | | | | | | This reverts commit 6260bf712a836762b18d80082505e981e040f4bc. Reason for revert: This CL did not handle Intel GPIO correctly. We need to add GPIO_EC_IN_RW into early_gpio_table for platforms using Intel SoC. Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org> Change-Id: Iaeb1bf598047160f01e33ad0d9d004cad59e3f75 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57951 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* vboot_logic: Set VB2_CONTEXT_EC_TRUSTED in verstage_mainHsuan Ting Chen2021-09-161-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | vboot_reference is introducing a new field (ctx) to store the current boot mode in crrev/c/2944250 (ctx->bootmode), which will be leveraged in both vboot flow and elog_add_boot_reason in coreboot. In current steps of deciding bootmode, a function vb2ex_ec_trusted is required. This function checks gpio EC_IN_RW pin and will return 'trusted' only if EC is not in RW. Therefore, we need to implement similar utilities in coreboot. We will deprecate vb2ex_ec_trusted and use the flag, VB2_CONTEXT_EC_TRUSTED, in vboot, vb2api_fw_phase1 and set that flag in coreboot, verstage_main. Also add a help function get_ec_is_trusted which needed to be implemented per mainboard. BUG=b:177196147, b:181931817 BRANCH=none TEST=Test on trogdor if manual recovery works Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org> Change-Id: I479c8f80e45cc524ba87db4293d19b29bdfa2192 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57048 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* drivers/mipi: Make orientation a property of the mainboard, not panelJulius Werner2021-09-0210-15/+18
| | | | | | | | | | | | | | | | | It doesn't make sense to store the orientation field directly in the panel information structure, which is supposed to be reuseable between different boards. The thing that determines orientation is how that panel is built into the board in question, which only the board itself can know. The same portrait panel could be rotated left to be used as landscape in one board and rotated right to be used as landscape in another. This patch moves the orientation field out of the panel structure back into the mainboards to reflect this. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: If2b716aa4dae036515730c12961fdd8a9ac34753 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57324 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* device/mipi: Move to drivers/mipiJulius Werner2021-08-261-1/+1
| | | | | | | | | | | | | | Sounds like we prefer to have this under drivers/ instead of device/. Also move all MIPI-related headers out from device/ into their own directory. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Ib3e66954b8f0cf85b28d8d186b09d7846707559d Reviewed-on: https://review.coreboot.org/c/coreboot/+/57128 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
* device: Move MIPI panel library from mainboard/google/kukui into commonJulius Werner2021-08-1816-2277/+15
| | | | | | | | | | | | | | | | | | | | | | All boards that are trying to use MIPI panels eventually run into the problem that they need to store physical parameters and a list of DCS initialization commands for each panel, and these commands can be very different (e.g. a large amount of very short commands, a few very large commands, etc.). Finding a data format to fit all these different cases efficiently into the same structures keeps being a challenge, and the Kukui mainboard already once put a lot of effort into designing a clean, flexible and efficient solution for this. This patch moves that framework into a common src/device/mipi/ library where it can be used by other boards as well. (Also, this will hopefully allow us to save some duplicated work when using the same panel on different boards at some point.) Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I877f2b0c7ab984412b288e2ed27f37cd93c70863 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56965 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
* mb/google/kukui: Add new config 'pico' in corebootLucas Chen2021-08-022-1/+6
| | | | | | | | | | | | | | Add new board 'pico' and set correct ram_id offset. BUG=b:194985056 TEST=None BRANCH=kukui Signed-off-by: Lucas Chen <lucas.chen@quanta.corp-partner.google.com> Change-Id: I33c37d99fa0451239bc6626e71bfddb29a11e97b Reviewed-on: https://review.coreboot.org/c/coreboot/+/56691 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
* mb/*: Specify type of `MAINBOARD_PART_NUMBER` onceAngel Pons2021-07-261-1/+0
| | | | | | | | | | | | | | | | Specify the type of the `MAINBOARD_PART_NUMBER` Kconfig symbol once instead of doing so on each and every mainboard. Change-Id: I3692f9e82fe90af4d0da1d037018a20aa1b45793 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56554 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/*: Specify type of `MAINBOARD_DIR` onceAngel Pons2021-07-261-1/+0
| | | | | | | | | | | | | | | | Specify the type of the `MAINBOARD_DIR` Kconfig symbol once instead of doing so on each and every mainboard. Change-Id: If1cc538b0c4938dac193699897b690e402b3c1e8 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56553 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/kukui: Add a new config 'Munna'Sunway2021-07-122-1/+6
| | | | | | | | | | | | | | Introduce a new board 'Munna' to Kukui family. BUG=None TEST=make # select Munna BRANCH=kukui Signed-off-by: Sunway <lisunwei@huaqin.corp-partner.google.com> Change-Id: Ie53750d0b79fe6d7c6e7778ba4616b557708601d Reviewed-on: https://review.coreboot.org/c/coreboot/+/56169 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/kukui: Add rt1015 support for katsuSunway2021-05-201-1/+1
| | | | | | | | | | | | | | | Modify the value of "SPEAKER_GPIO_NAME" in katsu as rt1015p sdb BUG=None BRANCH=kukui TEST=Speaker can work normally in katsu during firmware stage Signed-off-by: Sunway <lisunwei@huaqin.corp-partner.google.com> Change-Id: Ib3672383ab34bb07b4e5eb7f7e8b4549e13c67b6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54642 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/kukui: Add discrete EMCP LPDDR4X table for Kakadu/KatsuSunway2021-05-113-0/+30
| | | | | | | | | | | | | | Add EMCP LPDDR4X DDR FEPRF6432-58A1930 for ram id 9. BUG=b:186141919 BRANCH=kukui TEST=New Emcp can boot normally on kakadu/katsu Signed-off-by: Sunway <lisunwei@huaqin.corp-partner.google.com> Change-Id: Ieaf05a0a7b0c0671c07b0df29319ebd91fe63e57 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54009 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/kukui: Add flag for MIPI_DSI_MODE_LINE_END ANX7625Jitao Shi2021-04-061-1/+2
| | | | | | | | | | | | | | | Config ANX7625 line data end same time on all line. BUG=b:173603645 BRANCH=kukui TEST=Display is normal on Kukui Signed-off-by: Jitao Shi <jitao.shi@mediatek.com> Change-Id: Ia1dc217138a98a79ef2f31225b52ba2b1aaf8672 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51435 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
* mb/google/kukui: fix the issue of getting error panel_idxuxinxiong2021-04-061-1/+1
| | | | | | | | | | | | | | | | | | Current get panel_id is over sku_id() >> 4, but sku_id is combined with wfc_id/lcm_id/sku_id, so the panel_id value is wfc_id << 4 | lcm_id() in fact. When wfc_id is not 0, the panel_id will be wrong. So only get the low 4 bits for the panel_id. BUG=b:183779755 BRANCH=kukui TEST=emerge-kukui Change-Id: I63e0c8a2719462a9b979afe52a27c78b9fc804e8 Signed-off-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51853 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* mb/google/kukui: katsu: update the EDID and initial codeSunway2021-04-061-3/+4
| | | | | | | | | | | | | | The EDID and initial code are provided by STA (the vendor). BUG=b:183969078 TEST=Boots on Chromebook Katsu and displayed developer firmware screen successfully. Signed-off-by: Sunway <lisunwei@huaqin.corp-partner.google.com> Change-Id: I54e72c072b47d2be264ed7f0700812a6c704a104 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51918 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/kukui/var/cozmo: Add RAM ID tableLucas Chen2021-03-312-0/+9
| | | | | | | | | | | | | | | Add the RAM ID table offset 0x30 for cozmo. BUG=b:182776048 BRANCH=kukui TEST=emerge-jacuzzi coreboot Signed-off-by: Lucas Chen <lucas.chen@quanta.corp-partner.google.com> Change-Id: Ia29d38f61975c5e29a901adbfad343153628405f Reviewed-on: https://review.coreboot.org/c/coreboot/+/51845 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/kukui: fine tune the data lane trailJitao Shi2021-03-281-0/+6
| | | | | | | | | | | | | | | | ANX7625 requires customized hs_da_trail time. So override the data trail for ANX7625. BUG=b:173603645 BRANCH=kukui TEST=Display is normal on Jacuzzi Signed-off-by: Jitao Shi <jitao.shi@mediatek.com> Change-Id: I620035363507daaa19e3c272a44059c17be29af1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51433 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Chen-Tsung Hsieh <chentsung@chromium.org>
* mb/google/kukui: Add a new config 'Makomo'Sunway2021-03-232-1/+6
| | | | | | | | | | | | | | A new board introduced to Kukui family. BUG=None TEST=make # select Makomo BRANCH=kukui Signed-off-by: Sunway <lisunwei@huaqin.corp-partner.google.com> Change-Id: I42b84e2c0926e755ba210fc8baac19f8ed2c4e57 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51565 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/kukui: Add new config 'cozmo'Lucas Chen2021-03-172-0/+5
| | | | | | | | | | | | | | | New board 'cozmo'. BUG=b:181144502 TEST=None BRANCH=kukui Signed-off-by: Lucas Chen <lucas.chen@quanta.corp-partner.google.com> Change-Id: Ia0ec1d89444d2634bfcfb3475a422f4e4ae92b7f Reviewed-on: https://review.coreboot.org/c/coreboot/+/51437 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Chen-Tsung Hsieh <chentsung@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* mb/google/kukui: Add Micron 4GB discrete LPDDR4X DDR supportJessy Jiang2021-03-083-0/+29
| | | | | | | | | | | | | | Support 4G+128G MT29VZZZAD9GQFSM-046 W.9S9 discrete DDR bootup. BUG=b:162292216 BRANCH=kukui TEST=Boots correctly on Kukui. Signed-off-by: Jessy Jiang <jiangchao5@huaqin.corp-partner.google.com> Change-Id: I5657a007154bc52c6f0f27e1de6e3294a5e74ad7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48686 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* mb/: Drop the provided name in chip_opsKyösti Mälkki2021-02-211-1/+0
| | | | | | | | | | | Little point to replicate a string already provided both as a global Kconfig and global mainboard_part_number. Change-Id: I1fd138c711ebbb37c39b2c8f554b1f2e1a364424 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50719 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: ron minnich <rminnich@gmail.com>
* mb/google: Remove unused <string.h>Elyes HAOUAS2021-02-161-1/+0
| | | | | | | | | | | Found using: diff <(git grep -l '#include <string.h>' -- src/) <(git grep -l 'STRINGIFY\|memcpy\|memmove\|memset\|memcmp\|memchr\|strdup\|strconcat\|strnlen\|strlen\|strchr\|strncpy\|strcpy\|strcmp\|strncmp\|strspn\|strcspn\|strstr\|strtok_r\|strtok\|atol\|strrchr\|skip_atoi\|snprintf' -- src/)|grep '<' Change-Id: I3ba39077014c50c2dfb9fddf78813f1058c45cc1 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50685 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
* mb/google/kukui: Add byte mode/single rank DRAM support for burnet/escheKevin Chiu2021-02-061-0/+2
| | | | | | | | | | | | | | | | ID#5: Hynix - H9HCNNNFAMMLXR-NEE (Byte mode) ID#7: MICRON - MT53E1G32D2NP-046 WT:A (Single rank) BUG=b:165768895 BRANCH=kukui TEST=1. emerge-jacuzzi coreboot 2. power on test ok Change-Id: Iaa735c23889860218f6f6571cf0bc0b21b304b51 Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50276 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* mb/google/kukui: kakadu: update the initial code for BOE LCDSunway2021-02-041-4/+10
| | | | | | | | | | | | | | The latest initial code is from BOE, the vendor. BUG=b:179206650 BRANCH=kukui TEST=Run long time aging test and the BOE LCD shows normally. Signed-off-by: Sunway <lisunwei@huaqin.corp-partner.google.com> Change-Id: Ibc1bd5147dbda4e3b94023e7ba52ff6a18abba0c Reviewed-on: https://review.coreboot.org/c/coreboot/+/50215 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/kukui: Add panel for Katsuchenzanxi2021-01-254-0/+136
| | | | | | | | | | | | | | | | | Declare the following panel for Katsu: - BOE_TV105WUM_NW0 - STA_2081101QFH032011_53G BUG=b:176523929 TEST=build Katsu image passed BRANCH=kukui Change-Id: I59a02198bc0e13f2760677ae4ea3eb05eb883464 Signed-off-by: chenzanxi <chenzanxi@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49830 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* mb/google/kukui: Enable MT8183_DRAM_EMCP for katsuSunway2021-01-221-1/+1
| | | | | | | | | | | | | | | The katsu project will be using eMCP board design. BUG=b:176271935 TEST=Boots on chromebook katsu successfully. BRANCH=kukui Signed-off-by: Sunway <lisunwei@huaqin.corp-partner.google.com> Change-Id: I733a9a79e2ea6501e26bf79bfce2b1934a295342 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48893 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/kukui: Add discrete EMCP LPDDR4X table for Kakadu/Katsuxuxinxiong2021-01-194-1/+42
| | | | | | | | | | | | | | | | Add EMCP LPDDR4X DDR MT29VZZZCD9GQKPR for ram id 8. BUG=b:176262460 BRANCH=master TEST=emerge-jacuzzi coreboot Change-Id: If00478b9b05ab3ec48b6a8dec37e9f2f9f04e188 Signed-off-by: xuxinxiong <xuxinxiong@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49447 Reviewed-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/kukui: Add new ddr architecture support for kukuiShaoming Chen2021-01-1514-0/+69
| | | | | | | | | | | | | | | | | | Two configuration files are added: 1. H9HCNNNFAMMLXR-NEE-8GB: new byte mode 2. MT53E1G32D2NP-046-4GB: new single rank mode Also initialize the rank number field 'rank_num' for all configs. BUG=b:165768895 BRANCH=kukui TEST=DDR boot up correctly on Kukui Signed-off-by: Shaoming Chen <shaoming.chen@mediatek.corp-partner.google.com> Change-Id: I1786c1e251e8d6e110cbdce79feeb386db220404 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49108 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/kukui: Add panel api after dsi startJitao Shi2021-01-013-26/+36
| | | | | | | | | | | | | | | Some bridge chip or panel requires dsi signal output before dsi receiver works. BUG=b:168728787 BRANCH=kukui TEST=Display is normal on Kukui Signed-off-by: Jitao Shi <jitao.shi@mediatek.com> Change-Id: I3bded27087490f32ee233e615cfad1fd05fb582d Reviewed-on: https://review.coreboot.org/c/coreboot/+/47380 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* mb/google/kukui: Add a new config 'Katsu'Sunway2020-12-242-0/+5
| | | | | | | | | | | | | | | A new board introduced to Kukui family. BUG=b:176206134 TEST=make # select Katsu BRANCH=kukui Signed-off-by: Sunway <lisunwei@huaqin.corp-partner.google.com> Change-Id: I09fe2b8f6922dfd2af6424830568466fb98f7aee Reviewed-on: https://review.coreboot.org/c/coreboot/+/48874 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* drivers: Replace set_vbe_mode_info_validPatrick Rudolph2020-12-171-1/+1
| | | | | | | | | | | | | | | | | | | | | | | Currently it's not possible to add multiple graphics driver into one coreboot image. This patch series will fix this issue by providing a single API that multiple graphics driver can use. This is required for platforms that have two graphic cards, but different graphic drivers, like Intel+Aspeed on server platforms or Intel+Nvidia on consumer notebooks. The goal is to remove duplicated fill_fb_framebuffer(), the advertisment of multiple indepent framebuffers in coreboot tables, and better runtime/build time graphic configuration options. Replace set_vbe_mode_info_valid with fb_add_framebuffer_info or fb_new_framebuffer_info_from_edid. Change-Id: I95d1d62385a201c68c6c2527c023ad2292a235c5 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39004 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
* mb/google/kukui: help payload to identify correct speaker amp typeHung-Te Lin2020-12-152-1/+15
| | | | | | | | | | | | | | | | | Kukui based devices may use different speaker amplifiers, for example MAX98357A, RT1015, or RT1015Q/automode. To help payloads identifying which component was installed on board, we want to pass the speaker GPIO in different name. This can be set in Kconfig as CONFIG_SPEAKER_GPIO_NAME. BUG=b:174534548 TEST=emerge-kukui coreboot depthcharge chromeos-bootimage BRANCH=kukui Signed-off-by: Hung-Te Lin <hungte@chromium.org> Change-Id: I4b44b026bee4d3b58646eee207aea0120071dd46 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48558 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* lib/edid_fill_fb: Support multiple framebuffersPatrick Rudolph2020-12-101-2/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | Currently it's not possible to add multiple graphics driver into one coreboot image. This patch series will fix this issue by providing a single API that multiple graphics driver can use. This is required for platforms that have two graphic cards, but different graphic drivers, like Intel and Aspeed on server platforms or Intel and Nvidia on consumer notebooks. The goals are to remove duplicated fill_fb_framebuffer(), to advertise multiple independent framebuffers in coreboot tables, and better runtime/build time graphic configuration options. Add an implementation in edid_fill_fb that supports registering multiple framebuffers, each with its own configuration. As the current code is only compiled for a single graphics driver there's no change in functionality. Change-Id: I7264c2ea2f72f36adfd26f26b00e3ce172133621 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39002 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-15 22:49:21 +0000