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path: root/src/mainboard/google/octopus/romstage.c
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* mb/google/octopus: make new targets have DRAM part in CBI by defaultAaron Durbin2019-06-121-6/+1
| | | | | | | | | | | | | | | | | | All new targets utilizing octopus mainboard support default to always using DRAM_PART_NUM_IN_CBI. This allows easier addition of new targets. BUG=b:132668378 BRANCH=octopus Change-Id: Idb136aa960260abe1657b16ded02a7dfb63c6849 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33370 Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Fix code that would trip -Wtype-limitsJulius Werner2019-05-061-1/+1
| | | | | | | | | | | | | | | This patch fixes up all code that would throw a -Wtype-limits warning. This sometimes involves eliminating unnecessary checks, adding a few odd but harmless casts or just pragma'ing out the warning for a whole file -- I tried to find the path of least resistance. I think the overall benefit of the warning outweighs the occasional weirdness. Change-Id: Iacd37eb1fad388d9db7267ceccb03e6dcf1ad0d2 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32537 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* src: Use 'include <string.h>' when appropriateElyes HAOUAS2019-03-201-1/+1
| | | | | | | | | | | | | Drop 'include <string.h>' when it is not used and add it when it is missing. Also extra lines removed, or added just before local includes. Change-Id: Iccac4dbaa2dd4144fc347af36ecfc9747da3de20 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31966 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
* coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)Julius Werner2019-03-081-2/+2
| | | | | | | | | | | | This patch is a raw application of find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g' Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* mb/google/octopus: Use DIMM_INFO_PART_NUMBER_SIZE for part_num_storeFurquan Shaikh2018-10-241-1/+2
| | | | | | | | | | | | | | | | | This change uses DIMM_INFO_PART_NUMBER_SIZE to decide the size of part_num_store that holds the number of DRAM part. It ensures that host advertises the supported size to read part number from the EC. BUG=b:115697578 Change-Id: I8439a301fc037b0acdc8b1226ad04d2f363838ef Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/29241 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Jett Rink <jettrink@chromium.org>
* mb/google/octopus: add support for fetching DRAM part number from CBIAaron Durbin2018-08-091-1/+30
| | | | | | | | | | | | | | | | | | | | | | | | | Add 3 new Kconfig options: DRAM_PART_NUM_IN_CBI DRAM_PART_NUM_ALWAYS_IN_CBI DRAM_PART_IN_CBI_BOARD_ID_MIN These control whether to 1. attempt to use CBI at all 2. always use cbi and 3. conditionally use cbi based on board id. The intent is that the MIN variant would be used for the tranisition period then cut over to ALWAYS after full transition. Since multiple OEMs have different schedules these options are there to bridge the gap. yorp. bip, and octopus build targets would never flip DRAM_PART_NUM_IN_CBI, but in case someone does the MIN values are 255 to always take the old path. BUG=b:112203105 TEST=Set correct part number on phaser during testing. Change-Id: If9a0102806d78e89330b42aa6947d503a8a2deac Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/27946 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
* mb/google/octopus: save dimm info as SMBIOS Table-17Ravi Sarawadi2018-04-301-0/+1
| | | | | | | | | | | | | | | | | Save FSP provided memory HOB info as SMBIOS Table-17 format. Firmware tools such as mosys, dmidecode uses SMBIOS Table-17 to report memory metadata. BUG=b:78651920 TEST=Build for Octopus and check 'dmidecode -t17' and 'mosys memory spd print all' to verify dimm info. Change-Id: I9b032b766a2927725b2378f7f720644d4459f602 Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Reviewed-on: https://review.coreboot.org/25881 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
* mb/google/octopus: Add LPDDR4 memory initRavi Sarawadi2018-02-281-0/+2
| | | | | | | | | | | | | | Add LPDDR4 initialization support. BUG=b:73136980 BRANCH=None TEST=Build coreboot for Octopus board. Change-Id: Ieffcfa2f9d075eb0be13562f1a0c7ee503b005d9 Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Reviewed-on: https://review.coreboot.org/23832 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* mb/google/octopus: Add new boardHannah Williams2018-02-151-0/+27
Add octopus board using GLK soc. Copied base code from mainboard/intel/glkrvp. TODO: Fix as per octopus schematic. Change-Id: Ic8c25b3fafbfef31b8b3b802acb3bc53ee7146b6 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/23685 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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