| Commit message (Collapse) | Author | Age | Files | Lines |
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The default state for the IRQ lines when the eSPI controller comes out
of reset is high. This is because the IRQ lines are shared with the
other IRQ sources using AND gates. This means that in order to not cause
any spurious interrupts or miss any interrupts, the IO-APIC must use a
low polarity trigger.
On zork/guybrush/skyrim the eSPI IRQs are currently working as follows:
* On power on/resume the eSPI controller drives IRQ 1 high.
* eSPI controller gets configured to not invert IRQ 1.
* OS configures IO-APIC IRQ 1 as Edge/High.
* EC writes to HIKDO (Keyboard Data Out) which causes the EC to set IRQ1
high.
* eSPI controller receives IRQ 1 high, doesn't invert it, and leaves IRQ
1 as high. This results in missing the first interrupt.
* When the x86 reads from HIKDO, the EC deasserts IRQ1. This causes the
eSPI controller to set IRQ1 to low. We are now primed to catch the
next edge high interrupt. This is generally not a problem since the
linux driver will probe the 8042 with interrupts off.
On S3/S0i3 resume since the eSPI controller comes out of reset driving
the IRQ lines high, we trigger a spurious IRQ since the IO-APIC is
configured to trigger on edge high. This results in the 8042 controller
getting incorrectly marked as a wake trigger.
By configuring the IO-APIC to use low polarity interrupts, we no longer
lose the first interrupt. This also means we can use a level interrupt
to match what the EC actually asserts.
We use the `Interrupt` keyword instead of the `IRQ` keyword in the ACPI
because the linux kernel will ignore the level/polarity parameters
for the `IRQ` keyword and default to `edge/high. `Interrupt` doesn't
have this problem.
The PIC is not currently configured anywhere and it defaults to an
edge/high trigger. We could add some code to configure the PICs trigger
register, but I don't think we need the functionality right now.
For zork and guybrush, this change is a no-op. eSPI is configured in
verstage which is located in RO, and we have already locked RO for
these devices. We will need to figure out how to properly set the
`vw_irq_polarity` for these devices.
BUG=b:218874489, b:160595155, b:184752352, b:157984427, b:238818104
TEST=On zork, guybrush and skyrim
$ suspend_stress_test --post_resume_command 'cat /sys/devices/platform/i8042/serio0/wakeup/wakeup35/active_count'
Verify keyboard works as expected and no interrupt storms are observed.
On morphius I verified keyboard and mouse work on windows as well.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I4608a7684e34ebb389e0e55ceba7e7441939afe7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54924
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Move GPIO init for SSD_AUX_RESET_L to ensure that eMMC devices
will be initialized in time for the nominal boot flow.
BUG=b:237701972
TEST=Boots to OS
BRANCH=none
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I610966fd9d31581f15d8bcd51f8a116c27fd6311
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66461
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Enabling required config items to execute verstage in PSP.
BUG=b:217414563
TEST=Build and boot to OS in Skyrim with PSP verstage.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: Iee14dc80cb6691acb5cb59a21da5a3dff69f7dd2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66135
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add two memory parts and generate the associated DRAM part ID.
1) Hynix H9JCNNNBK3MLYR-N6E
2) Hynix H58G56AK6BX069
BUG=b:228415394
TEST=none
Change-Id: I0f5ca291e02e209032e2533f4b2d4241b5e62e42
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66062
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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The generic wifi driver currently contains a lot of intel-specific
functionality that interferes with enabling wake-on-lan. This commit
changes the device tree to use the generic PCIe driver which better
supports this functionality.
BUG=b:237682766
TEST=Booted on skyrim device and verified that wake on LAN works
Signed-off-by: Robert Zieba <robertzieba@google.com>
Change-Id: I5d15d33fd0a152eb3bf2bfe78e802483a701e750
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65800
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Skyrim uses second SPI pads for ESPI. Switch to it initialize ESPI in
verstage.
BUG=b:217414563
TEST=Build Skyrim BIOS image. Ensure that ESPI init is successful in PSP
verstage.
Change-Id: I6e3462e95c50d256b6c159ae1d854dd69a538bb0
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65862
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Martin L Roth <gaumless@tutanota.com>
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Now that the speed is limited to 5500 Mbps for all memory parts used in
Skyrim, regenerate the part IDs. Remove any custom generated part IDs
and the associated SPDs.
BUG=b:238074863
TEST=Build and boot to OS in Skyrim.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I6d8326208580a971e781887a7ec83355bb085c7f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65709
Reviewed-by: Robert Zieba <robertzieba@google.com>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This allows the mainboard code to change FSP-M parameters depending on
parameters that are only known at run time and not at build time.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I3e0e196a5d861acd7635c59db44ecf1970b73ce2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65855
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
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Branding changes to unify and update Chrome OS to ChromeOS (removing the
space).
This CL also includes changing Chromium OS to ChromiumOS as well.
BUG=None
TEST=N/A
Change-Id: I39af9f1069b62747dbfeebdd62d85fabfa655dcd
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65479
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
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Add fingerprint device and select UART_ACPI driver.
Disable FPMCU until the proper boot segment initializes it.
BUG=b:228271993
BRANCH=NONE
TEST=Can add fingerprints and unlock the device using them.
Signed-off-by: Moises Garcia <moisesgarcia@google.com>
Change-Id: I71e1c7d654395284cdec43bb6e5f581e546da36a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65299
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bhanu Prakash Maiya <bhanumaiya@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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The temperature values were taken from guybrush as a starting point for
skyrim.
BUG=b:230428864
TEST=Boot skyrim to OS and verify thermal zones are populated and
working in /sys/class/thermal/
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I6669b32f5e3dd63c6523f74166089eb4eb2d7848
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65457
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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With IOMMU disabled, kernel complains that 'IOMMUv2 functionality not
available on this system'. Enable iommu in devicetree for skyrim proto
board in order to allow kernel to load and initialize IOMMUv2.
BUG=b:232750390
TEST=Boot to Chrome OS on skyrim board, and
grep dmesg for "AMD IOMMUv2 loaded and initialized"
Change-Id: I2f10f5eda8083335619a34c44df253b8e5a8572c
Signed-off-by: Jason Glenesk <Jason.Glenesk@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65190
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
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This patch adds a new CONFIG_VBOOT_GSCVD option that will be enabled by
default for TPM_GOOGLE_TI50 devices. It makes the build system run the
`futility gscvd` command to create a GSCVD (GSC verification data) which
signs the CBFS trust anchor (bootblock and GBB). In order for this to
work, boards will need to have an RO_GSCVD section in their FMAP, and
production boards should override the CONFIG_VBOOT_GSC_BOARD_ID option
with the correct ID for each variant.
BUG=b:229015103
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I1cf86e90b2687e81edadcefa5a8826b02fbc8b24
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64707
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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The APOB data in DRAM is larger than the 96 kBytes of RW_MRC_CACHE, so
it won't fit in the flash and makes soc_update_apob_cache return early
before writing the APOB data from DRAM into the flash with this warning:
[WARN ] RAM APOB data is too large 1db18 > 18000
Increasing the RW_MRC_CACHE size to 120 kByte fixes this.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I763d20f504d4f5b7cea68f21f409de9a1035f440
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64555
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch uses ACPI _PLD macros to add custom values for USB ports.
+----------------+
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| Screen |
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+----------------+
C0 | | C1
A0 | MLB DB |
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+----------------+
BUG=b:232298017
TEST=None
Signed-off-by: Won Chung <wonchung@google.com>
Change-Id: Idca3dd468f1b9fde37a1bbf20d65768032c7160b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64875
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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Add two combination:
1. ALC5682I-VS and ALC1019
2. NAU88L25 and MAX98360
BUG=b:227165780, b:228879074
TEST=emerge-skyrim coreboot chromeos-bootimage
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Change-Id: I36d7b5c4e88825ceaa6922d9e3bed366f55a0d81
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63779
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-hsuan Hsu <yuhsuan@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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Skyrim uses the Ti50 GSC and the config should be updated to
reflect that.
BUG=b:233750667
TEST=Builds
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I5d4af19ab2dda35ab687a0659898d79b08c4de97
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64669
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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The HDMI port was specified as a display port. Update to allow
for testing of 4k streaming.
BUG=b:229771029
TEST=Builds
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: Ib4dc8a5c6110630cea768f81e34fd7b0a5a62657
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64654
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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On Skyrim, the power and lid switches are managed by the EC
and coreboot and the AP have no control over them within this
context. Remove unused GPIO's to prevent coreboot warnings
about resampling at boot.
BUG=b:233771163
TEST=Builds
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: Ie369bb7d430bd0dd1f1c1f41bf543a9b18e34db1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64644
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia6c5b3f83b66a2d54611ada3cb97ddda4b655d00
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64606
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The HD audio controller of the GPU on bus A device 0 function 1 wasn't
enabled, so it didn't get resources assigned. Enable it to fix this.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib9a4129ce594c5dd59f70e855fef5f2c04ebb9c1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64554
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The ACP device on bus A device 0 function 5 wasn't enabled, so it didn't
get resources assigned. Enable the ACP device to fix this.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ifc9376314213e9d624756519f703d508411cb1bb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64553
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The crypro device on bus A device 0 function 2 wasn't enabled, so it
didn't get resources assigned resulting in this the Linux kernel error:
[ 38.582036] pci 0000:04:00.2: attach allowed to drvr ccp [internal device]
[ 38.582064] ccp 0000:04:00.2: enabling device (0000 -> 0002)
[ 38.582175] ccp 0000:04:00.2: ioremap failed
[ 38.582178] ccp 0000:04:00.2: initialization failed
[ 38.582181] ccp: probe of 0000:04:00.2 failed with error -12
Enable the crypto device to fix this.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia812df6e59f3767dcbaa908fa620b62619590f85
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64552
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Select EC_GOOGLE_CHROMEEC_SKUID and EC_GOOGLE_CHROMEEC_BOARDID to
provide common routine for reading skudid and boardid from Chrome EC.
BUG=b:229052726
TEST=emerge-skyrim coreboot chromeos-bootimage
Check the corresponding directory gets mounted to /run/chromeos-config/v1
Change-Id: I6aff02d29d44e95cd9b9e9485593c81f0d4a4b0e
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64378
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
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Fix descriptors for USB ports to align with their function and
placement with respect to the schematics.
BUG=N/A
TEST=Builds
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: If57bebf9bffd4616c437ec655b64cab3298ac08e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64530
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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Enable MKBP (Matrix Keyboard Protocol) interface for all skyrim family
to use for buttons and switches. Disable TBMC (Tablet Mode Switch
device), as it is not needed anymore.
BUG=b:230682161
TEST=manual test on Skyrim:
Volume Up/Down and Power buttons, Tablet Mode switch
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Change-Id: I79ee2fdbb325491c9e3df5b9cff0c0c1181a7001
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64066
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
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Add Fibcom FM101-GL USB WWAN configuration with the required power
sequence as suggested in Fibocom FM101-GL Hardware Guide V1.0.
BUG=b:227761300
TEST=Build and boot to OS in Skyrim. Ensure that the WWAN module is
enumerated in the output of lsusb.
localhost ~ # lsusb
Bus 004 Device 003: ID 2cb7:01a2 Fibocom Wireless Inc. Fibocom FM101-GL Module
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I39f8e7204e31d9a4d093aacd838a18e6d2f44970
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64004
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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In Skyrim, USB-A port and WWAN modules are connected to the SoC USB
ports through an external hub. Update the USB configuration in the
devicetree accordingly. Enable the ACPI driver for external USB hub.
BUG=b:227761300
TEST=Build and boot to OS in Skyrim. Ensure that the hub and USB-A ports
are enumerated correctly in the output of lusub command.
Change-Id: Ibf6a3da8add7361fc50adcf7c62e46df234685dc
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63586
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Fix power sequence according to datasheet:GL9750S-OIY04 rev1.24.
BUG=b:229181624
TEST=Build and boot to OS in Skyrim. Ensure that the SD Controller
and SD Card are enumerated fine.
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Change-Id: Iea729d43d10a3f8353b4fe540146d00975f4d422
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64023
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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Set native function (SD_AUX_RESET_L), and drive it high.
BUG=b:229181624
TEST=Build and boot to OS in Skyrim. Ensure that the SD Controller
and SD Card are enumerated fine.
02:00.0 SD Host controller: Genesys Logic, Inc GL9750 (rev 01)
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Change-Id: I03d88d90acc03cdebcb1e83ed2e799dda8b5b735
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63739
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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We need to include the SMM handler to enable SCI events when ACPI is
enabled.
With this enabled we now see we have EC timeout problems while in SMI:
[SPEW ] SMI# #1
[WARN ] SMIx88 => 0x800
[DEBUG] Chrome EC: Set SMI mask to 0x0000000000000000
[DEBUG] Chrome EC: UHEPI supported
[ERROR] Timeout waiting for EC QUERY_EVENT!
[DEBUG] Clearing pending EC events. Error code EC_RES_UNAVAILABLE(9) is expected.
[ERROR] EC returned error result code 1
[DEBUG] Chrome EC: Set SCI mask to 0x00000000186601fb
We still need to debug that. I suspect we have problems reading from
the ACPI IO decodes 0x62 or 0x66.
BUG=none
TEST=Verify SMI handler runs
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ida0fcd634e620274e124a8669836f3974e0a2bf4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63844
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
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* Use GPE 24 since it doesn't conflict with any existing GEVENTS.
* Remove IRQ 12 mapping since it's not used.
* Unmask IRQ1 in PM registers.
* Use the new SMITYPE_ESPI_SCI_B SCI.
BUG=b:227282870
TEST=Build and boot to OS in Skyrim.
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I7e9816d67500365ed1d2ee39ef184a1f60321ca1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63704
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Add various verstage init functions to prepare for enable PSP verstage.
BUG=None
TEST=Build Skyrim BIOS image with PSP verstage enabled.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I0d0dba05d4d083e2c6860078676e59cf8f487c87
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63731
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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Break TPM related Kconfig into the following dimensions:
TPM transport support:
config CRB_TPM
config I2C_TPM
config SPI_TPM
config MEMORY_MAPPED_TPM (new)
TPM brand, not defining any of these is valid, and result in "generic" support:
config TPM_ATMEL (new)
config TPM_GOOGLE (new)
config TPM_GOOGLE_CR50 (new, implies TPM_GOOGLE)
config TPM_GOOGLE_TI50 (new to be used later, implies TPM_GOOGLE)
What protocol the TPM chip supports:
config MAINBOARD_HAS_TPM1
config MAINBOARD_HAS_TPM2
What the user chooses to compile (restricted by the above):
config NO_TPM
config TPM1
config TPM2
The following Kconfigs will be replaced as indicated:
config TPM_CR50 -> TPM_GOOGLE
config MAINBOARD_HAS_CRB_TPM -> CRB_TPM
config MAINBOARD_HAS_I2C_TPM_ATMEL -> I2C_TPM && TPM_ATMEL
config MAINBOARD_HAS_I2C_TPM_CR50 -> I2C_TPM && TPM_GOOGLE
config MAINBOARD_HAS_I2C_TPM_GENERIC -> I2C_TPM && !TPM_GOOGLE && !TPM_ATMEL
config MAINBOARD_HAS_LPC_TPM -> MEMORY_MAPPED_TPM
config MAINBOARD_HAS_SPI_TPM -> SPI_TPM && !TPM_GOOGLE && !TPM_ATMEL
config MAINBOARD_HAS_SPI_TPM_CR50 -> SPI_TPM && TPM_GOOGLE
Signed-off-by: Jes B. Klinke <jbk@chromium.org>
Change-Id: I4656b2b90363b8dfd008dc281ad591862fe2cc9e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63424
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Update SPI setting as below:
Normal speed:33mhz
Fast speed:66mhz
Alt speed:66mz
TPM speed:33mhz
BUG=b:225213679
TEST=boot skyrim and verify spi settings.
Signed-off-by: Chris.Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: Icbe4b9f4794f7e883c3819258ede809c3c8922b0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63717
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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This should no longer be needed because the ASL has been fixed.
Change-Id: I4d1500217bef54fa3d2be397e5e2a155da3f965d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63525
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Enable pen garage. Pen detect is active low.
BUG=b:229168203
TEST:Build and boot to OS in skyrim. Evtest work as expected
Input driver version is 1.0.1
Input device ID: bus 0x19 vendor 0x1 product 0x1 version 0x100
Input device name: "PRP0001:00"
Supported events:
Event type 0 (EV_SYN)
Event type 5 (EV_SW)
Event code 15 (SW_PEN_INSERTED) state 1
Properties:
Testing ... (interrupt to exit)
Event: time 1649922170.578779, type 5 (EV_SW), code 15 (SW_PEN_INSERTED), value 0
Event: time 1649922170.578779, -------------- SYN_REPORT ------------
Event: time 1649922172.070740, type 5 (EV_SW), code 15 (SW_PEN_INSERTED), value 1
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Change-Id: I3bb07af6aebdc355a73148d8be79b1014147f61d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63633
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Add Goodix touchscreen according to the Programming Guide Rev.0.7
BUG=b:228907558
TEST=local build and tested with Goodix touch screen
Change-Id: I35dd3ca76e9e0f17508bef46c90b53b4be5d0033
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63573
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Update the build scripts to inject variant specific SPDs into APCB.
BUG=None
TEST=Build and boot to OS in Skyrim boards with all the concerned memory
parts.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I3b3f6f248d54681c6f55c00660d1f2988ae906ba
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63600
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add supported memory parts and generate the associated DRAM part ID.
Also for MT62F2G32D8DR-031 WT:B memory part, add a custom SPD that
configures the DRAM speed at 5500 MHz. Use this custom SPD until that
part can operate at full speed (i.e. 6400 MHz).
BUG=None
TEST=Build Skyrim.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: Id87e79f5d6187d57d74487841c09aa309f1450b4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63599
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Robert Zieba <robertzieba@google.com>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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Change-Id: I88406fa1b54312616e6717af3d924436dc4ff1a6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58899
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Setting the clock source depends on clock request pin for WLAN/SD/SSD
device. Also turn off the unused (CLKREQ#3) clock sources.In skyrim,
clock source 0/1/2 are routed for WLAN/SD/SSD device.
BUG=b:227297986
BRANCH=none
TEST=Build
Signed-off-by: Chris.Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: I21fb912b69f59717eb4e84c379f706a0257a9ed1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63295
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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The only purpose of mainboard_chromeos_acpi_generate()
was to pass cros_gpio array for ACPI \\OIPG package
generation.
Promote variant_cros_gpio() from baseboards to ChromeOS
declaration.
Change-Id: I5c2ac1dcea35f1f00dea401528404bc6ca0ab53c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58897
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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* Use dedicated ALERT pin to resolve NO_RESPONSE error/status while
getting target configuration.
* Configure the ESPI to operate at 16 MHZ since operating at 33 MHz
causes boot stall.
BUG=b:226635441
TEST=Build and Boot to OS in Skyrim. Ensure that EC <-> AP communication
is working fine through Host Command debug logs in EC console, ectool
version command.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I951afdada8ee4f917cdeba8e287e5a2ae77c97ee
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63286
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add support for ELAN trackpad on I2C0 bus.
BUG=None
TEST=Build and boot to OS in Skyrim. Perform evtest on Elan trackpad.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: Ia1522af3f35ef131dda74c4aabecc4fa532dfbec
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63236
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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We are using the second SPI pads for eSPI.
BUG=b:226635441
TEST=Build skyrim
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I43713d7376a28ced2be635668836464ceec46392
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63096
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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ESPI is not initialized in PSP. Hence any attempt to write to port80
causes failure to boot. Disable PSP postcodes for now and re-enable it
later after ESPI is initialized in PSP.
BUG=b:224618411
TEST=Build and boot to OS in Skyrim.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I73b7ddec50936f7836f915f459ca0bdc0777cb22
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63119
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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This will setup the eSPI GPIOs in bootblock right before eSPI init.
BUG=b:226635441
TEST=build skyrim
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I6ff32bf840aa4b757e98d876cbd4e2ba15a760da
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63094
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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The eSPI CS function only exists on AGPIO30.
We will need to rework all boards to make eSPI function.
I also fixed the comments on the other eSPI pins.
BUG=b:226635441
TEST=Build skyrim
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ib03c0a7dcad31d10dd4bad0d10a0184ab84aef9a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63093
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Add Skyrim DXIO descriptors using info from AMD and skyrim bouard
shematics.
BUG=b:225179599
TEST=Boots to OS on Skyrim Board
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: Ib68cf3d64641b006e0f2c4805af22b44a505a0d1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62903
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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