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* mb/google/volteer: Disable PM ACPI timer to fix S0i3 regressionMatt DeVillier2024-02-211-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | Keeping the PM timer enabled will disqualify an ADL system from entering S0i3, and will also cause an increase in power during suspend states. The PM timer is not required for brya boards, therefore disabling it. Fixes: 0e90580 (soc/intel: transition full control over PM Timer from FSP to coreboot) This mirrors an identical commit for google/brya: 1ce0f3aab72d ("mb/google/brya: Fix S0i3 regression") TEST=Boot Linux on google/drobit, verify S0i3 counter incrementing after exiting S0ix suspend states. Change-Id: I644e42388c0f6127512bf52e774b79721601ecc9 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80612 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/tigerlake: Drop redundant PcieRpEnableNico Huber2024-02-194-15/+16
| | | | | | | | | | | | | | | The PcieRpEnable option is redundant to our on/off setting in the devicetrees. Let's use the common coreboot infrastructure instead. Thanks to Nicholas for doing all the mainboard legwork! Change-Id: Iacfef5f032278919f1fcf49e31fa42bcbf1eaf20 Signed-off-by: Nico Huber <nico.h@gmx.de> Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79920 Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/getac to mb/intel: Add SPDX license headers to Kconfig filesMartin Roth2024-02-182-0/+4
| | | | | | | | | Change-Id: Id859c981d0bf5dcf90bf6858607a9fe726516309 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80592 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
* mb/google/volteer/drobit: Add a board-specific VBT fileMatt DeVillier2024-02-132-1/+2
| | | | | | | | | | | | | | | | | Add a board-specific VBT file compatible with the latest FSP release (requires VBT version 250). TODO: Update all other volteer VBTs to v250 from v240. TEST=build/boot google/volteer (drobit) with edk2 payload Change-Id: Ie25a77be5204dfc8b888082492a285973843037c Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80183 Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* */mem_parts_used.txt: Change Makefile.inc to Makefile.mkMartin Roth2024-01-241-1/+1
| | | | | | | | | | | | Now that the files are renamed, make sure all references to Makefile.inc are updated as well. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I09e235eecf0c32c80a41bfcbbd3580cce6555e10 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80112 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Eric Lai <ericllai@google.com>
* mb/google/sarien to zork: Rename Makefiles from .inc to .mkMartin Roth2024-01-2440-0/+0
| | | | | | | | | | | | | | | | The .inc suffix is confusing to various tools as it's not specific to Makefiles. This means that editors don't recognize the files, and don't open them with highlighting and any other specific editor functionality. This issue is also seen in the release notes generation script where Makefiles get renamed before running cloc. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ib8a2ae26ed4380592d15e1a7b2d682639413af01 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80109 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
* mb/{google,intel}: Update FMD to support CBFS verificationAnil Kumar2023-11-011-2/+0
| | | | | | | | | | | | | | | | | This patch adds the required FMD changes to support the change in cse_lite 'commit Ie0266e50463926b8d377825 ("remove cbfs_unverified_area_map() API in cse_lite")' for CBFS verification. With the change in cse_lite the ME_RW_A/B blobs are now part of FW_MAIN_A/B and corresponding entries in FMD can be removed for boards that currently use them. BUG=b:284382452 Signed-off-by: Anil Kumar <anil.kumar.k@intel.com> Change-Id: I3ca88fee181f059852923d50292b24c0e5b9fd6d Reviewed-on: https://review.coreboot.org/c/coreboot/+/78502 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* treewide: convert to tpm_result_tJon Murphy2023-09-281-2/+2
| | | | | | | | | | | | | | | | Convert TPM functions to return TPM error codes(referred to as tpm_result_t) values to match the TCG standard. BUG=b:296439237 TEST=build and boot to Skyrim BRANCH=None Change-Id: Ifdf9ff6c2a1f9b938dbb04d245799391115eb6b1 Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77666 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* treewide: convert to %#x hex printsJon Murphy2023-09-281-1/+1
| | | | | | | | | | | | | | | Convert hex print values to use the %#x qualifier to print 0x{value}. BUG=b:296439237 TEST=build and boot to Skyrim BRANCH=None Change-Id: I0d1ac4b920530635fb758c5165a6a99c11b414c8 Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78183 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* drivers/tpm: Make temp test value naming consistentJon Murphy2023-09-181-4/+4
| | | | | | | | | | | | | | | | Make naming convention consistent across all functions return values. BUG=b:296439237 TEST=Boot to OS on Skyrim BRANCH=None Change-Id: If86805b39048800276ab90b7687644ec2a0d4bee Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77536 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* mb/google/volteer: Add ACPI display brightness supportMatt DeVillier2023-08-172-1/+4
| | | | | | | | | | | | | | Add support for ACPI display brightness controls, so that panel adjustment is available under Windows. TEST=build/boot Win11 on google/drobit, verify panel brightness controls available and functional. Change-Id: Ic0c026ae09b3fde648db4bdeb4971423953c96a1 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77143 Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/volteer: select ENABLE_TCSS_USB_DETECTIONMatt DeVillier2023-08-061-0/+1
| | | | | | | | | | | | | | Select ENABLE_TCSS_USB_DETECTION for non-ChromeOS builds, to enable booting from TCSS USB-C ports. TEST=build/boot google/drobit, verify able to boot from USB ports using edk2 payload. Change-Id: Ic6ab84dd5d1b980296eac043917d2cc7f14a5536 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76944 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* mb/google/volteer: Add EC_HOST_EVENT_PANIC to SCI maskRob Barnes2023-07-211-1/+2
| | | | | | | | | | | | | | | | | Adding EC_HOST_EVENT_PANIC to SCI mask allows the EC to interrupt the Kernel when an EC panic occurs. If system safe mode is also enabled on the EC, the kernel will have a short period to extract and save info about the EC panic. BUG=b:290985698 BRANCH=firmware-volteer-13672.B TEST=Observe kernel ec panic handler run when ec panics Change-Id: I87173f93d0e47baa816d15dad0777007342b4fdb Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76610 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* mb/google/volteer: Use FW_CONFIG to determine correct SOF audio profileMatt DeVillier2023-05-172-7/+28
| | | | | | | | | | | | | | | Use AUDIO PROBE to determine speaker amp config, set SOF driver profile accordingly. TEST=build/boot Win11 on Delbin and Drobit, verify correct audio profile selected, drivers loaded and functional. Change-Id: I13d787cb5ccb74d2774151ccd5deeb45b3364319 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75232 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* mb/google/volteer/Kconfig: Add variant model namesMatt DeVillier2023-05-081-6/+6
| | | | | | | | | | Change-Id: Id5b0fa96ca8d86ddf20d808f5107a43ad2d0a1e0 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74854 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* vc/google: Decouple DSM_CALIB from CHROMEOSMatt DeVillier2023-05-051-1/+1
| | | | | | | | | | | | | | | | | | | | | | | DSM (Dynamic Speaker Management) uses calibration parameters stored in a VPD (Vital Product Data) FMAP region to configure the audio output via an ACPI _DSD table. This has no dependency on a ChromeOS, and can be used by Linux/Windows drivers if appropriately configured. Remove the dependency of DSM_CALIB (and the calibration file) on CHROMEOS and replace it with VPD, so that non-CHROMEOS builds can utilize this feature as well. Move files from underneath vc/google/chromeos to underscore the point. TEST=build/boot google/nightfury, dump ACPI, verify DSM calibraton parameters present in _DSD table. Change-Id: I643b3581bcc662befc9e30736dae806f94b055af Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74812 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: CoolStar <coolstarorganization@gmail.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
* mb/google/volteer: Add SOF chip driverMatt DeVillier2023-05-046-0/+33
| | | | | | | | | | | | | | | Add SOF chip driver entries for all variants, so that the correct audio config is passed to the OS drivers. TEST=build, boot Windows on several volteer variants, verify audio functional under Windows using coolstar's SOF drivers. Change-Id: I62a96149cec9eeb7b2da8a2337083969a1b0fce0 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74816 Reviewed-by: CoolStar <coolstarorganization@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
* mb/google/volteer/Kconfig: Alphabetize variants, Kconfig selectionsMatt DeVillier2023-05-012-69/+69
| | | | | | | | Change-Id: I634af65cd41e0d70e673d550ed8063abc6eea6d4 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74853 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
* mb/google/volteer: Add VBT data files for variantsMatt DeVillier2023-05-014-0/+16
| | | | | | | | | | | | | | | | | | Add data.vbt files for all variants supported by current volteer recovery image. Several boards use the same VBT, so place the "common" VBT under the baseboard directory and set it as the default. For variants with a unique VBT, override the default and use the file in their respective variant directory. Select INTEL_GMA_HAVE_VBT for all variants which have a VBT file. TEST=build/boot various volteer variants Change-Id: I728ab81938c78f600ff8931a8073d1f7de152c09 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74852 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/volteer/var/delbin: Add new memory supportFrank Chu2023-04-213-3/+5
| | | | | | | | | | | | | | | | Add the new memory support: Samsung K4UBE3D4AB-MGCL BUG=b:274373361 BRANCH=firmware-volteer-13672.B TEST=FW_NAME=delbin emerge-volteer coreboot Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com> Change-Id: Ie88c25b4b0f88ed299711f2b6b94006d5301554c Reviewed-on: https://review.coreboot.org/c/coreboot/+/74556 Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* Makefiles: Drop redundant VARIANT_DIR definitionsKyösti Mälkki2023-04-171-1/+0
| | | | | | | | Change-Id: Ie75ce1eee3179a623da812a6b76c7ec457684177 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74470 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
* treewide: Remove useless "_STA: Status" commentElyes Haouas2023-02-192-10/+10
| | | | | | | | | Change-Id: I99ded00fa6dadb494c1523d00063dbc1fde95614 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73093 Reviewed-by: Tim Crawford <tcrawford@system76.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* treewide: Remove unuseful "_UID: Unique ID" commentElyes Haouas2023-02-172-6/+6
| | | | | | | | Change-Id: I150a4ed94bcaead6eb45f1c4b4952ae6957e0940 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72663 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* treewide: Remove unuseful "_HID: Hardware ID" commentElyes Haouas2023-02-172-6/+6
| | | | | | | | | | Change-Id: I5eb1424e9e6c1fbf20cd0bf68fbb52e1ec97f905 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72661 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Crawford <tcrawford@system76.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* mb/google/volteer/drobit: Add missing TBT devicetree entriesMatt DeVillier2023-02-101-0/+7
| | | | | | | | | | | | | | | Commit ae20d4c78f9f ("mb/google/volteer: Fix USB4 enabling for volteer family") reworked the USB4/TBT config for volteer, but drobit variant was missed for some reason. Add the missing USB4/TBT entries. TEST=build/boot Windows on drobit, verify USB4/TBT functional. Change-Id: I43d771eeaf29b4e141b222ccb05af5cb7ceedc6f Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72141 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* mb/google/volteer/eldrid: Fix touchscreen under WindowsMatt DeVillier2023-02-101-1/+1
| | | | | | | | | | | | | | | Under Win11, a longer delay after asserting reset is needed for the Goodix touchscreen to init properly. Increase the reset delay to match that used for the Goodix touchscreen by other volteer variants (120ms). TEST=build/boot Win11, Linux on eldrid variant with Goodix touchscreen, verify functional. Change-Id: I489f037f0bbade9567aad2ad64404a5ac66965d9 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72580 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* drivers/i2c/generic: Drop 'disable_gpio_export_in_crs' flagMatt DeVillier2023-01-1515-16/+0
| | | | | | | | | | | | | | | | | | | | | | | Exposing the GPIOs via an ACPI PowerResource and the _CRS results in the OS driver and ACPI thinking they own the GPIO. This can cause timing problems because it's not clear which system should be controlling the GPIO. Previously, we flagged as an error any device which set the 'has_power_resource' flag but did not set 'disable_gpio_export_in_crs.' There's no reason to require explicit disablement however, so drop the superfluous 'disable' flag, and change the _CRS generation to check if the GPIOs will be exported via the 'has_power_resource' flag instead. BUG=b:265055477 TEST=build/boot skyrim, dump SSDT and verify touchscreen GPIOs only listed under PRx, not under _CRS. Change-Id: I837ae6c6fe4b8e1c4e10686406cba06bdb7759d2 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71849 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
* mainboard: Remove duplicated <soc/gpio.h>Elyes Haouas2023-01-1313-13/+0
| | | | | | | | | | <gpio.h> chain-include <soc/gpio.h>. Change-Id: Ia57d5cd33c70b6a755babd4db56c64c0e3666f9f Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71817 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* mainboard/acpi: Replace constant "Zero" with actual numberFelix Singer2022-12-272-30/+30
| | | | | | | | | Change-Id: I4f2f02623b060ef0ebefc5aceb713c77a8b1e9a6 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71523 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* mainboard/acpi: Replace constant "One" with actual numberFelix Singer2022-12-272-12/+12
| | | | | | | | | Change-Id: Id1078b14a805eea53d2a7c5a8183a5413f26e115 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71521 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/volteer/eldrid: Correct DDR4 SPDs for EldridJohnny Li2022-12-243-3/+3
| | | | | | | | | | | | | | | | | | Correct DDR4 SPDs from H5AG36EXNDX019 to H5AG36EXNDX017. DRAM Part Name ID to assign H5AG36EXNDX017 0 (0000) BUG=b:236739240 BRANCH=Volteer TEST="FW_NAME=eldrid emerge-volteer coreboot" and verify it builds successfully. Signed-off-by: Johnny Li <johnny_li@wistron.corp-partner.google.com> Change-Id: If248714088835eb5dd48fa12223c273199297228 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71160 Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Zhuohao Lee <zhuohao@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/volteer/var/lindar: Use get_wifi_sar_fw_config_filenameEric Lai2022-12-241-6/+1
| | | | | | | | | | | | | | Use get_wifi_sar_fw_config_filename to remove the duplicate code. WIFI_SAR_CBFS_DEFAULT_FILENAME is not exist, so return the non-exist id has the same outcome. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: Ib34e6b4f435880d62936ae54f19ba2ec752eced2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71123 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
* mb/google/volteer: update ACPI HID/CID for Synaptics touchpadsMatt DeVillier2022-12-233-3/+6
| | | | | | | | | | | | | | | | The currently assigned ACPI HID 'PNP0C50' is not a valid per Windows WHQL validation tests. To ensure compatibility with both Windows and Linux, set the HID to 'SYNA0000' and CID to 'ACPI0C50' as previously done for other boards (eg, google/lulu). TEST=boot Linux 5.1x, Windows 10 on lindar, verify all touchpad functions work correctly. Change-Id: If2deedbd572b771c1e7793a3b3c37a3114aa2a48 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71077 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* mb/google/volteer: Add missing audio codec to HDA probeMatt DeVillier2022-12-2211-0/+11
| | | | | | | | | | | | | | | | Audio codec RT1011_ALC5682I_I2S is listed as a fw_config option in the baseboard, but missing from the HDA device probe list in the variant overridetrees, preventing it from being detected at boot. TEST=build/boot lindar, verify audio codec identified and HDA device not disabled by fw_config. Change-Id: Ib40b095688aac5cf4e0a60dcac250023c4f04c9f Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71150 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* mb/google/volteer: Use runtime detection for touchscreensMatt DeVillier2022-12-2218-30/+30
| | | | | | | | | | | | | | | | | | Now that power sequencing has been implemented, switch from using ACPI "probed" flag to "detect" flag for all i2c touchscreens. This removes non-present devices from the SSDT and relieves the OS of the burden of probing. BUG=b:121309055 TEST=build/boot Windows/linux on multiple volteer variants, verify all touchscreens functional in OS, dump ACPI and verify only i2c devices actually present on the board have entries in the SSDT. Change-Id: I0448d12a36f522b715e1fbeb8d37eb5a925ebc93 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71183 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/volteer: Set touchscreen IRQs to LEVEL vs EDGEMatt DeVillier2022-12-222-2/+2
| | | | | | | | | | | | | The GPIOs themselves are configured as level triggered, and the drivers (both Linux and Windows) work better with LEVEL vs EDGE triggering. TEST=tested with rest of patch train Change-Id: I269361f90a838d7766ad429afe82ef885f0d9371 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71182 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/volteer: Implement touchscreen power sequencingMatt DeVillier2022-12-2218-19/+289
| | | | | | | | | | | | | | | | For touchscreens on volteer variants, drive the enable GPIO high starting in romstage, then disable the reset GPIO in ramstage. This will allow coreboot to detect the presence of i2c touchscreens during ACPI SSDT generation (implemented in a subsequent commit). BUG=b:121309055 TEST=tested with rest of patch train Change-Id: Ie4c3b94594253ced6a875af78e6390cda8dcbc7d Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71181 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/volteer: Add method to set GPIOs in romstageMatt DeVillier2022-12-224-0/+13
| | | | | | | | | | | | | | | Add method variant_romstage_gpio_table() with empty weak implementation to allow variants to override as needed for touchscreen power sequencing (to be implemented in a subsequent commit). Call method in romstage to program any GPIOs the variant may need to set. TEST=tested with rest of patch train Change-Id: Ib3c2a0e849006b7bf70cbd0bf6f32aa01ccf1bc4 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71180 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* {soc/intel/cmn/pcie, mb/google/volteer}: Rename `is_external` variableKapil Porwal2022-11-291-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Name a variable based on its utility. `is_external` variable adds `ExternalFacingPort` _DSD property to an ACPI device hence rename it to `add_acpi_external_facing_port`. BUG=b:259716145 TEST=Build google/rex with this flag and verify it in SSDT at runtime. SSDT snippet: Name (_DSD, Package (0x04) // _DSD: Device-Specific Data { ToUUID ("6211e2c0-58a3-4af3-90e1-927a4e0c55a4"), Package (0x01) { Package (0x02) { "HotPlugSupportInD3", One } }, ToUUID ("efcc06cc-73ac-4bc3-bff0-76143807c389"), Package (0x01) { Package (0x02) { "ExternalFacingPort", One } } }) Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I65100283ed9b65037c9890f28ecab41fcfa25d83 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69970 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/volteer: add VBTs for lindar variantMatt DeVillier2022-10-204-0/+3
| | | | | | | | | | | | | | Add VBT data files, ensure secondary VBTs compiled in as needed, select INTEL_GMA_HAVE_VBT. TEST=build/boot lindar variant with FSP/GOP display init, edk2 payload Change-Id: I81022670fabda7994e292d333c999b508e61b469 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68465 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* mainboard/google: Remove ACPI ALS deviceGwendal Grignou2022-10-181-3/+0
| | | | | | | | | | | | | | | | | | | Remove the ACPI ALS device from the EC configuration for newer devices, because some do not have light sensors, and those who do have their ALS presented through the new EC sensor interface already. Inspired from commit ("f13e2501525f ("UPSTREAM: mainboard/google/eve: Remove ACPI ALS device") BUG=b:253967865 BRANCH=none TEST=Boot a device and ensure that 'acpi-als' device is not present in /sys/bus/iio/devices. Change-Id: Ibcfa9e8c5a4679d557150998fd255789d3f8a272 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68493 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/volteer: rename baseboard GPIO table getter for clarityMatt DeVillier2022-09-273-3/+3
| | | | | | | | | | | | | | Rename variant_base_gpio_table() to baseboard_gpio_table(), since the GPIO table comes from the baseboard, and is overridden by a separate table from the variant. Drop the __weak qualifier as this function is not overridden. Change-Id: Id1e1a67608454466dc65bf4c4985cf4eba84c97d Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67807 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/*/{device,override}tree: Set touchpads to use detect (vs probed) flagMatt DeVillier2022-09-0918-23/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | Historically, ChromeOS devices have worked around the problem of OEMs using several different parts for touchpads/touchscreens by using a ChromeOS kernel-specific 'probed' flag (rejected by the upstream kernel) to indicate that the device may or may not be present, and that the driver should probe to confirm device presence. Since c636142b, coreboot now supports detection for i2c devices at runtime when creating the device entries for the ACPI/SSDT tables, rendering the 'probed' flag obsolete for touchpads. Switch all touchpads in the tree from using the 'probed' flag to the 'detect' flag. Touchscreens require more involved power sequencing, which will be done at some future time, after which they will switch over as well. TEST: build/boot at least one variant for each baseboard in the tree. Verify touchpad works under Linux and Windows. Verify only a single touchpad device is present in the ACPI tables. Change-Id: I47c6eed37eb34c044e27963532e544d3940a7c15 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67305 Reviewed-by: Sean Rhodes <sean@starlabs.systems> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/**/dsdt.asl: Drop misleading "OEM revision" commentAngel Pons2022-08-161-1/+1
| | | | | | | | | | | | | | | | It is highly unlikely that the "OEM revision" of the DSDT is 0x20110725 on mainboards with a chipset not yet released on 2011-07-25. Since this comment is most likely to have been copy-pasted from other boards, drop it from boards which use a chipset newer than Sandy/Ivy Bridge. Change-Id: If2f61d09082806b461878a76b286204ae56bf0eb Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66715 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
* mb/google/volteer/eldrid:add new generic DDR4 SPDs for EldridJohnny Li2022-07-143-1/+3
| | | | | | | | | | | | | | | | | Update DDR4 SPDs to Eldrid to include the following: DRAM Part Name ID to assign H5AG36EXNDX019 0 (0000) BUG=b:236739240 BRANCH=Volteer TEST="FW_NAME=eldrid emerge-volteer coreboot" and verify it builds successfully. Signed-off-by: Johnny Li <johnny_li@wistron.corp-partner.google.com> Change-Id: I2c372fa40899aa750d335825cf3880bc52a612a7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65819 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* treewide: Unify Google brandingJon Murphy2022-07-042-2/+2
| | | | | | | | | | | | | | | | | Branding changes to unify and update Chrome OS to ChromeOS (removing the space). This CL also includes changing Chromium OS to ChromiumOS as well. BUG=None TEST=N/A Change-Id: I39af9f1069b62747dbfeebdd62d85fabfa655dcd Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65479 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* security/vboot: Add support for GSCVD (Google "RO verification")Julius Werner2022-06-211-0/+4
| | | | | | | | | | | | | | | | | | This patch adds a new CONFIG_VBOOT_GSCVD option that will be enabled by default for TPM_GOOGLE_TI50 devices. It makes the build system run the `futility gscvd` command to create a GSCVD (GSC verification data) which signs the CBFS trust anchor (bootblock and GBB). In order for this to work, boards will need to have an RO_GSCVD section in their FMAP, and production boards should override the CONFIG_VBOOT_GSC_BOARD_ID option with the correct ID for each variant. BUG=b:229015103 Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I1cf86e90b2687e81edadcefa5a8826b02fbc8b24 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64707 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* mb/google/volteer: Fix wrong Type-C port for retimerDerek Huang2022-06-131-1/+1
| | | | | | | | | | | | | | | | | This change fixes wrong type-C port number for voxel. Voxel uses tcss_usb3_port1 not tcss_usb3_port3. BUG=b:231344977 BRANCH=volteer TEST=Check the transactions are happening on correct port. Also checked retimer firmware update on both the ports. Signed-off-by: Derek Huang <derek.huang@intel.corp-partner.google.com> Change-Id: Iba7b3b15296bed99d3626a6d53dfd59e8d20fe5f Reviewed-on: https://review.coreboot.org/c/coreboot/+/64022 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/eldrid: Fix use of floatArthur Heymans2022-05-141-1/+1
| | | | | | | | | | | | Floats are not allowed in coreboot. As the compiler rounded down the value, do so in the code too as this is a known good value. Change-Id: I4e180d4cb8e0e1aa68186bfc1daffdc5c339dc64 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64240 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
* soc/intel/tigerlake: Add enum for `DdiPortXConfig`Angel Pons2022-05-051-2/+2
| | | | | | | | | | | | | | Add an enum for `DdiPortXConfig` devicetree options. Note that setting these options to zero does not disable the corresponding DDI port, but instead indicates that no LFP (Local Flat Panel, i.e. internal LCD) is connected to it. Change-Id: I9ea10141e51bf29ea44199dcd1b55b63ec771c0a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64047 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Tim Crawford <tcrawford@system76.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-29 14:14:22 +0000