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* lillipup: provide additional VBT for lillipup OLED skuKevin Chang2021-04-142-0/+12
| | | | | | | | | | | | | | | | | | | | Lillipup add two sku for OLED panel. Additional VBT is necessary to modify PWM source from VESA eDP AUX interface BUG=b:183630802 TEST=emerge-volteer coreboot-private-files-baseboard-volteer check vbt_oled.bin is under build folder and check in CPU log. Cq-Depend: chrome-internal:3744227 Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com> Change-Id: I576297b8296def3c37a01ae0223fa332aa9f02b1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52150 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Zhuohao Lee <zhuohao@google.com> Reviewed-by: YH Lin <yueherngl@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/volteer/var/lindar: Configure unused GPIOs as NCKevin Chang2021-04-091-6/+26
| | | | | | | | | | | | | Configure unused GPIOs as NC BUG=b:180830117 TEST=Build and boot lindar to OS. Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com> Change-Id: I0ba51dc262ccbf22b45d3be4b65e006f92587fd8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52151 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
* intel/tigerlake: Add Acoustic featuresShaunak Saha2021-04-066-55/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On VCCin there was an oscillation which occurred just as the kernel started (kernel starting... message). On some devices, this behavior seems even worse. In previous platforms VCCin toggled for a few ms and then was stable. For volteer, this happens at the same point in time for around 40ms. However, it starts oscillating again later in the boot sequence. Once at the root shell, it seems to oscillate indefinitely at around 100-200Hz (very variable though). To fix this we need to control the deep C-state voltage slew rate.We have options for controlling the deep C-state voltage slew rate through FSP UPDs. This patch expose the following FSP UPD interface into coreboot: - AcousticNoiseMitigation - FastPkgCRampDisable - SlowSlewRate We are setting SlowSlewRate for all volteer boards to 2 which is Fast/8. TGL has a single VR domain(Vccin). Hence, the chip config is updated to allow mainboards to set a single value instead of an array and FSP UPDs are accordingly set. BUG=b:153015585 BRANCH=firmware-volteer-13672.B TEST= Measure the change in noise level by changing the UPD values. Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Change-Id: Ica7f1f29995df33bdebb1fd55169cdb36f329ff8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50870 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
* mb/google/volteer/var/lindar: Increase Goodix touchscreen reset delay to 180 msKevin Chang2021-04-061-2/+2
| | | | | | | | | | | | | | | 1. Follow GT7375P Programming Guide_Rev.0.6 to increase reset delay to 180ms. BUG=b:181711141 TEST=Build and boot lindar to OS. Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com> Change-Id: I82222ca094eead7e9e691857e128243cfe7c310e Reviewed-on: https://review.coreboot.org/c/coreboot/+/51739 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* Lindar/Lillipup: Enable Bayhub SD card reader power-saving modeKevin Chang2021-04-061-0/+1
| | | | | | | | | | | | | | Enable Bayhub SD card reader power-saving mode for Lindar and Lillipup. BUG=b:173676531 TEST=Boot to OS and test with SD card function. Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com> Change-Id: I923d6e1beacd007c0e501f39c1f434c3e1085b9e Reviewed-on: https://review.coreboot.org/c/coreboot/+/51623 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* soc/intel/tigerlake: Move TCSS code to intel/common/blockTim Wawrzynczak2021-03-282-2/+2
| | | | | | | | | | | | | The Type-C subsystem ("TCSS") IP block is similar between TGL and ADL. For pre-boot purposes, the limited amount of functionality required appears to be common between the two, therefore move the functionality to intel/common/block and rename from `early_tcss to `tcss` along the way. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I1c6bb9c7098691f0c828f9d5ab4bd522515ae966 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51753 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel: Rename and move MISCCFG_GPIO_PM_CONFIG_BITS definition to soc/gpio.hSubrata Banik2021-03-271-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Lists of changes: 1. Rename MISCCFG_ENABLE_GPIO_PM_CONFIG -> MISCCFG_GPIO_PM_CONFIG_BITS 2. Move MISCCFG_GPIO_PM_CONFIG_BITS definition from intelblock/gpio.h to soc/gpio.h. Refer to detailed description below to understand the motivation behind this change. An advanced GPIO PM capabilities has been introduced since CNP PCH, refer to 'include/intelblock/gpio.h' for detailed GPIO PM bit definitions. Now with TGP PCH, additional bits are defined in the MISCCFG register for GPIO PM control. This results in different SoCs supporting different number of bits. The bits defined in earlier platforms (CNL, CML, ICL) are present on TGL, JSL and ADL too. Hence, refactor the common GPIO code to keep the bit definitions in intelblock/gpio.h, but the definition of MISCCFG_GPIO_PM_CONFIG_BITS is moved to soc/gpio.h so that each SoC can provide this as per hardware support. TEST=On ADL, TGL and JSL platform. Without this CL : GPIO COMM 0 MISCCFG:0xC0 (Bit 6 and 7 enable) With this CL : GPIO COMM 0 MISCCFG: 0x00 (Bit 6 and 7 disable) Change-Id: Ie027cbd7b99b39752941384339a34f8995c10c94 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51767 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
* mb/google/volteer: Collis: Update SPD tableFrankChu2021-03-255-2/+77
| | | | | | | | | | | | | | | | | | | | Add memory table to "mem_list_variant.txt", and command to generate files: go run ./util/spd_tools/lp4x/gen_part_id.go src/soc/intel/tigerlake/spd src/mainboard/google/volteer/variants/collis/memory/ src/mainboard/google/volteer/variants/collis/memory/mem_list_variant.txt DRAM Part Name ID to assign MT53D512M64D4NW-046 WT:F 0 (0000) H9HCNNNCRMBLPR-NEE 0 (0000) MT53D1G64D4NW-046 WT:A 1 (0001) H9HCNNNFBMBLPR-NEE 2 (0010) BUG=b:182227204 TEST=emerge-volteer coreboot Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com> Change-Id: I773c65c0b6d5e868572530305ab8a61a0dd1532d Reviewed-on: https://review.coreboot.org/c/coreboot/+/51741 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
* mb/google/volteer/variants/drobit: Modify touchpad power sequenceWayne3 Wang2021-03-241-0/+2
| | | | | | | | | | | | | | | | | Modify power sequence of touchpad to meet the definition in the spec. BUG=b:178353432 BRANCH=firmware-volteer-13672.B TEST=build test firmware and verified by EE team. Change-Id: I8b8e383223d017223c36044efdf21738fe26d2ea Signed-off-by: Wayne3 Wang <wayne3_wang@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51514 Reviewed-by: Hao Chou <hao_chou@pegatron.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Zhuohao Lee <zhuohao@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/volteer/variants/delbin: Disable PmcUsb2PhySusPgEnableRavi Sarawadi2021-03-231-0/+2
| | | | | | | | | | | | | | | | eDP panel flicker during system idle state is observed. Disabling USB2 SUS well power gating can remove flicker symptom. Please refer to doc#634894 for more details. BUG=b:182323059 BRANCH=None TEST=Boot and confirm no display flicker. Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Change-Id: Icadf9c494fab82b219317c3ca3b04f633b543083 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51613 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
* mb/google/volteer/variants/eldrid: Include SPD for H4AAG165WB-BCWENick Vaccaro2021-03-223-1/+3
| | | | | | | | | | | | | | | | | Add SPD support to eldrid for DDR4 memory part H4AAG165WB-BCWE. Eldrid should use DRAM_ID strap ID 4 (0100) on SKUs populated with H4AAG165WB-BCWE DDR4 memory parts. BUG=b:181732562 TEST="FW_NAME=eldrid emerge-volteer coreboot" and verify it builds successfully. Change-Id: I38cfe3eb26b00563ce17df3a3ac2a0a846f2ae00 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51667 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/volteer/variants/copano: Configure specific DPTF parametershao_chou2021-03-221-0/+53
| | | | | | | | | | | | | | | Configure board specific DPTF parameters for copano BUG=b:176961219 BRANCH=firmware-volteer-13672.B TEST=build and verify by thermal team Change-Id: Ibce67f81503b84b58798bc198947e61907276ad3 Signed-off-by: Hao Chou <hao_chou@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51561 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/volteer/var/elemi: Config GPP_B7/GPP_B8 as NCWisley Chen2021-03-191-4/+0
| | | | | | | | | | | | | | | elemi does not use the GPP_B7/GPP_B8, so config to NC. Currently, there is no functional impact. BUG=b:182981460 TEST=emerge-volteer coreboot, boot into OS, and suspend/resume successfully. Change-Id: I7b491fd595b0e77e6dcce08e3172dbe592f63c37 Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51570 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
* sar: Fix semantics of `get_wifi_sar_cbfs_filename()`Furquan Shaikh2021-03-171-5/+3
| | | | | | | | | | | | | | | | | | | | Currently, if `get_wifi_sar_cbfs_filename()` returns NULL, then `get_wifi_sar_limits()` assumes that the default filename is used for CBFS SAR file. This prevents a board from supporting different models using the same firmware -- some which require SAR support and some which don't. This change updates the logic in `get_wifi_sar_limits()` to return early if filename is not provided by the mainboard. In order to maintain the same logic as before, current mainboards are updated to return WIFI_SAR_CBFS_DEFAULT_FILENAME instead of NULL in default case. Change-Id: I68b5bdd213767a3cd81fe41ace66540acd68e26a Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51485 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* drivers/wifi, mb/google: Drop config `WIFI_SAR_CBFS`Furquan Shaikh2021-03-171-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | Now that SAR support in VPD is deprecated in coreboot, there is no need for a separate Kconfig `WIFI_SAR_CBFS` as the SAR table is only supported as a CBFS file. This change drops the config `WIFI_SAR_CBFS` from drivers/wifi/generic/Kconfig and its selection in mb/google/.../Kconfig. wifi_sar_defaults.hex is added to CBFS only if CONFIG_WIFI_SAR_CBFS_FILEPATH is not empty because current mainboards do not provide a default SAR file in coreboot. Thus, CONFIG_WIFI_SAR_CBFS_FILEPATH is updated to have a default value of "". BUG=b:173465272 Cq-Depend: chromium:2757781 Change-Id: I0bb8f6e2511596e4503fe4d8c34439228ceaa3c7 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51484 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/volteer/variant/lindar: Disable SA GV for Samsung memory with ↵Kevin Chang2021-03-153-0/+15
| | | | | | | | | | | | | | | | | | | wrong date code MB Disable SA GV, because factory used Samsung memory with wrong date code. So we need to use board version to identify build MB phase to disable SA GV. Disable SA GV when board version equal one. BUG=b:179747696 BRANCH=firmware-volteer-13672.B TEST=Built and booted into OS. Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com> Change-Id: I51f4adcf0dd8dbf1cf39d8aec6e4303565551e5f Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51200 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
* mb/google/volteer/variants: Disable non-existing BT PCI interface and add BT ↵Cliff Huang2021-03-151-1/+2
| | | | | | | | | | | | | | | flag Remove the CNVi BT PCI config and add BT flag. There is no PCI host interface in this version of CNVi. TEST: BT is checked using 'lsusb -d 8087:0026' from OS to make sure BT is enumerated. Change-Id: Ic700021d7a09be63ffc2715f31992257e2e893af Signed-off-by: Cliff Huang <cliff.huang@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50898 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/volteer: Create collis variantFrankChu2021-03-158-0/+52
| | | | | | | | | | | | | | | | | | | Create the collis variant of the volteer reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:182227204 BRANCH=None TEST=util/abuild/abuild -p none -t google/volteer -x -a make sure the build includes GOOGLE_COLLIS Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com> Change-Id: Ibcf8b59b38d02517cea0a3ee474ff82fc0a2a958 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51387 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao@google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
* mb/google/volteer/variants/copano: Add gpio-keys ACPI node for PENHhao_chou2021-03-152-1/+14
| | | | | | | | | | | | | | | | Use gpio_keys driver to add ACPI node for pen eject event. Also setting gpio wake pin for wake events. BUG=b:175519097 BRANCH=firmware-volteer-13672.B TEST=build and verify on a Copano Change-Id: Id0a132aa398abde4983af123d00e355ac61839a8 Signed-off-by: hao_chou <hao_chou@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51249 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Wayne3 Wang <wayne3_wang@pegatron.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/volteer: Add WiFi SAR table support for Lindar/LillipupKevin Chang2021-03-152-0/+18
| | | | | | | | | | | | | | | | Lindar/Lillipup uses the WIFI_SAR_ID field in FW_CONFIG to pick which SAR table to load. BUG=b:178302811 BRANCH=volteer TEST=build and test no lindar/lillipup Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com> Change-Id: Ibe829062033ba8246b9d9550cdcdc360f5f67dd3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50872 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: YH Lin <yueherngl@google.com>
* mb/google/volteer/var/lindar: Add FW_CONFIG WIFI_SAR_ID fields in devicetreeKevin Chang2021-03-151-0/+6
| | | | | | | | | | | | | | | | Add FW_CONFIG WIFI_SAR_ID fields in devicetree. BUG=b:178302811 BRANCH=volteer TEST=build and test on lindar/lillipup Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com> Change-Id: I7ec37b80ffca6924f1f0952dcfbc43c378a70923 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51386 Reviewed-by: YH Lin <yueherngl@google.com> Reviewed-by: Zhuohao Lee <zhuohao@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* drivers/i2c: sx9310: Replace register map with descriptive namesGwendal Grignou2021-03-106-138/+53
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current driver is using chip registers map to configure the SAR sensor, which is opaque, especially when the datasheet is not published widely. Use more descriptive names, as defined in Linux kernel documentation at https://www.kernel.org/doc/Documentation/devicetree/bindings/iio/proximity/semtech%2Csx9310.yaml BUG=b:173341604 BRANCH=volteer TEST=Dump all tables, check semtech property: for i in $(find /sys/firmware/acpi/tables/ -type f) ; do f=$(basename $i); cat $i > /tmp/$f.dat ; iasl -d /tmp/$f.dat done In SSDT.dsl, we have: Package (0x06) { Package (0x02) { "semtech,cs0-ground", Zero }, Package (0x02) { "semtech,startup-sensor", Zero }, Package (0x02) { "semtech,proxraw-strength", Zero }, Package (0x02) { "semtech,avg-pos-strength", 0x0200 }, Package (0x02) { "semtech,combined-sensors", Package (0x03) { Zero, One, 0x02 } }, Package (0x02) { "semtech,resolution", "finest" } } Change-Id: I8d1c81b56eaeef1dbb0f73c1d74c3a20e8b2fd7b Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50210 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
* mb/google/volteer: Configure tcss port information for early tcss initBrandon Breitenstein2021-03-052-0/+59
| | | | | | | | | | | | | | | | | | | Implement the mainboard_tcss_get_port_info weak function so that the TCSS muxes can be properly configured to ensure mapping is correct in mux. This ensures that any devices that are connected during boot are not improperly configured by the Kernel. BUG=b:180426950 BRANCH=firmare-volteer-13672.B TEST= Verified that the SOC code that initialized TCSS muxes to disconnect mode is executing properly for all TCSS ports and verified that USB3 devices are no longer downgrading to USB2 speed if connected during boot. Change-Id: I59e5c5a7d2ab5ef5293abe6c59c3a585b25f7b75 Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51195 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
* mb/google/volteer: Fix FPMCU pwr/rst gpio handlingNick Vaccaro2021-03-0533-36/+395
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 1. No gpio control in bootblock 2. Power on and then deassert reset at the end of ramstage gpio 3. Disable power and assert reset when entering S5 On "reboot", the amount of time the power is disabled for is equivalent to the amount of time between triggering #3 and wrapping around to #2. This change affects the following volteer variants that include an FPMCU: 1. Drobit 2. Eldrid 3. Elemi 4. Halvor 5. Malefor 6. Terrador 7. Trondo 8. Voema 9. Volteer2 10. Voxel BUG=b:178094376 TEST=none Change-Id: Ib51815349cea299907c10d6c56c27bd239e499e7 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50828 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/volteer/variants/copano: Describe USB ports in devicetreehao_chou2021-03-041-10/+13
| | | | | | | | | | | | | | | | | Modify USB port to match schematics. And assigned USB2 port to type-c use. BUG=b:177481079 BRANCH=firmware-volteer-13672.B TEST=emerge-volteer coreboot Change-Id: I25412d16df8ad809c05635022c11bd8882d002c5 Signed-off-by: hao_chou <hao_chou@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49980 Reviewed-by: Wayne3 Wang <wayne3_wang@pegatron.corp-partner.google.com> Reviewed-by: Zhuohao Lee <zhuohao@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel: Retype `CnviBtAudioOffload` devicetree optionAngel Pons2021-03-031-1/+1
| | | | | | | | | | | | | | | The `FORCE_ENABLE` and `FORCE_DISABLE` names do not match what FSP UPDs say, and can be confused with the `PchHdaTestPowerClockGating` UPD. Replace the enum with a bool, and drop the confusing names. Note that the enum for Ice Lake was incorrect, but no mainboards used the option. Change-Id: I2c9b4c6a2f210ffca946ca196299fa672a06ccc7 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51154 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/*/*: Don't select PCIEXP_HOTPLUGArthur Heymans2021-03-031-1/+3
| | | | | | | | | | | PCIEXP_HOTPLUG has a prompt and as such is not supposed to be forced. Just change the default value to 'y'. Change-Id: Ie4248700f5ab5168bff551b740d347713273763c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51151 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* vboot: update GBB flags to use altfw terminologyJoel Kitching2021-02-271-1/+1
| | | | | | | | | | | | | | | | As per CL:2641346, update GBB flag names: GBB_FLAG_FORCE_DEV_BOOT_LEGACY -> GBB_FLAG_FORCE_DEV_BOOT_ALTFW GBB_FLAG_DEFAULT_DEV_BOOT_LEGACY -> GBB_FLAG_DEFAULT_DEV_BOOT_ALTFW BUG=b:179458327 TEST=make clean && make test-abuild BRANCH=none Signed-off-by: Joel Kitching <kitching@google.com> Change-Id: I0ac5c9fde5a175f8844e9006bb18f792923f4f6d Reviewed-on: https://review.coreboot.org/c/coreboot/+/50906 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* mb/google/volteer/var/elemi: Configure IRQ as level triggered for elan_tsWisley Chen2021-02-261-1/+1
| | | | | | | | | | | | | | Follow elan's suggestion to configure IRQ as level trigger to prevent touchscreen lost BUG=b:180778934 BRANCH=firmware-volteer-13672.B TEST=emerge-volteer coreboot Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Change-Id: I3aca0ad20791c989dec9e70d69d637b28c9cc043 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50417 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/volteer: add variant_ramstage_init()Nick Vaccaro2021-02-262-0/+10
| | | | | | | | | | | | | | Add a weak variant routine to allow variants to perform any needed initialization in ramstage. BUG=b:178094376 TEST=none Change-Id: I65dc1cdf15b68d9f2239e02fcb4b2c902d749378 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50827 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/volteer: Fix eldrid DPTF's passive and critical policiesTim Wawrzynczak2021-02-251-4/+6
| | | | | | | | | | | | | | | | | | | | | Because the entries were formatted differently to the baseboard, the devicetree overrides didn't work as intended, and all 5 entries from the baseboard were included, and then the overrides were applied, but the baseboard's entries were kept, so there were duplicate ACPI entries, which causes errors when parsing the table. Fixes: 5f30ae3714d ("mb/google/volteer: update thermal table for Eldrid") BUG=b:181034399 TEST=compile, verify static.c is correct now Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I32fe2eae591ed4d3c08378977c463327f7ee1100 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51044 Reviewed-by: YH Lin <yueherngl@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nick Chen <nick_xr_chen@wistron.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/volteer/variants/drobit: Update DPTF parametersWayne3 Wang2021-02-251-2/+54
| | | | | | | | | | | | | | | | | | | Update the first version DPTF parameters. The TDP is down to 13w for acoustic concern. BUG=b:177777472 BRANCH=firmware-volteer-13672.B TEST=build test image and verified by thermal team. Change-Id: I36f016530a61e3660938ce8d2948bb3b0f275d88 Signed-off-by: Wayne3 Wang <Wayne3_Wang@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51030 Reviewed-by: Paul Yang <paul.f.yang@intel.corp-partner.google.com> Reviewed-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Wayne3 Wang <wayne3_wang@pegatron.corp-partner.google.com> Reviewed-by: Ariel Chang <ariel_chang@pegatron.corp-partner.google.com> Reviewed-by: Zhuohao Lee <zhuohao@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/volteer: Correct AT24 NVM address sizeDaniel Kang2021-02-121-1/+1
| | | | | | | | | | | | | | | | | | | | | | Currently, the address size field of AT24 NVM is incorrect, and Linux v5.4 kernel logs the message below: at24 i2c-PRP0001:02: Bad "address-width" property: 13 The valid size of the AT24 NVM is 16 bits so modify the value from 0x0D to 0x10. BUG=b:177655681 BRANCH=none TEST=Boot volteer and check the kernel log and see "Bad address-width" error message is not shown. Signed-off-by: Daniel Kang <daniel.h.kang@intel.com> Change-Id: Ice6c3eac1e023b981217e1d7dc06587fc46b1a02 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49633 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Bingbu Cao <bingbu.cao@linux.intel.com>
* mb/google/volteer/variants: Remove unneeded whitespace before tabElyes HAOUAS2021-02-111-1/+1
| | | | | | | | | Change-Id: I4c991e6119f14d949a2e103024132d70674f29a1 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50431 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* mb/google: order matters in mem_parts_used.txtPaul Fagerburg2021-02-102-1/+19
| | | | | | | | | | | | | | | | | | | | | * Add comments to mem_parts_used.txt to point out that the order of the entries matters when assigning IDs, so always add a new part to the end of the file. * Update existing mem_parts_used.txt to add the same comment. * No updates to Zork variants, because they use an optional ID, so the order actually doesn't matter there. BUG=b:175898902 TEST=create a new variant of dalboz, trembyle, volteer, waddledee, or waddledoo, and observe that mem_parts_used.txt has the new verbiage. Signed-off-by: Paul Fagerburg <pfagerburg@google.com> Change-Id: Iffbd8e69a89b1b7c810c5d25c7a6148d459d8b02 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50449 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Rob Barnes <robbarnes@google.com>
* mb/google/volteer/var/voxel: Add settings for noise mitgationSheng-Liang Pan2021-02-101-0/+11
| | | | | | | | | | | | | | | Enable acoustic noise mitgation for volteer platforms. BUG=b:179328166 BRANCH=none TEST= Measure the change in noise level by changing the values in devicetree. Signed-off-by: Pan Sheng-Liang <sheng-liang.pan@quanta.corp-partner.google.com> Change-Id: I279a85c7741094bb7ddf0c1fde74b31189b12171 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50293 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
* mb/google/volteer: Enable external bypass, clkgate & phygateShreesh Chhabbi2021-02-101-0/+9
| | | | | | | | | | | | | | | This change sets the soc config options for external_bypass, external_clk_gate and external_phy_gate. BUG=b:177821896 TEST=Build coreboot for volteer Signed-off-by: Shreesh Chhabbi <shreesh.chhabbi@intel.corp-partner.google.com> Change-Id: I9e5218cda79d7453bf830639ccea4e5be019b070 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50290 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/volteer/var/voxel: Add gpio-keys ACPI node for PENHSheng-Liang Pan2021-02-072-2/+15
| | | | | | | | | | | | | | Use gpio_keys driver to add ACPI node for pen eject event. Also setting gpio wake pin for wake events. BUG=b:176213181 TEST=emerge-volteer coreboot chromeos-bootimage Signed-off-by: Pan Sheng-Liang <sheng-liang.pan@quanta.corp-partner.google.com> Change-Id: If0959df5d0f069048777df81b0d4092ea90314eb Reviewed-on: https://review.coreboot.org/c/coreboot/+/49967 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/volteer: update thermal table for EldridNick Chen2021-02-041-11/+13
| | | | | | | | | | | | | | | | | 1. Add pl4 value 2. Change policies passive with sensor 0 and 1 3. Change granularity value with pl1 and pl2 BUG=b:178768749 TEST=make buildall Signed-off-by: Nick Chen <nick_xr_chen@wistron.corp-partner.google.com> Change-Id: I2f1fe9a6de4dbb587b79cb8758c5458a3ae5d768 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50111 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mainboards: Remove default CHROMEOS=yKyösti Mälkki2021-02-041-2/+0
| | | | | | | | | | | | | Even the boards with MAINBOARD_HAS_CHROMEOS need to be build-tested with CHROMEOS=n. Change-Id: I16fcf62a23dae1b21c77cee275c867f9c1de893b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50118 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
* mb/google/volteer/variants/drobit: Configure USB2 port for Type-CWayne3_Wang2021-02-031-4/+7
| | | | | | | | | | | | | | | | | | USB2 ports assigned to type-C connector need to be configured properly by the USB2_PORT_TYPE_C. and also modify the description of USB port. BUG=b:177480902 BRANCH=firmware-volteer-13672.B TEST=emerge-volteer coreboot chromeos-bootimage build Pass And check the typeC port function is normal by manual. Signed-off-by: Wayne3_Wang <Wayne3_Wang@pegatron.corp-partner.google.com> Change-Id: I9e962f8cd76e1986700821168594c50bc21553e9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50217 Reviewed-by: Wayne3 Wang <wayne3_wang@pegatron.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/volteer/var/voema: Enable EEPROM for OV2740David Wu2021-02-031-0/+66
| | | | | | | | | | | | | | Add ACPI entries for AT24 NVM device. BUG=b:169551066 TEST=Build and run for basic camera functions. Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: Ib8fb684166649f78713050d62445bf47189b06ab Reviewed-on: https://review.coreboot.org/c/coreboot/+/50216 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jim Lai <jim.lai@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/volteer/variant/copano: support regular/numpad touchpadZhuohao Lee2021-02-032-2/+18
| | | | | | | | | | | | | | | | | Define the 25th bit of the fw_config for the regular touchpad and numpad touchpad selection. BUG=b:174027837 BRANCH=firmware-volteer-13672.B TEST=build pass Change-Id: Ic5d61f19fd385600cfdcdd045dab1e61b06e4663 Signed-off-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50129 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Marco Chen <marcochen@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/volteer/variants/drobit: Modify touchpad I2C sequenceWayne3_Wang2021-02-031-0/+6
| | | | | | | | | | | | | | | | | | | Modify touchpad I2C sequence to meet requirement. BUG=b:178512111 BRANCH=firmware-volteer-13672.B TEST=emerge-volteer coreboot chromeos-bootimage build Pass And check the touchpad I2C5 sequence by EE. Signed-off-by: Wayne3_Wang <Wayne3_Wang@pegatron.corp-partner.google.com> Change-Id: Iebbeeec51b802c318ac014dcdd2603b600d931a9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49958 Reviewed-by: Zhuohao Lee <zhuohao@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Hao Chou <hao_chou@pegatron.corp-partner.google.com> Reviewed-by: Wayne3 Wang <wayne3_wang@pegatron.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/volteer/variants/drobit: Add TBT PCIE rp setting for drobitWayne3_Wang2021-02-031-0/+8
| | | | | | | | | | | | | | | | | | | | | Add the TBT PCIE rp setting to on and also fixes system hang in recovery screen after selected "Power off" item problem. BUG=b:177963941 BRANCH=firmware-volteer-13672.B TEST=emerge-volteer coreboot chromeos-bootimage build Pass And check the system can power off normally in recovery page Cq-Depend: chrome-internal:3581043 Signed-off-by: Wayne3_Wang <Wayne3_Wang@pegatron.corp-partner.google.com> Change-Id: Ic0a4756b4af839ea0a23febb991bd71af7733dcc Reviewed-on: https://review.coreboot.org/c/coreboot/+/50103 Reviewed-by: Wayne3 Wang <wayne3_wang@pegatron.corp-partner.google.com> Reviewed-by: Ariel Chang <ariel_chang@pegatron.corp-partner.google.com> Reviewed-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/volteer: Select SOC_INTEL_CSE_LITE_SKU for volteer baseboardFurquan Shaikh2021-02-012-17/+2
| | | | | | | | | | | | | | This change moves the selection of SOC_INTEL_CSE_LITE_SKU into Kconfig under BOARD_GOOGLE_BASEBOARD_VOLTEER instead of requiring each individual board to select it. TEST=Verified that timeless build does not result in any changes. Change-Id: I2d94931fdc3077794bed5cc51708b5a5d9e64972 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50096 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/volteer: Drop boldar variantFurquan Shaikh2021-02-018-44/+0
| | | | | | | | | | This variant never really got used and can be deprecated. Change-Id: I5d59460c90266ba5f9c3bdb951f53a37ffae9e03 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50095 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/volteer: Add GL9755 support to DrobitWayne3_Wang2021-01-281-0/+1
| | | | | | | | | | | | | | | | | Add the GL9755 support to drobit and also fixes the S0ix can't into C3~C9 problem BUG=b:174348200 BRANCH=firmware-volteer-13672.B TEST=emerge-volteer coreboot Signed-off-by: Wayne3_Wang <Wayne3_Wang@pegatron.corp-partner.google.com> Change-Id: I52df6b2cdebfaf8a5eb010c4af1a2cf3d918f5e5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49921 Reviewed-by: Wayne3 Wang <wayne3_wang@pegatron.corp-partner.google.com> Reviewed-by: Paul2 Huang <paul2_huang@pegatron.corp-partner.google.com> Reviewed-by: Zhuohao Lee <zhuohao@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* ACPI: Move include for <vc/google/chromeos.asl>Kyösti Mälkki2021-01-281-3/+0
| | | | | | | | Change-Id: I4356a8bda71e84afe8c348d366479c5006bf2459 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49796 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* ACPI: Add top-level ASLKyösti Mälkki2021-01-271-0/+1
| | | | | | | | | | | | | | | | | | | Objects that are created with acpigen need to be declared with External () for the generation of dsdt.asl to pass iasl without errors. There are some objects that are common to all platforms, and some that should be declared only conditionally. Having a top-level ASL helps to achieve this. Change-Id: Ibaf1ab9941b82f99e5fa857c0c7e4b6192c74330 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49794 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-26 14:19:46 +0000