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* mb/google/zork/vilboz: Enable ALC1015 AMP driverFrank Wu2021-03-261-0/+3
| | | | | | | | | | | | | | | | Enable ALC1015 driver for audio support in vilboz BUG=b:177971830 BRANCH=firmware-zork-13434.B TEST=emerge-zork coreboot chromeos-bootimage, then verify with ALC1015 AMP Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: If0abfd6570579fe637a7bef31de2f01d58f3bdf6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51053 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
* mb/google/zork/var/vilboz: Add Mainboard Type for VCORE ICJohn Su2021-03-101-0/+8
| | | | | | | | | | | | | | | To define Mainboard Type config, use the fw_config bit[26]. Check MB Type to modify SDLE settings for different VCORE IC. BUG=b:177193131 BRANCH=zork Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Change-Id: If153c0a3e641ae32ef89737925bd9f62dfb71f3d Reviewed-on: https://review.coreboot.org/c/coreboot/+/49683 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Kangheui Won <khwon@chromium.org>
* mb/google/zork/var/vilboz: Add WiFi SAR for VilbozFrank Wu2021-01-151-3/+8
| | | | | | | | | | | | | | | | | | | The fw_config field SPI_SPEED is not used for zork devices. To define SAR config, use the fw_config bit[23..26]. Then vilboz can loaded different WiFi SAR table for different SKUs. BUG=b:176858126, b:176751675, b:176538384 BRANCH=zork TEST=emerge-zork coreboot chromeos-bootimage, then verify that tables are in CBFS and loaded by iwlwifi driver. Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: I5ba98799e697010997b515ee88420d0ac14ca7ec Reviewed-on: https://review.coreboot.org/c/coreboot/+/49296 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
* mb/google/zork/var/vilboz: Fix FW_CONFIG_SHIFT_WWAN valueJohn Su2021-01-121-1/+1
| | | | | | | | | | | | | | | | | | The FW config takes 2 bits for USE_FAN[27,28]. So FW_CONFIG_SHIFT_WWAN value should be 29. BUG=b:174121847 BRANCH=zork TEST=build vilboz Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Change-Id: Ica6d04f9c48aa0800189283608bf57416ac75cf7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49236 Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/zork/var/vilboz: Add enable acp_i2s_use_external_48mhz_osc flagJohn Su2020-12-221-0/+8
| | | | | | | | | | | | | | | | Add enable acp_i2s_use_external_48mhz_osc flag and then WWAN sku will use external clock source at next build. BUG=b:174121847 BRANCH=zork TEST=build vilboz and check MISC_CLK_CNTL1. Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Change-Id: Ida747938373f648524b1e7f34bc69e372a69c4f9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48556 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/zork: Init fingerprint GPIOs for boot vs resumeMartin Roth2020-11-161-0/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a function that initializes GPIOs based on the sleep type that the system is coming back from. This allows initialization of the fingerprint GPIOs which need to be handled differently between wake from S3 and boot from S5. On initial boot, the state of the FP sensor could be either enabled or disabled. Because of this, on boot, we power off the sensor for >200ms, to reset its state, then power it back on. In suspend/resume, the fingerprint sensor should remain powered the entire time. If fingerprint is disabled on the trembyle-based board, set the pins to no-connect. Dalboz doesn't have fingerprint and the GPIOS are configured differently due to the FT5 chip having fewer GPIOS than FP5, so nothing needs to be initialized there. There were also a couple of trivial comment clean ups regarding the FPMCU GPIOS. BUG=b:171837716 TEST=Boot & Check GPIO states. BRANCH=Zork Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I16a2e621145782e0a908bb3e49478586c09a0e0a Reviewed-on: https://review.coreboot.org/c/coreboot/+/47308 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
* fw_config: Convert fw_config to a 64-bit fieldTim Wawrzynczak2020-10-301-4/+4
| | | | | | | | | | | | | | | | | We all knew this was coming, 32 bits is never enough. Doing this early so that it doesn't affect too much code yet. Take care of every usage of fw_config throughout the codebase so the conversion is all done at once. BUG=b:169668368 TEST=Hacked up this code to OR 0x1_000_0000 with CBI-sourced FW_CONFIG and verify the console print contained that bit. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I6f2065d347eafa0ef7b346caeabdc3b626402092 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45939 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/zork: Update style of check on cbi return valuesEric Lai2020-10-261-4/+4
| | | | | | | | | | | | | | Since google_chromeec_cbi_get_board_version and google_chromeec_cbi_get_fw_config both call cbi_get_unit32 and return 0 as success, non-zero as failure. Let's add more readability for the false condition. BUG=None TEST=check with empty CBI value Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ia49ac1ee35302f8f6afe8c0eb8e13afdf36c5b2b Reviewed-on: https://review.coreboot.org/c/coreboot/+/46566 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/zork: Add helper function to read DB ID bits in FW_CONFIGBhanu Prakash Maiya2020-08-131-0/+5
| | | | | | | | | | | | | | | | Add helper function variant_get_daughterboard_id() to read daughterboard id bits (0-3) in firmware configuration table in CBI. BRANCH=none BUG=b:162344105,b:152817444 TEST=Check if daughterboard id bits (0-3) can be read from FW_CONFIG. Signed-off-by: Bhanu Prakash Maiya <bhanumaiya@google.com> Change-Id: Ia3c882439bfbe6da28be2df0ec0c976d5c142677 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44424 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/zork: Remove validity checks for FW_CONFIG in CBIBhanu Prakash Maiya2020-08-131-26/+0
| | | | | | | | | | | | | | | | | | | After confirming that all zork variants and phases have valid FW_CONFIG value in CBI, this patch is dropping FW_CONFIG validity checks like VARIANT_HAS_FW_CONFIG and VARIANT_BOARD_VER_FW_CONFIG_VALID in Kconfig and will also remove associated helper functions. BRANCH=none BUG=b:162344105,b:152817444 TEST=Check if FW_CONFIG bits can be read in coreboot and FW_CONIFG helper function do not return 0 if board has a valid FW_CONFIG in CBI. Signed-off-by: Bhanu Prakash Maiya <bhanumaiya@google.com> Change-Id: I633dc7c500ef8759f3fffb0db6b76d96257c3c9a Reviewed-on: https://review.coreboot.org/c/coreboot/+/44422 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
* mb/google/zork: Add kconfigs to check schematic version 3.6Josie Nordrum2020-08-061-0/+25
| | | | | | | | | | | | | | | | Added VARIANT_SUPPORTS_PRE_V3_6_SCHEMATICS and VARIANT_MIN_BOARD_ID_V3_6_SCHEMATICS. Added helper functions to check if variant uses v3.6 and if variant uses CODEC GPI. BUG=b:161938476 BRANCH=None TEST=None Change-Id: If86e1ea3c02db354c7b410f1bbc1daacb483cc51 Signed-off-by: Josie Nordrum <josienordrum@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44156 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/zork: Add helpers for v3 schematics and wifi power enableFurquan Shaikh2020-07-081-0/+32
| | | | | | | | | | | | | | | | | | | | | | | | | This change adds following two helper functions: 1. variant_uses_v3_schematics() - Check whether the variant is using v3 version of schematics. 2. variant_has_active_low_wifi_power() - Check whether the variant is using active low power enable for WiFi. In addition to this, Kconfig options are reorganized to add two new configs - VARIANT_SUPPORTS_PRE_V3_SCHEMATICS and VARIANT_SUPPORTS_WIFI_POWER_ACTIVE_HIGH. This allows the helper functions to return `true` early without checking for board version. Eventually, when a variant decides to drop support for pre-v3 schematics, it can be dropped from selecting VARIANT_SUPPORTS_PRE_V3_SCHEMATICS. Similarly, when the variant decides to drop support for active high power enable for WiFi, it can be dropped from selecting VARIANT_SUPPORTS_WIFI_POWER_ACTIVE_HIGH. Change-Id: I62851299e8dd7929a8e1e9a287389abd71c7706c Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43224 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/zork: Add Picasso based Zork mainboard and variantsRaul E Rangel2020-05-271-0/+115
This is a copy of the mb/google/zork directory from the chromiumos coreboot-zork branch. This was from commit 29308ac8606. See https://chromium.googlesource.com/chromiumos/third_party/coreboot/+/29308ac8606/src/mainboard/google/zork Changes: * Minor changes to make the board build. * Add bootblock.c. * Modify romstage.c * Removed the FSP_X configs from zork/Kconfig since they should be set in picasso/Kconfig. picasso/Kconfig doesn't currently define the binaries since they haven't been published. To get a working build a custom config that sets FSP_X_FILE is required. BUG=b:157140753 TEST=Build trembyle and boot to OS Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I3933fa54e3f603985a0818852a1c77d8e248484f Reviewed-on: https://review.coreboot.org/c/coreboot/+/41581 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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