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* mb/google/zork/var/shuboz: Add SPD ID for MT40A512M16TB-062E:RKane Chen2022-01-283-0/+3
| | | | | | | | | | | | | | | | | | | | | | | Add supported memory parts in "mem_parts_used.txt" and generate the SPD ID 0x04 for the parts. Shuboz memory table as follow: value Vendor Part number 0000 MICRON MT40A512M16TB-062E:J 0001 HYNIX H5AN8G6NCJR-XNC 0010 MICRON MT40A1G16KD-062E:E 0011 SAMSUNG K4AAG165WA-BCWE 0100 MICRON MT40A512M16TB-062E:R BUG=b:216571906 BRANCH=zork TEST=emerge-zork coreboot Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com> Change-Id: Ib0100456457adabed6fd6615e0873de2cf9acb98 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61373 Reviewed-by: Kangheui Won <khwon@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/zork: use full path of SoC's chip.hFelix Held2021-12-201-1/+1
| | | | | | | | Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I50d8c45e711dc62afe6f80e0f66422bcc9924dfd Reviewed-on: https://review.coreboot.org/c/coreboot/+/60202 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* mb/google/zork/var/shuboz: Add fw_config probe for ALC5682-VD & VSKane Chen2021-12-131-0/+86
| | | | | | | | | | | | | | | | | | | | | ALC5682-VD/ALC5682I-VS load different kernel driver by different hid name. Update hid name and machine_dev depending on the AUDIO_CODEC_SOURCE field of fw_config. Define FW_CONFIG bits 36 - 37 (SSFC bits 4 - 5) for codec selection. ALC5682-VD: _HID = "10EC5682" ALC5682I-VS: _HID = "RTL5682" BUG=b:198689479 BRANCH=zork TEST=ALC5682-VD/ALC5682I-VS audio codec can work Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com> Change-Id: I0c78aa166010ffa4d0cacc8a11d418d5a6906749 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59558 Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google: Update comments in mem_parts_used.txt to match new templatesReka Norman2021-09-231-2/+2
| | | | | | | | | | | BUG=b:191776301 TEST=None Signed-off-by: Reka Norman <rekanorman@google.com> Change-Id: Iafcbb3ce33cd2299ff98b54b9200f3e70929fb1f Reviewed-on: https://review.coreboot.org/c/coreboot/+/57821 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/zork: Migrate zork to use SPD files under spd/Reka Norman2021-09-233-7/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | SPD files are being moved from the soc and mainboard directories to a centralised spd/ directory. This change migrates all zork variants to use this new location. The contents of the new SPDs are identical, only their file paths have changed. The variant Makefile.inc and dram_id.generated.txt files were generated using the part_id_gen tool. E.g. for dalboz: util/spd_tools/bin/part_id_gen \ PCO \ ddr4 \ src/mainboard/google/zork/variants/dalboz/spd \ src/mainboard/google/zork/variants/dalboz/spd/mem_parts_used.txt BUG=b:191776301 TEST=Check that each variant's coreboot.rom is the same with and without this change. Built using: abuild -p none -t google/zork -a -x --timeless Signed-off-by: Reka Norman <rekanorman@google.com> Change-Id: I305a24f9345bab28ff35e317b6e7fd7efba22413 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57772 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/zork/var/shuboz: adjust telemetry settingsKane Chen2021-07-071-4/+4
| | | | | | | | | | | | | | | | | | | | | | According to stardust test tracking report to adjust telemetry setting. VDD Slope : 30595 -> 30400 VDD Offset: 77 -> 317 SOC Slope : 24063 -> 23789 SOC Offset: 105 -> 94 BUG=b:190338440 BRANCH=zork TEST=emerge-zork coreboot Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com> Change-Id: Id997f9cd220d704c5b0882c257a596fb3d2485ef Reviewed-on: https://review.coreboot.org/c/coreboot/+/56077 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Daniel Kurtz <djkurtz@google.com>
* soc/amd/picasso: introduce and use devicetree aliases for I2C2&I2C3Felix Held2021-06-161-1/+1
| | | | | | | | Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I06102f4fcc3bf9de332c71a52c632241b95cde19 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55543 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* mb/google/zork/var/shuboz: update USB OC pin mappingKane Chen2021-05-132-0/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | modify USB OC pin setting for Shuboz/Jelboz/Jelboz360 Shuboz/Jelboz: usb_port_overcurrent_pin[0] = "USB_OC_PIN_0" # USB C0 usb_port_overcurrent_pin[1] = "USB_OC_PIN_0" # USB A0 usb_port_overcurrent_pin[2] = "USB_OC_PIN_1" # USB A1 usb_port_overcurrent_pin[3] = "USB_OC_PIN_1" # USB C1 Jelboz360: usb_port_overcurrent_pin[0] = "USB_OC_PIN_0" # USB C0 usb_port_overcurrent_pin[1] = "USB_OC_PIN_0" # USB A0 usb_port_overcurrent_pin[2] = "USB_OC_NONE" # NONE usb_port_overcurrent_pin[3] = "USB_OC_PIN_1" # USB C1 BUG=b:182879559 BRANCH=zork TEST=emerge-zork coreboot, validate the OC mapping. Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com> Change-Id: Icc1fa090109e6be54e2a5f49e364f5502f53aca2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51523 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
* mb/google/zork: Configure IRQs as level triggered for ELAN touchpadVictor Ding2021-04-161-1/+1
| | | | | | | | | | | | | | | | | | Based on the datasheet provided by ELAN, the /INT pin is "low active" and "indicates touchpad likes to send data to system(host) when low". The signal is level-triggered. BRANCH=zork BUG=b:172846122 TEST=cros build-ap -b zork Signed-off-by: Victor Ding <victording@google.com> Change-Id: I1f2182aaf483932304591ab14592f35214ea6efd Reviewed-on: https://review.coreboot.org/c/coreboot/+/52366 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Kangheui Won <khwon@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/zork: Move max98357a out of baseboardEric Lai2021-03-221-0/+7
| | | | | | | | | | | | | | Not all of dalboz variants support the this amp. Thus, move out of baseboard. BUG=b:182815488 TEST=builds Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: If708574f5fb18dd3b4f2ef978529a16a40d5dc0c Reviewed-on: https://review.coreboot.org/c/coreboot/+/51511 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-hsuan Hsu <yuhsuan@google.com> Reviewed-by: Kangheui Won <khwon@chromium.org>
* mb/google/zork/var/shuboz: adjust telemetry settingsKane Chen2021-03-181-4/+4
| | | | | | | | | | | | | | | | | | | | According to stardust test tracking report to adjust telemetry setting. VDD Slope : 30518 -> 30595 VDD Offset: 435 -> 77 SOC Slope : 22965 -> 24063 SOC Offset: 165 -> 105 BUG=b:182399760 BRANCH=zork TEST=emerge-zork coreboot Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com> Change-Id: Ie7e6af77bdaad6cc964ac206a69ccb854aae869f Reviewed-on: https://review.coreboot.org/c/coreboot/+/51517 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
* mb/google/zork/var/shuboz: support regular/numpad touchpadKane Chen2021-03-101-7/+19
| | | | | | | | | | | | | | | | | | Define the 26th bit of the fw_config for the regular touchpad and numpad touchpad selection. REGULAR_TOUCHPAD: 1 NUMPAD_TOUCHPAD: 0 BUG=b:174964012 BRANCH=zork TEST=build pass Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com> Change-Id: Ie2055d6bb45a64bc0e59209cecc0f8a31c0f3718 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51278 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
* mb/google/zork/var/shuboz: adjust I2C2 data hold time for TPKane Chen2021-03-101-0/+1
| | | | | | | | | | | | | | | Add ".data_hold_time_ns" to follow I2C specification. The adjusted result aobut 0.315us(more than 0.3us) BUG=b:181091107 BRANCH=zork TEST=emerge-zork coreboot chromeos-bootimage Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com> Change-Id: Id92fadcb54b9722709e32ced1f0be001b8c97975 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51361 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
* mb/google/zork/var/shuboz: Decrease I2C3 CLK below 400 kHzKane Chen2021-03-011-2/+2
| | | | | | | | | | | | | | | | | | | | | | Modify I2C3 setting to follow I2C specification (lower than 400kHz). Original setting: .rise_time_ns = 184 .fall_time_ns = 42 Change to: .rise_time_ns = 110 .fall_time_ns = 34 BUG=b:181091107 BRANCH=zork TEST=emerge-zork coreboot chromeos-bootimage Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com> Change-Id: Ibdbb9a7dde524bdbde4789ee7ea005646080d97a Reviewed-on: https://review.coreboot.org/c/coreboot/+/51052 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
* mb/google/zork/var/shuboz: Adjust GPIO settingsKane Chen2021-02-231-0/+2
| | | | | | | | | | | | | | 1. GPIO_4 to NC BUG=b:179333669 BRANCH=zork TEST=emerge-zork coreboot Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com> Change-Id: I4342b2beb7fc755bee47ee4fad0023d7a6592c4b Reviewed-on: https://review.coreboot.org/c/coreboot/+/50277 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/zork/var/shuboz: Adjust touchscreen settingsKane Chen2021-02-101-1/+2
| | | | | | | | | | | | | | | | Modify GPIO_140 delay time and add "disable_gpio_export_in_crs" to meet touchscreen controller power on sequence. BUG=b:174442484 BRANCH=master TEST=emerge-zork coreboot chromeos-bootimage Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com> Change-Id: I36a7055b7be0963479f8a0f4dc49c92bc8fbdc9d Reviewed-on: https://review.coreboot.org/c/coreboot/+/50228 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/zork/var/shuboz: Modify touchpad setting for JelbozKane Chen2021-02-101-7/+8
| | | | | | | | | | | | | | | | Since Jelboz support number pad, due to one single coreboot for both Jelboz and Shuboz, modify "overridetree.cb" setting to number pad support for Jelboz. BUG=b:174964012 BRANCH=master TEST=emerge-zork coreboot chromeos-bootimage Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com> Change-Id: Ie0219419834b34b6eac589f28d3604f5f1b65679 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49742 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
* src: Remove unused <boardid.h>Elyes HAOUAS2021-02-031-1/+0
| | | | | | | | Change-Id: I960870fabde1dacfe52a8a35c253b0bd097d3e10 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50183 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
* mb/google/zork/var/shuboz: update STAPM add telemetry settingKane Chen2021-01-151-1/+6
| | | | | | | | | | | | | | | | | | | | 1. Modify STAPM time constant 2500 to 1400. 2. Add telemetry setting: VDD Slope : 30518 VDD Offset: 435 SOC Slope : 22965 SOC Offset: 165 BUG=b:177399751 BRANCH=master TEST=emerge-zork coreboot chromeos-bootimage Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com> Change-Id: I251029389c10ee0f17f368b1c00ac666d372fc3c Reviewed-on: https://review.coreboot.org/c/coreboot/+/49386 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
* mb/google/zork: Modify variant to Shuboz supportKane Chen2021-01-073-1/+58
| | | | | | | | | | | | | | | 1. Add ELAN touchscreen/touchpad to overridetree.cb 2. Follow Dalboz setting to add variant.c BUG=b:174528384 BRANCH=zork TEST=emerge-zork coreboot Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com> Change-Id: Ic3193ca7957251841e75a7e5c7a16fc5047919fb Reviewed-on: https://review.coreboot.org/c/coreboot/+/48001 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/zork: Add GPIO to Shuboz supportKane Chen2020-12-172-0/+24
| | | | | | | | | | | | | | | | 1. AGPIO5 to NC 2. EGPIO141 to NC 3. EGPIO144 to NC BUG=b:174528384 BRANCH=zork TEST=emerge-zork coreboot Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com> Change-Id: I51f291476e01982e1a3f92cd1b338a528434112d Reviewed-on: https://review.coreboot.org/c/coreboot/+/48002 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/zork: Update SPD table for ShubozKane Chen2020-12-023-2/+13
| | | | | | | | | | | | | | | | | | | | | | | | | Add memory table to "mem_parts_used.txt", and command to generate files: go build gen_part_id.go ./gen_part_id ../../../src/mainboard/google/zork/spd ../../../src/mainboard/google/zork/variants/shuboz/spd/ ../../../src/mainboard/google/zork/variants/shuboz/spd/mem_parts_used.txt Shuboz memory table as follow: value Vendor Part number 0x00 MICRON MT40A512M16TB-062E:J 0x01 HYNIX H5AN8G6NCJR-XNC 0x02 MICRON MT40A1G16KD-062E:E 0x03 SAMSUNG K4AAG165WA-BCWE BUG=b:174528384 BRANCH=zork TEST=emerge-zork coreboot Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com> Change-Id: I5f5f875daab58343f1cc8a9327ea128ba5e1f050 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47902 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
* mb/google/zork: Create Shuboz variantKane Chen2020-11-1011-0/+78
Create the shuboz variant of the zork reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.2.0). BUG=b:172021093 BRANCH=none TEST=emerge-zork coreboot Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com> Change-Id: I3f62625f8cbde1c9adf8ab335edeb9e811e32679 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47152 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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