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* soc/amd/common: Move Agesa related headersRichard Spiegel2017-12-128-9/+9
| | | | | | | | | | | | | | Move AGESA related headers in soc/amd/common to soc/amd/common/block/include/amdblocks. BUG=b:69262110 TEST=Build with no error gardenia and kahlee (no code change, headers moved). Change-Id: I5d3064625ddf8caaf370aabaf93165c6817f1ca0 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/22772 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
* mb/google/poppy/variants/nami: Implement variant_memory_paramsFurquan Shaikh2017-12-122-0/+52
| | | | | | | | | | | | | | | This change provides implementation of variant_memory_params for nami. Since it uses DDR4 memory, DQ-DQS mapping table is not required. Also, Rcomp resistor values are provided based on SDP v/s DDP memory. BUG=b:70188937 Change-Id: Ic1d0cfdb7d8b02fa0be0a4c54b20057a4c2fc3ce Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/22779 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* mb/google/poppy/variants/soraka: Tune I2C5 paramsFurquan Shaikh2017-12-111-1/+1
| | | | | | | | | | | | | | This change updates scl_lcnt value for I2C5 to bring the bus frequency closer to 400kHz. BUG=b:65062416 TEST=Verified that I2C5 frequency is between 389-396kHz. Change-Id: Ibaccab0c797174332633cb75e30d18ff5af76a43 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/22788 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* soc/amd/common: Move files to common/blockRichard Spiegel2017-12-112-2/+2
| | | | | | | | | | | | | | | | The following files need to be moved: amd_pci_util.c, amd_pci_util.h and spi.c. The remaining files are AGESA related and will be part of a separate issue/commit. BUG=b:62240201 TEST=Build with no error gardenia and kahlee (no code change, just folder reorg). Change-Id: I3f965afa21124d4874d3b7bfe0f404a58b070e23 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/22765 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
* google/gru: Stop mucking with unused I2S0 pins in codec configJulius Werner2017-12-112-21/+6
| | | | | | | | | | | | | | | | | | | | | | Due to a schematic error, our code was written to configure more I2S0 pins than are actually used. We're also pinmuxing the whole bank of pins over to the I2S controller even though we don't need them all. Restrict the GPIO initialization and pinmuxing to the pins we really need so the other ones can be correctly used as SKU ID pins on Scarlet. Also, move the "audio" IO voltage domain selection to the other such selections in the bootblock, since that covers two whole banks of GPIOs and there's no guarantee that they're all used for audio (and thus not needed before ramstage). BUG=b:69373077 TEST=Booted Scarlet, confirmed correct SKU ID (7) was detected on rev2. Change-Id: I9314617e725fe83d254984529f269d4442e736f1 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/22791 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Schneider <dnschneid@chromium.org>
* google/gru: Change Scarlet SKU ID pins to pull-upsJulius Werner2017-12-111-1/+2
| | | | | | | | | | | These pins need to be pull-ups. I forgot. BUG=b:69373077 Change-Id: I9314617e01d35898254984529f269d4442e736f1 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/22775 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* google/nautilus: Add Maxim98357a supportNaveen Manohar2017-12-112-0/+6
| | | | | | | | | | | | | | | Adds Maxim98357a support for Nautilus using the generic driver in drivers/generic/max98357 BUG=b:68686020 TEST=With entire merged audio should be enabled on max98357 speaker codec. Change-Id: I958bf7c1395259b3e3fb30332882fd51a48dc0cc Signed-off-by: Naveen Manohar <naveen.m@intel.com> Reviewed-on: https://review.coreboot.org/22458 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
* mb/google/poppy/variants/nautilus: add SPK DMIC nhlt supportNaveen Manohar2017-12-112-0/+11
| | | | | | | | | | | | | | | | | Nautilus board uses max989357a speaker codec and 4CH DMIC. Select the appropriate NHLT blob to be packaged in CBFS. Also generate the required ACPI NHLT table for codec and the supported topology in nautilus. BUG=b:68686020 TEST=With the required driver support in kernel verify that the Audio plays on Speaker and captures on 4CH DMIC Change-Id: Ie90af02e0935029f53f9020bd78027b6eb31a187 Signed-off-by: Naveen Manohar <naveen.m@intel.com> Reviewed-on: https://review.coreboot.org/22457 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
* google/cyan: fix FSP memory init paramsMatt DeVillier2017-12-091-3/+5
| | | | | | | | | | | | | | | | | | In the original Chromium source, PcdMemorySpdPtr is only set for cyan, but none of the other Braswell variants. When upstreamed, it was left set for all boards as it didn't appear to be problematic. In wider testing, I came across one reks board for which it caused FSP memory init to fail, so restricting the parameter to cyan only as it was originally. TEST: build/boot google/reks with Micron EDF8132A3MA-JD-F RAM, observe board now successfully boots where it did not previously. Change-Id: Iacfbd4bc89fa04717baf85704181d346bca2ed2f Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/22782 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mainboard/google/kahlee: Update GPIOsMartin Roth2017-12-091-58/+51
| | | | | | | | | | | | | | | | | | | | | | | | | - The touchscreen interrupt was moved from the GPIO 3, as originally suggested to GPIO 11. This changes the gevent from 2 to 18. - Add EMMC reset on GPIO 93. - Add EMMC bridge PCIe reset on GPIO 40. - Set device enables to high. - Remove extra SCI comment from GPIO 130. - Set individual device PCIe reset pins to high. - Enable global PCIe reset on GPIO 26. - Mark LPC_CLK1 as unused. - Update net names based on latest schematics. - Set Direction and level/edge correctly for SCIs/SMIs. - Remove SCI for pen detect. - Add comments. BUG=b:70234300, b:69681660, b:69305596 TEST=build grunt Change-Id: Ib591e4278ed23d0963ecb19ad9c326498b4c7796 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22751 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* mainboard/google/kahlee: Update PCIe port mapMartin Roth2017-12-097-6/+171
| | | | | | | | | | | | | | | | - Grunt moved the EMMC chip to port 2, where Kahlee had the SD reader on PCIe port 1, so move the OemCustomize file into the variant directory. - Add comments in baseboard version so it's easier to understand. - Update reset pins, put the definitions in gpio.h BUG=b:70255003 TEST=Build and boot Kahlee. Build Grunt. Change-Id: I78ec72e9d6fd52b8ac75e7187bd01ee7ddc3ba2a Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22750 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
* google/fizz: Set BJ max current and voltageDaisuke Nojiri2017-12-081-15/+92
| | | | | | | | | | | | | | | | This patch makes coreboot set the max current and voltage for barrel jack adapters. BUG=b:64442692 BRANCH=none TEST=Boot Fizz. Use chgsup console command to verify the max current and voltage are set as expected. Change-Id: Ifebee09096e0935cc7d3e53920a251b0496d3c55 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://review.coreboot.org/22623 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/reef: provide override GPIO table in coralChris Wang2017-12-083-0/+44
| | | | | | | | | | | | | | | | | | | | Allow overriding specific GPIOs by SKU ID. Override two GPIO settings for nasher to save the power consumption when the system in S0ix. Change as below: AVS_DMIC_CLK_A1: IGNORE -> Tx1RXDCRx0. AVS_DMIC_CLK_B1: IGNORE -> Tx1RXDCRx0. BUG=b:69025557 BRANCH=master TEST=compile/verify the power consumption change from ~150mW to ~100mW on clamshell SKU and from ~200mW to ~100mW for convertible SKU. Change-Id: I9e0674f206426fddb3947273754774b310106334 Signed-off-by: Chris Wang <chriswang@ami.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/22752 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* google/scarlet: update Kingdisplay kd097d04 timingLin Huang2017-12-071-4/+4
| | | | | | | | | | | | | | With the old timing, the hblank time isn't large enough, it may cause display artifacts. So fix it. BUG=b:70160653 TEST=panel work on Scarlet rev2 board Change-Id: Ib061f5e215611d20f59e3f24cfe3c7fbc507ebed Signed-off-by: Lin Huang <hl@rock-chips.com> Reviewed-on: https://review.coreboot.org/22746 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* kahlee/ec.c: Use new wide IO functionRichard Spiegel2017-12-071-3/+6
| | | | | | | | | | | | | | | | In preparation to deleting early_setup,c, change early_ec_init() to use new southbridge.c function sb_set_wideio_range and remove <#ifdef __PRE_RAM__>. BUG=b:64033893 TEST=Build, boot and check serial output, search for "Covered by wideIO xx", which should match earlier message "Range assigned to wide IO xx" generated within modified early_ec_init(). Change-Id: Iaea17f4f636aab6bd8b05b1b3bed53a677164e74 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/22591 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* mb/google/poppy/variants/nami: Add support for nami boardFurquan Shaikh2017-12-079-0/+902
| | | | | | | | | | | | This change adds variant nami derived from baseboard poppy. BUG=b:70160119 Change-Id: Ic6795d49d3e6e98a32f4af0b621e8bb463041412 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/22703 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* mb/google/poppy: Add support for DDR4 memoryFurquan Shaikh2017-12-074-43/+84
| | | | | | | | | | | | | | | | This change updates memory SPD handling code in baseboard poppy to allow variants to define either LPDDR3 or DDR4 memory types. In addition to that, it also updates the function to print SPD info considering offsets that might be different across the two memory types. BUG=b:70188937 Change-Id: Iefad01719c62264fb0d7e987904e77647d6026c2 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/22745 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* mb/google/poppy/variants/nautilus: Fix memory paramsFurquan Shaikh2017-12-072-0/+51
| | | | | | | | | | | | | | | | Until now, nautilus was using the DQ-DQS mappings provided by the baseboard. However, based on schematics, these values are not correct. This change adds DQ-DQS mapping tables for nautilus. BUG=b:70188533 Change-Id: Ife6ba19b8fe8873ab8cca977ca8f34a4d86e8e6e Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/22706 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: shkim <sh_.kim@samsung.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* google/gru: Add SKU ID for ScarletJulius Werner2017-12-071-0/+16
| | | | | | | | | | | | | | Scarlet has SKU detection strapping pins now. This patch adds the code to read them. BUG=b:69373077 Change-Id: I8d889a845950923bc7b5be9b79792cf3c8b6b8ad Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/22697 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* boardid: Switch from Kconfig to weak functionsJulius Werner2017-12-0719-25/+0
| | | | | | | | | | | | | | This patch switches the board_id and ram_code helper framework to use weak functions rather than Kconfigs to determine whether the board supplies these IDs. This cuts down on the amount of boilerplate Kconfigs many boards have to set and also gives them more flexibility, such as being able to determine at runtime whether a given ID is present. Change-Id: I97d6d1103ebb2a2a7cf1ecfc45709c7e8c1a5cb0 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/22695 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* boardid: Minor clean up and standardizationJulius Werner2017-12-0715-15/+15
| | | | | | | | | | | | | | | Merge the different coreboot table strapping ID structures into one because they're really just all the same, and I want to add more. Make the signature of the board_id() function return a uint32_t because that's also what goes in the coreboot table. Add a printk to the generic code handling strapping IDs in ramstage so that not every individual mainboard implementation needs its own print. (In turn, remove one such print from fsp1_1 code because it's in the way of my next patch.) Change-Id: Ib9563edf07b623a586a4dc168fe357564c5e68b5 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/22741 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Kconfig: Remove BOARD_ID_MANUAL optionJulius Werner2017-12-063-1/+8
| | | | | | | | | | | | | | | | | | The BOARD_ID_MANUAL and BOARD_ID_STRING options were introduced for the Urara board which is now long dead, and have never been used anywhere else. They were trying to do something that we usually handle with a separate SKU ID these days, whereas BOARD_ID is supposed to be reserved for different revisions of the same board/SKU. Get rid of it to make further refactoring of other options easier. Also shove some stuff back into the Urara mainboard that should've never crept into generic headers. Change-Id: I4e7018066eadb38bced96d8eca2ffd4f0dd17110 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/22694 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/poppy: Remove variant_cros_gpios from variantsFurquan Shaikh2017-12-062-22/+0
| | | | | | | | | | | | | Variants nautilus and soraka currently provide the exact same definition for variant_cros_gpios as provided by the baseboard. This change removes the function defintions from variants so that the weak definition in baseboard can be used. Change-Id: Ic88623f34039792f0f9fb46842b24e4f1290981b Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/22705 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/poppy: Add config option for camera ACPI supportFurquan Shaikh2017-12-063-16/+9
| | | | | | | | | | | | | This change adds a new config option VARIANT_HAS_CAMERA_ACPI to allow variants to define ACPI tables for camera support. It also prevents boards that do not need this from unnecessarily providing dummy files for camera ACPI support. Change-Id: I91f8e407e0f021071eeadbde8c2695e2a6d69e06 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/22702 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* mb/google/poppy: Change POPPY_USE_* to VARIANT_HAS_*Furquan Shaikh2017-12-061-21/+20
| | | | | | | | | | | | Change the prefix for TPM options from POPPY_USE_* to VARIANT_HAS_*. This makes it clear that these are variant specific options. Change-Id: I6fd120a34a5b0c1f018164d5c2b60548da1d0f61 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/22701 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* mb/google/poppy: Introduce VARIANT_SPECIFIC_OPTIONS_*Furquan Shaikh2017-12-062-6/+21
| | | | | | | | | | | | In order to allow variants to select different Kconfig options, this change adds VARIANT_SPECIFIC_OPTIONS_${VARIANT_NAME} which can be selected by each variant in Kcnonfig.name. Change-Id: I15db2fdac5c9e55f9698c8a0c083d6467afae245 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/22700 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* mb/google/poppy: Remove dynamic disabling of TPMFurquan Shaikh2017-12-061-15/+0
| | | | | | | | | | | | This change removes the dynamic disabling of TPM based on config options. Poppy and its variants will have only one type of TPM supported and so there is no need to update it dynamically. Change-Id: Ie82825fcf7092e845583edaac9ba0d3fc9d1dd80 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/22704 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/poppy/variants/soraka: Disable SPI TPMFurquan Shaikh2017-12-062-47/+2
| | | | | | | | | | | Soraka is no longer using SPI TPM. This change disables GSPI0 in device tree and updates gpio config accordingly. Change-Id: Ia0554ce3a0d553631123cc2b23b6dc2f6f40a1a3 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/22699 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* mb/google/poppy: Disable SPI TPMFurquan Shaikh2017-12-062-47/+2
| | | | | | | | | | | Mainboard poppy is no longer using SPI TPM. This change disables GSPI0 in device tree and udpates gpio configuration accordingly. Change-Id: I713e41c45e323bf13aa79412ec679c90121a52b2 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/22698 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* google/kahlee: Set USB OC pinsMarc Jones2017-12-064-0/+49
| | | | | | | | | | | | | | | Set the USB over current pins for the Grunt baseboard and Kahlee mainboard. Removes the ACPI ASL OC code, which is not used on Stoney Ridge SOC. BUG=b:69229635 TEST=Build and boot Kahlee. Not tested with OC test fixture. Change-Id: I5a9b3409d9c91b89fd02f8eecf9e04c435f14342 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/22679 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
* google/gru: update RAMID tableLin Huang2017-12-0511-7847/+22
| | | | | | | | | | | There is some confusion with old RAMID table, make it clear, and let's no longer tangle it in future. Change-Id: I44215b4a6668074575a5df691ac1ff8fa3d15492 Signed-off-by: Lin Huang <hl@rock-chips.com> Reviewed-on: https://review.coreboot.org/22663 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* mb/google/poppy,nautilus,soraka: Disable PD on AC_PRESENT in deep SxFurquan Shaikh2017-12-053-3/+3
| | | | | | | | | | | | | This change updates device tree deep_sx_config to disable internal pull-down on AC_PRESENT. BUG=b:69983729 Change-Id: I041900a5262f8fd920856f126185329242a0639a Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/22689 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* mb/google/fizz: Enable Wake-on-Lan featureGaggery Tsai2017-12-041-0/+1
| | | | | | | | | | | | | | | This patch enables WOL feature. BUG=b:69290148 BRANCH=None TEST=powerd_dbus_suspend && sudo etherwake -i eth0 $MAC to make sure the system could be woken up by WOL packet. Change-Id: I1178a776db2cdb448fe6650d49ae6c0281ac1128 Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com> Reviewed-on: https://review.coreboot.org/22606 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
* google/reef: Fix whitespace inconsistency in coral codePatrick Georgi2017-12-021-4/+4
| | | | | | | | | | | | | BUG=none BRANCH=none TEST=none Change-Id: I4e61f1327027c5100773e2b837f439a939807e72 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/22662 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* google/reef: add more USB tuning for coral variantsPatrick Georgi2017-12-021-0/+11
| | | | | | | | | | | | | | | Lava numbers are in. BUG=b:69990330 BRANCH=none TEST=verified that USB signal is within spec Change-Id: I7416ec8d058271700ebe43f8d92af61c6c0d6b42 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/22661 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ren Kuo <ren.kuo@quantatw.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* mainboard/google/kahlee: Remove usb_oc.asl filesMartin Roth2017-12-024-85/+0
| | | | | | | | | | | | | | | These files aren't needed for the overcurrent functionality. BUG=b:69305596, b:69229635 TEST=Build Grunt & Kahlee. Overcurrent wasn't yet enabled so no other testing was needed. Change-Id: I8dcd50a249e387ccf1142949b359cee09942460a Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22659 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
* mainboard/google/kahlee: Add Baseboard GPIOsMartin Roth2017-12-022-8/+294
| | | | | | | | | | | | | Add initial baseboard GPIOs based on grunt schematics. BUG=b:69305596 TEST=Build grunt Change-Id: I4efcee7dbf54fb9ea82e5e9394db805bb69203c8 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22546 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
* mainboard/google/kahlee: Update Kconfig string used in makefilesMartin Roth2017-12-011-1/+1
| | | | | | | | | | | | | | | | Update the variable ${CONFIG_VARIANT_DIR} to use parens instead. Either is valid, but since we use parentheses everywhere else, it's better to be consistent. BUG=b:69691210 TEST=Build grunt & kahlee Change-Id: Ieffabaae5516a893f1dc1f7195a17c4cdeae8853 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22656 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
* mb/google/poppy/variants/nautilus: Disable DPTFFurquan Shaikh2017-11-302-4/+1
| | | | | | | | | | | | This change disables DPTF until the support is properly added in dptf.asl Change-Id: I68f2442e00718a4edbb34661d31d3a415d41c29f Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/22560 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
* mainboard/google/fizz: Disable DPTF active policyDavid Wu2017-11-301-40/+0
| | | | | | | | | | | | | | | | Use EC to perform FAN control. BUG=b:67487721,b:69404739,b:64439568 BRANCH=master TEST=emerge-fizz coreboot and boot on fizz dut Change-Id: I3394d3af9cbdb3eab1f18254909f60e2704735c3 Signed-off-by: David Wu <david_wu@quantatw.com> Reviewed-on: https://review.coreboot.org/22481 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: TH Lin <t.h_lin@quanta.corp-partner.google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
* mb/google/poppy/variants/soraka: Set PCH thermal trip point to 75 degreeCSubrata Banik2017-11-301-0/+3
| | | | | | | | | | | | | | | | | | | PMC logic shuts down the thermal sensor when CPU is in a C-state and DTS Temp <= Low Temp Threshold in case Dynamic Thermal Shutdown in S0ix is enabled. BUG=b:69110373 BRANCH=none TEST=Ensure Thermal Device(B0: D20: F2) TSPM offset 0x1c[LTT (8:0)] value is 0xFA. Change-Id: I6246300a4376a0194950d4de277af040b10b6c1f Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/22628 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
* mb/google/nautilus: add synaptics touch screen supportChris Wang2017-11-301-1/+14
| | | | | | | | | | | | | | | Add synaptics touchscreen in the device tree so that the correct ACPI device is created. BUG=b:66462881 BRANCH=master TEST=compiled/verify the touchscreen works Change-Id: I6e89a5db0e9f8ae777eed661f3bf89d653a937e6 Signed-off-by: Chris Wang <chriswang@ami.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/22613 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
* google/kahlee: Add SPD functionMarc Jones2017-11-2911-9/+141
| | | | | | | | | | | | | | | | | | Add the mainboard_spd_read function in romstage and call the variants function. Grunt is the baseboard and has soldered down memory, so add it for the default weak SPD functions and build the SPDs in cbfs. Kahlee overrides the weak SPD function and falls back to the soc I2C SPD functions. BUG=b:67845441 TEST=Build and boot Kahlee. Change-Id: I789002bfadc1a2b24f9046708986d29c0e2daf33 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/22486 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
* google/kahlee: Rename board_id to memory_skuMarc Jones2017-11-296-36/+7
| | | | | | | | | | | | | | | | The GPIOs used in board_id are meant to indicate the memory configuration. Rename board_id to memory_skus. Report the board_id received from the EC. BUG=b:69649438 Change-Id: I84bacead3daf829c97f595c4c11a243953243c29 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/22561 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
* mb/google/poppy/variants/nautilus: Disable camera devicesFurquan Shaikh2017-11-291-2/+2
| | | | | | | | | | | This change disables camera devices until camera support is properly added for nautilus. Change-Id: I7de37cbf9c32fa063f55a2e54986e33b66acfa3b Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/22559 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* mb/google/poppy: Add variant support for camera aslFurquan Shaikh2017-11-297-3/+67
| | | | | | | | | | | | | | | | | | This change adds infrastructure to allow variants to define their own camera.asl file. - Poppy and soraka use the one provided by baseboard. - Dummy file is added for nautilus since it does not have camera support enabled yet. TEST=Verified that DSDT table remains the same with and without this change. Change-Id: I0f0b489e74739aa4708283d58d8b7626b77a89a3 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/22558 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: shkim <sh_.kim@samsung.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* google/scarlet: support kd097d04 panelLin Huang2017-11-281-2/+165
| | | | | | | | | | Support kd097d04 dual mipi panel on Scarlet. Change-Id: Ie8bc0cbb79840f1924a8cc111f2511292203731f Signed-off-by: Lin Huang <hl@rock-chips.com> Reviewed-on: https://review.coreboot.org/22472 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* google/gru: correct backlight gpioLin Huang2017-11-283-3/+11
| | | | | | | | | | | it uses backlight enable pin as backlight gpio currently, correct it and define the right backlight gpio. Change-Id: I7c5abfd5bbbae015b899f3edc8892ea32bf82463 Signed-off-by: Lin Huang <hl@rock-chips.com> Reviewed-on: https://review.coreboot.org/22529 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* rockchip/rk3399: support dual mipi dsiLin Huang2017-11-282-12/+5
| | | | | | | | | | | | | Refactor the mipi driver, so we can support dual mipi panel. And pass the panel data from mainboard.c, that we can support different panel with different board. Change-Id: Id1286c0ccbe50c89514c8daee66439116d3f1ca4 Signed-off-by: Lin Huang <hl@rock-chips.com> Reviewed-on: https://review.coreboot.org/22471 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Brian Norris <briannorris@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* mb/google/poppy/variants/nautilus: set I2C speed to 400KHzChris Wang2017-11-281-8/+52
| | | | | | | | | | | | | | | Add "speed_config" for each I2C port configuration to set speed to 400KHz. BRANCH=master BUG=none TEST=compiled/verified Change-Id: Icb48733b87cefc92577547b1eab661a8cbb12be6 Signed-off-by: Chris Wang <chriswang@ami.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/22589 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-09-04 05:48:06 +0000