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* mb/intel/ehlcrb: Update FIVR configsLean Sheng Tan2021-07-211-0/+16
| | | | | | | | | | | | | | | | | | This patch sets the optimized FIVR configs for ehlcrb customized based on the performance measurements to achieve the better power savings in sleep states. - Enable the external V1p05, Vnn, VnnSx rails in S0i3, S3, S4, S5 states. - Update the supported voltage states. - Update max supported current, voltage transition time and RFI spread spectrum. Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Change-Id: I1e30ff6d84bfe078fcce0f968fce6aaab7fd575b Reviewed-on: https://review.coreboot.org/c/coreboot/+/55981 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/intel/adlrvp: Enable I2S audio codecs on ADL-M RVPAnil Kumar2021-07-214-1/+88
| | | | | | | | | | | | | | | | | | - Add configurability using FW_CONFIG field in CBI, to enable/disable I2S codec support for MAX98373 codecs - AUDIO=ADL_MAX98373_ALC5682I_I2S: enable max98373 codec using expansion board Bug=None Test=With CBI FW_CONFIG set to 0x100, check I2S audio output on expansion card Signed-off-by: Anil Kumar <anil.kumar.k@intel.com> Change-Id: If2649647e58c5f30e2b539d534adf2a4e68f4fda Reviewed-on: https://review.coreboot.org/c/coreboot/+/52221 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/{google, intel}: Make use of `cpu/intel/cpu_ids.h'Subrata Banik2021-07-191-1/+1
| | | | | | | | | | | Remove inclusion of mp_init.h for getting CPUIDs and use dedicated cpu_ids.h file in SoC directory. Change-Id: I411f4f2c237a9e2d39038ee30f2957698ee053bd Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56412 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
* mb/intel/adlrvp: Update PMC Descriptor for Alder lake A0(906a0h) siliconSridhar Siricilla2021-07-171-0/+86
| | | | | | | | | | | | | | | | | | | The patch updates PMC Descriptor which is part of Descriptor Region if system equipped with Alder lake A0 silicon. This change allows to use unified Descriptor Region for Alder lake A0(CPU ID:0x906a0) and B0 (CPUD ID:0x906a1) silicons. The change has to be reverted before EOM is enableda on the system. BUG=B:187431859 TEST=Verified PMC Descriptor getting modified for Alder lake B0 silicon if not updated. Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I2a1f60fda7575212bb694fc423bd229452515903 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56073 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
* mb/intel/adlrvp: Disable xDCI in devicetreeMonika A2021-07-151-1/+0
| | | | | | | | | | | Disable tcss_xdci as it is not used. Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Change-Id: I94102240b13d2b96e0295f41bc2b0ba078faf342 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52262 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
* intel/kblrvp: Move lockdown config to baseboard devicetreeFelix Singer2021-07-134-15/+4
| | | | | | | | | | | | | | | | | | Clean up lockdown configuration and move it to the baseboard's devicetree. Since most of the mainboards use `CHIPSET_LOCKDOWN_COREBOOT`, use it for the rvp8 variant for consistency as well. Built intel/rvp11 with `BUILD_TIMELESS=1` and coreboot.rom remains identical. intel/rvp8 changes, as expected. Change-Id: I78e847c321c61c3a974b26f30bc2823ff84df651 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56212 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/intel/kblrvp/variants: Fix indentation and remove empty linesFelix Singer2021-07-132-3/+1
| | | | | | | | | Change-Id: I4b5e0992494949bcb2fbda1361e0118c087a437a Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56211 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/intel/adlrvp_m: Enable EC software syncThejaswani Putta2021-07-121-1/+1
| | | | | | | | | | | | | | | | | This patch enables CONFIG_VBOOT_EARLY_EC_SYNC. EC software sync will be performed in romstage. BUG=None BRANCH=None TEST=Verify EC software sync works on adlrvp_m Signed-off-by: Thejaswani Putta <thejaswani.putta@intel.com> Change-Id: I3a13094e5da2f672a6789fe86528de44e909045e Reviewed-on: https://review.coreboot.org/c/coreboot/+/56154 Reviewed-by: Selma Bensaid <selma.bensaid@intel.com> Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/intel/tglrvp: Update Power Limit2 minimum valueSumeet Pawnikar2021-07-082-2/+2
| | | | | | | | | | | | | | | | Update Power Limit2 (PL2) minimum value to the same as maximum value. DTT does not throttle PL2, so this minimum value change here does not impact any existing behavior on the system. BUG=None BRANCH=None TEST=Build and test on tglrvp system Change-Id: I6bbbfa8e43a241df721b91425294983c1d561f2c Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56085 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/intel/adlrvp_m: Remove ASL code and enable dynamic SSDT creation for ↵Varshit B Pandya2021-07-052-3/+104
| | | | | | | | | | | | | | | | camera ACPI This change updates device tree to enable SSDT generation for world facing camera and user facing camera for ADLRVP. Also reverts DSDT changes related to both camera. TEST=Build and Boot aldrvp check i2c enumeration and output of media-ctl Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com> Change-Id: I39f82dc9eb91496d80479ae3f59ca5e03402a599 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55733 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
* mb/intel/adlrvp: Remove ASL code and enable dynamic SSDT creation for camera ↵Varshit B Pandya2021-07-054-506/+104
| | | | | | | | | | | | | | | | | ACPI This change updates device tree to enable SSDT generation for world facing camera and user facing camera for ADLRVP. Also reverts DSDT changes related to both camera. TEST=Build and Boot aldrvp check i2c enumeration and output of media-ctl Compared SSDT with this patch against DSDT without this patch, they are same Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com> Change-Id: I08834bbcf80dc46737de07f69a2402ed6bf93d4f Reviewed-on: https://review.coreboot.org/c/coreboot/+/55526 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
* mb/intel/adlrvp: Update the FIVR configurationsV Sowmya2021-07-051-0/+15
| | | | | | | | | | | | | | | | This patch sets the optimized FIVR configuration for adlrvp cutomized based on the pnp measurements to achieve the better power savings in sleep states. * Enable the external V1p05, Vnn, VnnSx rails in S0i1, S0i2, S0i3, S3, S4, S5 states. * Update the supported voltage states. * Set the ICC max to 500mA for v1p05 and vnn. Signed-off-by: V Sowmya <v.sowmya@intel.com> Change-Id: I83e6910502d5cf9d4c26fa581272f59ac483ae19 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55703 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
* soc/intel/elkhartlake: Enable PCH GBELean Sheng Tan2021-06-301-0/+4
| | | | | | | | | | | | | | | | | | Enable PCH GBE with following changes: 1. Configure PCH GBE related FSP UPD flags 2. Use EHL own GBE ACPI instead of common code version due to different B:D.F from the usual GBE 3. Add kconfig PMC_EPOC to use the PMC XTAL read function Due to EHL GBE comes with time sensitive networking (TSN) capability integrated, EHL FSP is using 'PchTsn' instead of the usual 'PchLan' naming convention across the board. Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Change-Id: I6b0108e892064e804693a34e360034ae7dbee68f Reviewed-on: https://review.coreboot.org/c/coreboot/+/55355 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* ec/google: Use EC_HOST_EVENT_NONERob Barnes2021-06-301-3/+3
| | | | | | | | | | | | | | google_chromeec_get_event returns 0 for no event. Return EC_HOST_EVENT_NONE=0 to improve readability. BUG=b:184074997 TEST=Build and boot guybrush without error Signed-off-by: Rob Barnes <robbarnes@google.com> Change-Id: Ic08ed9ccdd7c0023d0fe8b641fcf60dca495a242 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55547 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/intel/adlrvp_m: Enable TCSS USB ports device pathBernardo Perez Priego2021-06-281-1/+15
| | | | | | | | | | | | | | This provide a more consistent mechanism to enable corresponding USB TCSS port. BUG=b:182960979 TEST=Boot device, Type C port should operate correctly. Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com> Change-Id: Iadc0df2e6e19a5afacbb7db1ae0bc7546dbcdc1a Reviewed-on: https://review.coreboot.org/c/coreboot/+/55772 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/alderlake: Update mainboard_memory_init_params() argumentSubrata Banik2021-06-242-5/+5
| | | | | | | | | | | | | | This patch updates mainboard_memory_init_params() function argument from FSPM_UPD to FSP_M_CONFIG. Ideally mainboard_memory_init_params() function don't need to override anything other than FSP_M_CONFIG UPDs hence passing config block alone rather passing entire FSP-M UPD structure. Change-Id: I238870478a1427918abf888d71ba9c9fa80d3427 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55785 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/intel/sm: Skip FSP to program UART0Subrata Banik2021-06-231-1/+1
| | | | | | | | | | | Set "SerialIoUartMode" for UART0 as PchSerialIoSkipInit Change-Id: Idc7da7bf38634c04b0f4acd4c7c2ea9fa88545e5 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55207 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: V Sowmya <v.sowmya@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/intel/adlrvp: Update Mainboard part number and VendorMeera Ravindranath2021-06-221-1/+5
| | | | | | | | | | | | | | | dmidecode output should match with the CrOS kernel updated string. TEST=dmidecode grep "Manufacturer" = Intel Corporation dmidecode grep "Product name" = Alder Lake Client Platform Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Change-Id: I7cce423de624e7056e88b52a1443c554fd9123bc Reviewed-on: https://review.coreboot.org/c/coreboot/+/51408 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/intel/ehlcrb: Change default romsize and remove chromeos.fmdLean Sheng Tan2021-06-182-44/+1
| | | | | | | | | | | | Change the default rom size to 32MB and remove chromeos.fmd because Chrome OS is not supported on EHL for now. Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Change-Id: I49d9404eb901087037b5423a4a503c5271e14138 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55554 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/intel/adlrvp_m: Remove DP_HPD 1 & 2 definition from devicetreeBernardo Perez Priego2021-06-171-4/+0
| | | | | | | | | | | | | | | | | Due to latest corresponding UPD filling implementation, this is not required. This patch fixed the brokenness caused by Commit hash b10afbd2e2a8326fb21dc726a6c2bd53b06eb010. Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com> Change-Id: I49e434f7bbafcb148e82202697e87c3e4268d7b1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55635 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/intel/adlrvp_m: Configure DP_HPD as PAD_NC and disable DdiPortHpdBernardo Perez Priego2021-06-172-1/+7
| | | | | | | | | | | | | | | | | GPP_A19(DP_HPD1) and GPP_A20(DP_HPD2) were configured native function (NF1), this causes redundancy with legacy HPD interruption. This change configures GPP_A19 and GPP_A20 to be no connection and disables DdiPort1Hpd and DdiPort2Hpd. BUG=None TEST=Boot to kernel and verified no kernel HPD pins assertion message. Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com> Change-Id: I80ef40a1aca19cd6ad56219175d2fd40890a393d Reviewed-on: https://review.coreboot.org/c/coreboot/+/55548 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sanrio Alvares <sanrio.alvares@intel.com> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
* broadwell boards: Use Haswell hostbridge.aslAngel Pons2021-06-161-1/+1
| | | | | | | | | | | | | Use hostbridge.asl from Haswell instead of Broadwell. Both files are equivalent. Then, drop the now-unused hostbridge.asl from Broadwell. Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical. Change-Id: I87d51727b75a9c59e2f5f3ba8d48c575ce93c78c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55484 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* soc/intel/alderlake/romstage: Update display UPDs based on InternalGfxSubrata Banik2021-06-163-19/+13
| | | | | | | | | | | | | | | | Disable all display related UPDs if IGD is not enabled as FSP don't need to perform display port initialization while IGD itself is disabled else assign UPDs based on devicetree config. TEST=Dump FSP-M display related UPDs with IGD enable and disable to ensure patch integrity. Change-Id: I0479904141dfc5e707679109aa18b7ef4264cf96 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55273 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* soc/intel/broadwell/pch: Replace ACPI device NVSAngel Pons2021-06-141-1/+0
| | | | | | | | | | | | | | | | | | | | The same functionality can be provided through a runtime-generated SSDT. The remaining parts of device NVS are removed in a follow-up. Since the SSDTs are only loaded after the DSDT (if loaded at all), using SSDT-provided objects outside method bodies is not possible: the objects are not yet in OSPM's ACPI namespace, which causes in ACPI errors. Owing to this, the operation regions used by the _PS0 and _PS3 methods need to be moved into the SSDT, as they depend on the SSDT-provided BAR1 values. Tested on out-of-tree Compal LA-A992P, generated SSDT disassembles with no errors and contains expected values. Linux does not complain either. Change-Id: I89fb658fbb10a8769ebea2e6535c45cd7c212d06 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52520 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/intel/adlrvp: Add board id for MR DDR5 SKUDeepti Deshatty2021-06-144-4/+8
| | | | | | | | | | | | | Add support for Maple Ridge DDR5 SKU with boardid 0x16 TEST=Verified build for ADL-P Chrome RVP Signed-off-by: Deepti Deshatty <deepti.deshatty@intel.com> Change-Id: I9f0e9072f5866b60fb8463bb90f61915c78568db Reviewed-on: https://review.coreboot.org/c/coreboot/+/52760 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Meera Ravindranath <meera.ravindranath@intel.corp-partner.google.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: V Sowmya <v.sowmya@intel.com>
* mb/*/mptable.c: Use smp_write_pci_intsrc()Kyösti Mälkki2021-06-141-17/+17
| | | | | | | | | | | | Split parameter '(devfn << 2) | intx' to 'devfn, intx'. Formatted with 'spatch --max-width 96' Change-Id: I17a6b3919b6e55aaa7ca2873ca713b36ebe7d3a6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55285 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/*/mptable.c: Replace magic constantsKyösti Mälkki2021-06-141-19/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Read I/O APIC ID and version from hardware registers. With coccinelle below, and minor fixups. @ r1 @ expression E1, E2, E3, E4; typedef u8; @@ -smp_write_ioapic(E1, E2, E3, E4); +u8 ioapic_id = smp_write_ioapic_from_hw(E1, E4); @ r2 @ expression E1, E2, E3, E4; @@ -mptable_add_isa_interrupts(E1, E2, E3, E4) +mptable_add_isa_interrupts(E1, E2, ioapic_id, E4) @ r3 @ expression E1, E2, E3, E4, E5, E6, E7; @@ -smp_write_pci_intsrc(E1, E2, E3, E4, E5, E6, E7) +smp_write_pci_intsrc(E1, E2, E3, E4, E5, ioapic_id, E7) @ r4 @ symbol mp_INT; expression E1, E3, E4, E5, E6, E7; @@ -smp_write_intsrc(E1, mp_INT, E3, E4, E5, E6, E7) +smp_write_intsrc(E1, mp_INT, E3, E4, E5, ioapic_id, E7) Change-Id: I20799f0c09cf0292661e1f3cb93373b2c68b7314 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55284 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Furquan Shaikh <furquan@google.com>
* cpu/x86/lapic: Replace LOCAL_APIC_ADDR referencesKyösti Mälkki2021-06-111-1/+1
| | | | | | | | | | | | Note that there are assumptions about LAPIC MMIO location in both AMD and Intel sources in coreboot proper. Change-Id: I2c668f5f9b93d170351c00d77d003c230900e0b4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55194 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/tigerlake: Move MAX_CPUS to KconfigAndy Pont2021-06-101-4/+0
| | | | | | | | | | | | | | | Most of the Kconfig files for Intel SOC devices define the MAX_CPUS value within src/soc/intel/*/Kconfig. Move the definition there for Tiger Lake and remove from the mainboard Kconfig files. Signed-off-by: Andy Pont <andy.pont@sdcsystems.com> Change-Id: If145b9eb5d99821f4ce513118e4417d05f821ef5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55307 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
* soc/intel/adl: Add SKU specific power limits supportSumeet Pawnikar2021-06-071-5/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Power limits (PL1 and PL2) depend on the specific SKU of the CPU. By expanding the SoC chip config power_limits_config member to an array indexed by ADL_*_POWER_LIMITS_*_CORE macros, the appropriate power limits are applied. Using this the correct set of power limits are being selected from the array based on system agent PCI ID. Based on this, chipset.cb file contains the set of power limits being used by varieties of ADL boards. These power limit values are as per document 619501. BUG=None BRANCH=None TEST=Built and verified the following console output on below boards On adlrvp (482): CPU PL1 = 28 Watts CPU PL2 = 64 Watts On adlrvp (682): CPU PL1 = 45 Watts CPU PL2 = 115 Watts On brya (282): CPU PL1 = 15 Watts CPU PL2 = 55 Watts Change-Id: Ic1676e2b4d611cdc85e770f131d5b6d5ecd180be Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54676 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Selma Bensaid <selma.bensaid@intel.com>
* sb/intel/bd82x6x: Drop P_LVLx support in FADTAngel Pons2021-06-071-2/+0
| | | | | | | | | | | IO MWAIT redirection is not enabled, and C-states are reported using the _CST ACPI object, which overrides the P_LVLx values. Change-Id: I737bd58bcda3e7c5f6591e4c2309530ff035e2c8 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55218 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
* bd82x6x boards: Drop redundant `c2_latency`Angel Pons2021-06-071-1/+0
| | | | | | | | | | If unspecified, chipset code already uses 101, and 0x65 == 101. Change-Id: I524ca492fa577003df23017756f74a455582132f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55212 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
* mb/intel/sm: Use device aliasesSubrata Banik2021-06-051-73/+40
| | | | | | | | | | | | | | | | | Use the device aliases provided by alderlake chipset.cb instead of the raw pci device+function. Take advantage of the default states in chipset.cb and only list the devices that are enabled for all shadowmountain board variants. TEST=Dump devicetree device enable list without and with this CL, no difference observed. Change-Id: I2b769d653ad8ad8ff069a0787d00ff33ead5c912 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55206 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/intel/adlrvp: Use device aliasesSubrata Banik2021-06-054-151/+88
| | | | | | | | | | | | | | | | | Use the device aliases provided by alderlake chipset.cb instead of the raw pci device+function. Take advantage of the default states in chipset.cb and only list the devices that are enabled for all different adlrvp boards. TEST=Dump devicetree device enable list without and with this CL, no difference observed. Change-Id: Ib9e82d953416c076588974f3167d00ae96f01bb5 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55205 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/intel/{adlrvp, sm}: Remove ADL-S devices from ADL-P/M devicetree.cbSubrata Banik2021-06-053-30/+0
| | | | | | | | Change-Id: I095394d9a79506346b8464c850d03cbd8ce2b812 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55221 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/elkhartlake: Update FSP-S storage related configsLean Sheng Tan2021-06-041-0/+12
| | | | | | | | | | | | | | Further add initial Silicon UPD storage settings: - SATA - SD card - eMMC Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Change-Id: Id4145fcf156756a610b8a9a705d4ab99fe7b0bf8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55082 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
* soc/intel/elkhartlake: Update FSP-S UPD RP & USB related configsLean Sheng Tan2021-06-041-1/+18
| | | | | | | | | | | | | Further add initial Silicon UPD settings for: - PCIe root ports - USB Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Change-Id: I60afb78a7997b8465dd6318f3abee28f95a65100 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55034 Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/elkhartlake: Update FSP-S UPD configs for graphic & chipsetLean Sheng Tan2021-06-041-0/+14
| | | | | | | | | | | | | | | | | | | Further add initial silicon UPD settings for: - graphics & display - chipset lockdown - PAVP - legacy timer - PCH master gating control - HECI This CL also enables HECI 1 in devicetree.cb. Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Change-Id: I657f44f8506640c23049614b2db9d1837e6d44ed Reviewed-on: https://review.coreboot.org/c/coreboot/+/54960 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
* mb/intel/adlrvp_m: Enable LTR for PCIEBernardo Perez Priego2021-06-011-4/+8
| | | | | | | | | | | | | BUG=none TEST=Use command $ lspci -vv LTR+ is listed on DevCtl2 Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com> Change-Id: If65d08a46b9e7304fbe4b92b7f1e6d4e08c599e7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54492 Reviewed-by: Ryan A Albazzaz <ryan.a.albazzaz@intel.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/elkhartlake: Update FSP-S UPD LPSS related configsTan, Lean Sheng2021-06-011-3/+61
| | | | | | | | | | Add Silicon upd settings for LPSS (GSPI/UART/I2C). Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Change-Id: Ib0c3cd1d37ff9892d09d6d86ac50e230549c7e53 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54959 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
* mb/intel/adlrvp_m: add ec device entry to devicetreeBora Guvendik2021-05-301-0/+7
| | | | | | | | | | | | TEST=Boot to OS and verify acpi tables. Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: I3c78ac44afa3515acef9ea2d59f22f95e6b45e90 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54490 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: John Zhao <john.zhao@intel.corp-partner.google.com> Reviewed-by: John Zhao <john.zhao@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/elkhartlake: Update FSP-M UPD related configsTan, Lean Sheng2021-05-301-0/+42
| | | | | | | | | | | | | | Upload the FSP-M UPD configs. This CL also updated the chip.h and devicetree.cb with the relevant variables and configs. This CL also updated the GPIO related settings (PMC & SD card) in devicetree.cb. Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Change-Id: If6321064b37535b390cf3dd7c41a719c598a0cd7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54892 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
* mb/intel/adlrvp_m: Disable unused TBT ports from device treeBernardo Perez Priego2021-05-281-3/+3
| | | | | | | | | | | | | These PCIe and DMA ports are not available for adlrvp_m. BUG=none TEST=Boot device Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com> Change-Id: Ic568c692fbb82fb3fc70c0cafc2328f8fa2cd74d Reviewed-on: https://review.coreboot.org/c/coreboot/+/54885 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/intel/ehlcrb: Upload EHL CRB GPIO configsTan, Lean Sheng2021-05-281-2/+256
| | | | | | | | | | | Initial upload of the GPIO configs for EHL CRB. This CL also includes the UART GPIO configs in early GPIO table. Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Change-Id: Ied4cbb34149b0b837597c0fc17dc5956f3ca409e Reviewed-on: https://review.coreboot.org/c/coreboot/+/54891 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
* mb/intel/shadowmountain: Update mainboard propertiesJohn Zhao2021-05-181-1/+8
| | | | | | | | | | | | | | This changes updates mainboard properties by adding DFP number and power_gpio for each DFP. BUG=b:186521258 TEST=None Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I29480bf77f7df9890bef64a5f9f02074a34dc131 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54292 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/intel/shadowmountain: Remove power_gpio from baseboardJohn Zhao2021-05-181-6/+1
| | | | | | | | | | | | | | | | Along with upstream kernel for Retimer firmware update, coreboot defines power control for each DFP respectively under host router. This change removes the power_gpio from the baseboard. Individual DFPx power_gpio will be added once the dependent definition is complete. BUG=b:186521258 TEST=Build image successfully. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I819d2900afabbfdb2713fa8eee35d3c90cb904fd Reviewed-on: https://review.coreboot.org/c/coreboot/+/54290 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mainboard: Use decimal for `device lapic 0x0 on`Angel Pons2021-05-182-2/+2
| | | | | | | | | | | Most boards use `device lapic 0 on` with zero written in decimal. For the sake of consistency, update the remaining boards to follow suit. Change-Id: I1d3b1ac107e33aae11189cdd5e719b8e48b10f08 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54359 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* mainboard: Use decimal for `device domain 0x0 on`Angel Pons2021-05-181-1/+1
| | | | | | | | | | | Most boards use `device domain 0 on` with zero written in decimal. For the sake of consistency, update the remaining boards to follow suit. Change-Id: I6e2f0a19d57cfe6fc4e4ac4d14310133ad6b01d8 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54358 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* mainboard: Use decimal for `device cpu_cluster 0x0 on`Angel Pons2021-05-181-1/+1
| | | | | | | | | | | Most boards use `device cpu_cluster 0 on` with zero written in decimal. For the sake of consistency, update the remaining boards to follow suit. Change-Id: I083c8f8e9b38ddcc217dc8bf17ae3c9473ba77e9 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54357 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* soc/intel/alderlake: mb/intel/sm: Add tcss codeDeepti Deshatty2021-05-181-2/+1
| | | | | | | | | | | | | | | Enable FSP 'MultiPhaseSilicon' init to execute tcss configure during silicon init. Type-c aux lines DC bias changes are propagated from tigerlake platform. TEST=Verified superspeed pendrive detection on coldboot. Signed-off-by: Deepti Deshatty <deepti.deshatty@intel.com> Change-Id: Ifce6abb0fce20e408931b904426131a42a5a4a36 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54089 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-12 14:31:18 +0000