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* pci_mmio_cfg: Always use pci_s_* functionsNico Huber2021-11-091-1/+1
| | | | | | | | | | | | | | When MMIO functions are available, the pci_s_* functions do exactly the same thing. Drop the redundant pci_mmio_* versions. Change-Id: I1043cbb9a1823ef94bcbb42169cb7edf282f560b Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58333 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
* ChromeOS: Fix <vc/google/chromeos/chromeos.h>Kyösti Mälkki2021-11-0910-1/+9
| | | | | | | | Change-Id: Ibbdd589119bbccd3516737c8ee9f90c4bef17c1e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58923 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* mb/google,intel: Fix indirect include bootmode.hKyösti Mälkki2021-11-0512-0/+12
| | | | | | | | | | Change-Id: I9e7200d60db4333551e34a615433fa21c3135db6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58921 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/intel/adlrvp: Configure EC in RW GPIOAnil Kumar2021-11-025-4/+13
| | | | | | | | | | | | | | | | | EC_IN_RW signal from EC GPIO is connected to GPIO E7 of SOC. This GPIO can be used to check EC status trusted (LOW: in RO) or untrusted (HIGH: in RW). Branch=none Bug=none Test=Issue manual recovery and confirm DUT is entering recovery mode on ADL-M RVP. Signed-off-by: Anil Kumar <anil.kumar.k@intel.com> Change-Id: I20804db450ab0b3ebe19c51ba2b294a0137d81a7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58099 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* soc/intel/braswell: Set GNVS DPTE via devicetreeAngel Pons2021-11-012-3/+2
| | | | | | | | | | | | Introduce the `dptf_enable` devicetree setting to set the DPTE GNVS field, as newer Intel platforms do. Change-Id: I88b746c64ca57604f946eefb00a70487a2fb27c0 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57988 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
* Revert "mb/intel/adlrvp: Remove EC region"Bernardo Perez Priego2021-10-291-1/+2
| | | | | | | | | | | | | | | | This reverts commit 0a1602217fd0d60c59a497cb83a23b44cf4973d9. EC region is required in order to provide unified coreboot image for Chrome and Windows SKU RVP's. Also removing EC region causes a regression for ADL-P platforms. With this patch EC region is included back into flash map. Change-Id: I0f7f2b5dd392b08e1978a3b3f3236eac0dab1f12 Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58661 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
* intel/adlrvp: Add sub-regions to SI_ME in chromeos.fmdFurquan Shaikh2021-10-261-3/+9
| | | | | | | | | | | | | This change adds sub-regions to SI_ME in chromeos.fmd. These are required to support stitching of CSE components. BUG=b:189177538 Change-Id: Ife48aafcec43555175aad44f8b6307beeaea9184 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58592 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/intel/adlrvp: Rework KconfigFelix Singer2021-10-202-30/+48
| | | | | | | | | | | | | | | | | | | | | Rework Kconfig file that each variant has its own config option with their specific selects / configuration and move common selects to `BOARD_INTEL_ADLRVP_COMMON`, which is used as base for each variant. Also, move selects from Kconfig.name to Kconfig that the configuration is at one place and not distributed over two files. Built each variant with `BUILD_TIMELESS=1` and all generated coreboot.rom files remain identical. Excluded the .config file by disabling `INCLUDE_CONFIG_FILE` to make this reproducible. Change-Id: If68c118f22579cc0a3db570119798f0f535f9804 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56221 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/intel/adlrvp_m: Enable touchpadBernardo Perez Priego2021-10-202-1/+17
| | | | | | | | | | | | | These changes include ELAN touchpad to ACPI tables and configure GPIO's. BUG=None Test=Boot board, touchpad should be functional Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com> Change-Id: I78e5e133f7d3af47395819a79638a90fee4fd19e Reviewed-on: https://review.coreboot.org/c/coreboot/+/57863 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
* mb/intel/adlrvp: Remove EC regionBernardo Perez Priego2021-10-201-1/+0
| | | | | | | | Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com> Change-Id: Ic76c29069beb510dd7620f340e0aab212668c3f3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58235 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
* mb/intel/jasperlake_rvp: Rework KconfigFelix Singer2021-10-202-15/+21
| | | | | | | | | | | | | | | | | | | | | Rework Kconfig file that each variant has its own config option with their specific selects / configuration and move common selects to `BOARD_INTEL_JASPERLAKE_RVP_COMMON`, which is used as base for each variant. Also, move selects from Kconfig.name to Kconfig that the configuration is at one place and not distributed over two files. Built each variant with `BUILD_TIMELESS=1` and all generated coreboot.rom files remain identical. Excluded the .config file by disabling `INCLUDE_CONFIG_FILE` to make this reproducible. Change-Id: Ic7552195ed5a3ae6ab8e456d7d38d5539a052009 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56222 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
* mb/intel/kblrvp: Rework KconfigFelix Singer2021-10-192-11/+28
| | | | | | | | | | | | | | | | | | Rework Kconfig file that each variant has its own config option with their specific selects / configuration and move common selects to `BOARD_INTEL_KBLRVP_COMMON`, which is used as base for each variant. Built each variant with `BUILD_TIMELESS=1` and all generated coreboot.rom files remain identical. Excluded the .config file by disabling `INCLUDE_CONFIG_FILE` to make this reproducible. Change-Id: I2a9c12a15c098fcb64c006a707c94a1aed93d73a Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56219 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
* mb/intel/coffeelake_rvp: Rework KconfigFelix Singer2021-10-192-20/+47
| | | | | | | | | | | | | | | | | | | | Rework Kconfig file that each variant has its own config option with their specific selects / configuration and move common selects to `BOARD_INTEL_COFFEELAKE_COMMON`, which is used as base for each variant. Also, move selects from Kconfig.name to Kconfig so that the configuration is at one place and not distributed over two files. Built each variant with `BUILD_TIMELESS=1` and all generated coreboot.rom files remain identical. Excluded the .config file by disabling `INCLUDE_CONFIG_FILE` to make this reproducible. Change-Id: I3b3d3cff5ea7a3f4d1c4ddd911240763e4891e06 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56217 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Thomas Heijligen <src@posteo.de>
* cpu/intel/speedstep: Constify `get_cst_entries()`Angel Pons2021-10-194-4/+4
| | | | | | | | | | | Make the `get_cst_entries()` function provide a read-only pointer. Also, constify the actual data where applicable. Change-Id: Ib22b3e37b086a95af770465a45222e9b84202e54 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58393 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* mb/intel/adlrvp_m: Enable retimer force power gpioBernardo Perez Priego2021-10-181-1/+4
| | | | | | | | | | | | | | | | | | | Retimer FORCE_PWR GPIO is a debug GPIO, that has to be set LOW, to allow Retimer LC Domain to toggle during a switch from DP Alt to TBT Alt modes. Contrary to DS specifying it may be left unconfigured, hence floating, there are instances seen during boot, where it stays HIGH (adlmrvp) or LOW (adlprvp). Hence configure it to LOW. Branch=none Bug=none Test=Boot to OS, connect TBT dock which enumerates in DP Alt, Login, TBT dock enumerates in TBT Alt Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com> Change-Id: I0ff58823785a31c70535ad9c913c06a653884a2c Reviewed-on: https://review.coreboot.org/c/coreboot/+/58113 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
* soc/intel/skylake: switch to common GNVSMichael Niewöhner2021-10-173-3/+3
| | | | | | | | | | | | | | Switch to common GNVS. No additional fields to those being present in common GNVS are used by any SKL/KBL device. Thus, they're dropped completely. Change-Id: I87ab4ab05f6c081697801276a744d49e9e1908e0 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57946 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
* Skylake boards: Drop setting useless `IRQ_SLOT_COUNT`Angel Pons2021-10-173-12/+0
| | | | | | | | | | | | | The `IRQ_SLOT_COUNT` value is only meaningful when generating a PIRQ table. None of these boards do it, so specifying this value achieves absolutely nothing. Drop it to prevent further useless copy-pasting. Change-Id: I2d63b850c03fc1471c0eef180e8b621311b2c336 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58362 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
* mainboard: Drop invalid `VGA_BIOS_FILE` defaultsAngel Pons2021-10-155-25/+0
| | | | | | | | | | | | | | | | | | | | | | | | If the VGA BIOS file path for `VGA_BIOS_FILE` in a mainboard's Kconfig does not exist in the coreboot tree (including submodules), drop it. These files should be stored in the `site-local` subdirectory and the paths specified for each board in `site-local/Kconfig`. For example: config VGA_BIOS_FILE default "site-local/x200_vbios.bin" if BOARD_LENOVO_X200 Note that this is just an example. There are better ways to structure one's `site-local` subfolder. Using the `CONFIG_MAINBOARD_DIR` option would be one of them, though variants may still need special handling. Also, update autoport to not generate `VGA_BIOS_FILE` defaults. Change-Id: I1b5dfba035a42d7943f270f95fb7d32b285584d2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51340 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* mb/intel/adlrvp: Drop INTEL_CAR_NEM Kconfig select on ADL-M RVPBora Guvendik2021-10-081-2/+0
| | | | | | | | | | | | | This patch enables eNEM flow for ADL-M TEST=Able to build and boot ADL-M RVP using eNEM mode. Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: I69959f4c53f4073e6e8b51491747d8358b4c907b Reviewed-on: https://review.coreboot.org/c/coreboot/+/57323 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
* src/mainboard to src/security: Fix spelling errorsMartin Roth2021-10-053-4/+4
| | | | | | | | | | | | These issues were found and fixed by codespell, a useful tool for finding spelling errors. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Ie34003a9fdfe9f3b1b8ec0789aeca8b9435c9c79 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58081 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* mb/intel/adlrvp{p,m}: Enable dynamic GPIO PMMeera Ravindranath2021-10-042-19/+0
| | | | | | | | | | | | | | | GPIO PM was disabled for adlrvp to evaluate if longer interrupt pulses are required for ADL. Since ADL requires 4us long pulses (EDS:626817), GPIO PM can be enabled. This change drops the GPIO PM override and re-enables dynamic GPIO PM. TEST=Boot adlrvp to OS, ensure no TPM timeout errors. Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Change-Id: I0b7b66b5525d8b80775ab7578ce6b12181af7882 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57411 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
* mb/intel/adlrvp: set PL4 value dynamically for thermalSumeet Pawnikar2021-10-012-8/+14
| | | | | | | | | | | | | | | | | | Set PL4 value dynamically for adlrvp board based on CPU SKUs which is detectable at runtime. These values are based on platform design specification. BUG=None BRANCH=None TEST=Build FW and test on adlrvp board On 682: Overriding power limits PL1 (4000, 28000) PL2 (64000, 64000) PL4 (140000) Change-Id: I9c0c418e2548cc7f9aa647a5ad98123b33e9f9b8 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57464 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/intel/adlrvp: set power limits dynamically for thermalSumeet Pawnikar2021-10-012-6/+11
| | | | | | | | | | | | | | | Set power limit values dynamically based on CPU TDP and PCI ID of SKU. These values are as per platform design specification. BUG=None BRANCH=None TEST=Build FW and test on adlrvp board Change-Id: I8ba901fe7c978aad43b85a860c71b33bfbff2ff5 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57462 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/intel/adlrvp_m: correct SSD power sequenceSelma Bensaid2021-09-302-4/+11
| | | | | | | | | | | | This is to fix SSD detectiong failure in warm boot observed on ADL-M RVP. This patch implements the coreect power sequence: SSD_PREST Low - SSD_PWR_EN High - SSD_PREST High Signed-off-by: Selma Bensaid <selma.bensaid@intel.com> Change-Id: If6f9fc17a30c28c2948809cdbade9919d4ddd6c5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58027 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
* mb/intel/adlrvp: Update Rcomp target value for DDR4 RVP SKUSubrata Banik2021-09-301-2/+2
| | | | | | | | | | | | | | Update to recommended Rcomp drive strength value for DDR4 as per MRC team's input. Additionally, add space around the `targets` array. Change-Id: Ied63913db94b2e52ab394a66c70f7edfd507d99a Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58036 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/intel/adlrvp, mb/google/brya: Add ADLP 242 PLx configurationsTracy Wu2021-09-291-0/+1
| | | | | | | | | | | | | | Add ADLP 242 sku PLx related settings, which follow the settings of ADLP 282 sku (both are 15w). BUG=b:201253904 TEST=USE='fw_debug' emerge-brya intel-adlfsp coreboot chromeos-bootimage Change-Id: If9b60893ab3e2c4a88e7d2cf45223c5fbce6f847 Signed-off-by: Tracy Wu <tracy.wu@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57992 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
* mb/intel/kblrvp: Clean up dsdt.aslFelix Singer2021-09-271-7/+2
| | | | | | | | | | | | Move includes using library paths to the top and remove unnecessary comments. Also, get rid of that unnecessary _SB scope. Use an absolute path for the PCI0 device instead. Change-Id: Ibb63f3ecd9cfbb6f564e0a9968c2776c25d84f79 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57856 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* mb/intel/kunimitsu: Clean up dsdt.aslFelix Singer2021-09-271-7/+2
| | | | | | | | | | | Move includes using library paths to the top and remove unnecessary comments. Change-Id: I42458f16a323d3e37d0ee1bd8335e1f8d0e1fadc Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57851 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* mb/intel/saddlebrook: Clean up dsdt.aslFelix Singer2021-09-271-14/+6
| | | | | | | | | | | | Move includes using library paths to the top and remove unnecessary comments. Also, get rid of that unnecessary _SB scope. Use an absolute path for the PCI0 device instead. Change-Id: I730cd3eeffff60b3b569bfb748febbdc8ca85990 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57850 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* mb/intel/adlrvp: Switch to using device pointersFurquan Shaikh2021-09-242-9/+4
| | | | | | | | | | | | This change replaces the device tree walks with device pointers by using alias for dptf_policy device. Change-Id: I02ca63ac2cc1b8ed2f5a381b3824c9beff7f33ec Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57870 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/intel/adlrvp_m: Enable HECI1 communicationzhixingma2021-09-231-0/+3
| | | | | | | | | | | | | | The patch enables HECI1 interface to allow OS applications to communicate with CSE. TEST=Verify PCI device 0:16.0 exposed in the lspci output Signed-off-by: zhixingma <zhixing.ma@intel.com> Change-Id: Ifd338345caa183f03097f1003080992da70296ff Reviewed-on: https://review.coreboot.org/c/coreboot/+/57813 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
* broadwell boards: Reflow USB2 parameter statementsAngel Pons2021-09-171-16/+8
| | | | | | | | | | | These statements fit on a single line. Reflow them to ease future works. Change-Id: Ie18e9a00f67b999fdcedcab3c28b68e34bc93da4 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55814 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
* mb/intel/adlrvp: Override Type-C IOM GPIO Pads based on Board IDSubrata Banik2021-09-161-1/+37
| | | | | | | | | | | | | | | | | | | | | | | This patch allows ADL-RVP mainboards to set AUX GPIO PADs based on the board id value. Various ADL-P and ADL-M RVPs SKUs demand different GPIO AUX programming hence, this patch implements a helper function inside `adlrvp` mainboard to override devicetree chip config. Note: Different ADL-P/M SKUs (LP4/LP5/DDR4/DDR5) don't have dedicated devicetree for overrides hence, board id is being used for unique SKU identification. Additionally, skip AUX GPIO PAD filling up for Windows SKUs. TEST=Able to override AUX GPIO PADs based on ADL-P RVP board id. Change-Id: I2f0a37c7a8bd69af715551df2a93e6eed89e954a Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57532 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/intel/adlrvp_p: Enable TCSS USB ports device pathMeera Ravindranath2021-09-141-0/+19
| | | | | | | | | | TEST=Boot RVP, ensure Type C ports operate correctly. Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Change-Id: Iadc0df2e6e29a5afbcbb7db1ae0be6546dbcdc1a Reviewed-on: https://review.coreboot.org/c/coreboot/+/57274 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
* mb/intel/tglrvp: Enable USB4 resources using SoC KconfigFurquan Shaikh2021-09-131-15/+1
| | | | | | | | | | | | | This change uses the newly added `SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES` Kconfig to enable USB4 resources and drops the configuration in mainboard. Change-Id: I707c5d63ea8c58e72126fe0d319ba81a99221ba5 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57127 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/adlrvp: Add new ADL P board variant for MCHP1727Brandon Breitenstein2021-09-133-3/+46
| | | | | | | | | | | | | | | Add new board variant to enable MCHP1727 Modular EC Card on RVP BUG=b:179214042 BRANCH=none TEST=emerge brya and verify that adlrvp_p_mchp images boot Change-Id: I9dc96ad5c5db21fedbe480d19fcae8434d3bd169 Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56839 Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* cannonlake mainboards: Set PMC as hidden in devicetreeTim Wawrzynczak2021-09-101-1/+1
| | | | | | | | | | | | | | | | | | | | | | FSP-S hides the PMC from the PCI bus when it runs, but there are still initialization steps coreboot programs for the PMC. Therefore, change all of the cannonlake mainboards to set the PMC as hidden in the devicetree, which means the device will be skipped during enumeration, but device callbacks are still issued as if the device were enabled. TEST=Ran full patch train on google/dratini, disassembled SSDT and the PEPD device matches what is in pep.asl. Also verified via dmesg that the INT33A1 device is still initialized by the kernel. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ib4a20ce9075ce7653388a5d3e281fe774bf89355 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56008 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
* mb/intel/shadowmountain: Enable SaGv supportV Sowmya2021-09-061-2/+1
| | | | | | | | Signed-off-by: V Sowmya <v.sowmya@intel.com> Change-Id: I15203920546363466eef567136821b59dda763b0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54648 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/intel: Drop unused `GPIO_MEM_CONFIG_.` definesAngel Pons2021-09-062-12/+0
| | | | | | | | | | | These defines are copy-paste leftovers from Kunimitsu. However, neither Saddle Brook nor KBLRVP use memory-down, so drop the unneeded defines. Change-Id: I396aeaa634f619be7be0ee97c0cab1c682f53ff2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57231 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
* mb/intel/kblrvp: Drop redundant overridetree lineAngel Pons2021-09-061-1/+0
| | | | | | | | | | The I2C #5 device is already disabled in the devicetree. Change-Id: Ia4970dc07ef57e8184bce395a446974a22eddb08 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57230 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
* mb/intel/kblrvp: Mark disabled SerialIO devices as `off`Angel Pons2021-09-062-6/+4
| | | | | | | | | | | | Disable devicetree devices disabled in the `SerialIoDevMode` array. These devices get disabled by FSP-S, and coreboot doesn't see them. Change-Id: I8dbb45c96eae5188e5999df9a458f06f6b196adf Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57229 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Nico Huber <nico.h@gmx.de>
* mb/intel/kblrvp: Do not use Legacy mode for UART #2Angel Pons2021-09-061-1/+1
| | | | | | | | | | | | | | | | | | | | All KBLRVP variants select the `INTEL_LPSS_UART_FOR_CONSOLE` Kconfig option and set `UART_FOR_CONSOLE` to `2`, so that UART #2 is used as coreboot console. However, the LPSS console driver requires the LPSS UART to be memory-mapped (and not I/O-mapped, like Super I/O UARTs). KBLRVP variant RVP8 uses `PchSerialIoLegacyUart` for UART #2, which makes FSP-S configure UART #2 in legacy, I/O-mapped mode. This most likely results in the UART console not working after FSP-S has run. This change updates RVP8 to use `PchSerialIoSkipInit` for UART #2, like the other KBLRVP variants do. Change-Id: Ic5c78f5895fe1dd5e7be6ef7aec3de6940dd2475 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57228 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
* mb/intel/kblrvp: Drop commented-out SD card configAngel Pons2021-09-061-3/+0
| | | | | | | | | | | This is most likely a copy-paste remnant, and will never be needed for RVP8: the SDXC device does not exist on PCH-H (and RVP8 uses a PCH-H). Change-Id: I69059a88dcdb032beaab5fb03981dccbae0db02e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57227 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
* mb/intel/kblrvp: Disable I2C #4 and #5 on PCH-HAngel Pons2021-09-062-6/+3
| | | | | | | | | | | | | The I2C #4 and I2C #5 devices do not exist on PCH-H. Disable the devices using the PCH-H variants' overridetrees (the base devicetree enables I2C #4), set the `SerialIoDevMode` entries to `PchSerialIoDisabled` and drop inapplicable I2C #4 voltage settings. Change-Id: I56f34fa2004993d2123ccd5c1008fd71682ec2bd Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57226 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* soc/intel/adl: Move USB4 hotplug Kconfig to commonFurquan Shaikh2021-09-061-1/+1
| | | | | | | | | | | | | | | | This change adds a new Kconfig `SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES` that can be selected by mainboard to reserve hotplug resources for USB4 at the SoC level. `ADL_ENABLE_USB4_PCIE_RESOURCES` is dropped from soc/intel/alderlake and instead the newly added Kconfig is now used. This new Kconfig is added so that the same config can be used across different platforms. In following changes, this Kconfig is utilized by TGL as well. Change-Id: Id7c359a0e255c43c2732f6cbe287bc7da14a46e3 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57124 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* mb/intel/adlrvp: Clean up the print messageBora Guvendik2021-09-051-1/+1
| | | | | | | | | | TEST=none Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: I6346b087543217c78f87751051a4f38b23c566d2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57389 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
* mb/intel/leafhill,minnow3: remove FSP_M_CBFS and FSP_S_CBFS overrideFelix Held2021-09-052-16/+0
| | | | | | | | | | | The overrides set the options to the same value as drivers/intel/fsp2_0/ Kconfig does, so drop the overrides. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I53922786382a2e7d29b3df560a1998f41e1d2ea8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57350 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* mb/intel/leafhill,minnow3: remove FSP_M_FILE and FSP_S_FILE overrideFelix Held2021-09-052-20/+0
| | | | | | | | | | | | | | | Normally, selecting FSP_USE_REPO will select FSP_FULL_FD which then will configure the proper paths for FSP_M_FILE and FSP_S_FILE. The override in these two boards caused FSP_M_FILE and FSP_S_FILE being empty despite ADD_FSP_BINARIES being selected by FSP_USE_REPO which is an invalid case that needs to be avoided, so remove the board-level override of those two options. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I20c8cebea8327d59f0f33d05b824a74bf2121f4b Reviewed-on: https://review.coreboot.org/c/coreboot/+/57347 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* mb/intel/leafhill,minnow3: remove ADD_FSP_BINARIES config overrideFelix Held2021-09-052-8/+0
| | | | | | | | | | | | | | The ADD_FSP_BINARIES override in the mainboard's Kconfig caused this option to not be selected when FSP_USE_REPO is selected. Remove the override to fix this problem. These two boards are the only ones in tree that had an override for this option, so now the ADD_FSP_BINARIES option is only defined in drivers/intel/fsp2_0/Kconfig. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I23439f3134eef9460625addbff7efd64c5f65ae5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57346 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* mb/intel/adlrvp_m: Fix TPM IRQ conflict with I2C4Selma Bensaid2021-09-031-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add TPM IRQ config to gpio_m.c, so the TPM IRQ is not allocated to I2C4. BUG=NA BRANCH=None TEST= boot to os and check cat /proc/interrupts, cr50 SPI interrupt is assigned and does not conflict with I2C. CPU0 CPU1 CPU2 CPU3 CPU4 CPU5 CPU6 CPU7 CPU8 CPU9 CPU10 CPU11 0: 36 0 0 0 0 0 0 0 0 0 0 0 IO-APIC 2-edge timer 1: 0 0 0 0 0 0 0 0 9 0 0 0 IO-APIC 1-edge i8042 8: 0 0 0 0 0 0 0 0 0 0 0 0 IO-APIC 8-edge rtc0 9: 0 0 0 0 0 0 0 0 0 0 0 0 IO-APIC 9-fasteoi acpi 14: 0 0 0 0 0 0 0 0 0 0 0 0 IO-APIC 14-fasteoi INTC1055:00 16: 0 0 0 0 0 0 0 0 0 0 4 0 IO-APIC 16-fasteoi intel-ipu6 22: 0 13 0 0 0 0 0 0 0 0 0 0 IO-APIC 22-fasteoi idma64.4, i801_smbus, ttyS0 37: 0 0 0 0 0 0 0 0 0 0 0 0 IO-APIC 37-fasteoi idma64.0, i2c_designware.0 38: 0 0 0 0 0 0 0 0 0 0 4 0 IO-APIC 38-fasteoi idma64.1, i2c_designware.1 41: 0 0 0 0 2274 0 0 0 0 0 0 0 IO-APIC 41-edge cr50_spi 42: 0 0 0 0 0 0 0 0 0 0 0 0 IO-APIC 42-fasteoi idma64.2, i2c_designware.2 43: 4 0 0 0 0 0 0 0 0 0 0 0 IO-APIC 43-fasteoi idma64.3, i2c_designware.3 Signed-off-by: Selma Bensaid <selma.bensaid@intel.com> Change-Id: Id0f3885dec5a6f635254c233709090321491c739 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57102 Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-04 17:11:45 +0000