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* arch/x86: consolidate HPET base address definitionsFelix Held2022-02-252-2/+4
* mb/intel/adlrvp_n: Update devicetreeKrishna Prasad Bhat2022-02-212-168/+20
* mb/intel/adlrvp: Fix vbt loading errorLean Sheng Tan2022-02-101-0/+3
* mb/intel/galileo/reg_access.c: Remove duplicated "ERROR" in log messagesElyes HAOUAS2022-02-081-4/+2
* treewide: Remove "ERROR: "/"WARN: " prefixes from log messagesJulius Werner2022-02-071-1/+1
* mb/**/Kconfig: Properly override `IGNORE_IASL_MISSING_DEPENDENCY`Angel Pons2022-01-314-16/+12
* IASL: Ignore IASL's "Missing dependency" warningElyes HAOUAS2022-01-2813-0/+42
* soc/intel/adl: Replace dt `HeciEnabled` by `HECI1 disable` configSubrata Banik2022-01-254-12/+0
* mb/intel/adlrvp: Add missing CAM1 RST GPIO for ADL-NUsha P2022-01-221-0/+2
* soc/intel/ehl: Replace dt `HeciEnabled` by `HECI1 disable` configSubrata Banik2022-01-211-3/+0
* mb/intel/adlrvp: Add wake events for AC connect/disconnectKrishna Prasad Bhat2022-01-181-1/+3
* mb/intel/adlrvp_n: Configure EC in RW GPIOKrishna Prasad Bhat2022-01-182-5/+4
* mb/google/brya/variants/*: Add cpu pcie rp flagsTracy Wu2022-01-172-0/+4
* src: Remove unused <cbfs.h>Elyes HAOUAS2022-01-171-1/+0
* soc/intel/skl: Replace dt `HeciEnabled` by `HECI1 disable` configSubrata Banik2022-01-165-2/+9
* soc/intel/jsl: Replace dt `HeciEnabled` by `HECI1 disable` configSubrata Banik2022-01-141-0/+3
* soc/intel/tgl: Replace dt `HeciEnabled` by `HECI1 disable` configSubrata Banik2022-01-142-6/+0
* soc/intel/tigerlake: add devicetree option PcieRpSlotImplementedMichael Niewöhner2022-01-142-0/+8
* soc/intel/alderlake: Factor out A0 stepping workaroundAngel Pons2022-01-112-86/+1
* src/mainboard/{hp,intel}: Remove unused <console/console.h>Elyes HAOUAS2022-01-101-1/+1
* src/mb: Remove unused <string.h>Elyes HAOUAS2022-01-041-1/+0
* src: Use 'stdint.h' when appropriateElyes HAOUAS2022-01-011-1/+0
* src: Drop duplicated includesElyes HAOUAS2022-01-011-1/+0
* mb/google/taniks,vell;mb/intel/adlrvp_n_ext_ec: fix build errorFelix Held2021-12-241-6/+6
* mb/intel/adlrvp: Configure GPIOs for Alder Lake-NUsha P2021-12-243-0/+250
* mb: Remove dot from end of non-sentence commentPaul Menzel2021-12-236-6/+6
* mb: Add space before closing comment block keywordPaul Menzel2021-12-237-7/+7
* ChromeOS: Refactor ACPI CNVS generationKyösti Mälkki2021-12-2313-47/+0
* mb/intel/adlrvp_n: Add support for ADL-N LP5 RVPKrishna Prasad Bhat2021-12-235-1/+100
* drivers/intel/pmc_mux/conn: Change usb{23}_port_number fields to device pointersReka Norman2021-12-236-26/+26
* mb/intel/{adlrvp,sm}: Remove unused header `helpers.h`Subrata Banik2021-12-234-4/+0
* mainboard: Fix comment about early GPIOsAngel Pons2021-12-196-6/+6
* mb/intel/adlrvp_n: Add initial code for adl-n variant boardKrishna Prasad Bhat2021-12-155-2/+516
* Denverton-NS boards: Drop useless `thermal.asl`Angel Pons2021-12-152-10/+0
* mb/intel/adlrvp: Add support for external clock bufferSubrata Banik2021-12-102-0/+39
* soc/intel/tigerlake: Hook up DPTF device to devicetreeFelix Singer2021-12-092-6/+0
* soc/intel/tigerlake: Hook up SMBus device to devicetreeFelix Singer2021-12-092-2/+0
* mb/google/brya/var/brask: Set vGPIO reset typeKane Chen2021-12-031-80/+80
* soc/intel/alderlake: Add Kconfigs for all PCH typesAngel Pons2021-12-022-3/+4
* mb/intel/adlrvp: Use dedicated VBT files for ADL-MBernardo Perez Priego2021-11-221-2/+3
* mb/intel/adlrvp: Enable CPU PCIe RP 2Meera Ravindranath2021-11-191-0/+6
* mb/intel/adlrvp: Fix sagv point3 clipping to 4800MhzBora Guvendik2021-11-171-2/+2
* mb/intel/adlrvp: Fix S0ix regressionMeera Ravindranath2021-11-171-21/+0
* Reland "vboot_logic: Set VB2_CONTEXT_EC_TRUSTED in verstage_main"Hsuan-ting Chen2021-11-158-0/+44
* mb/google,intel: Add ChromeOS GPIOs to onboard.hKyösti Mälkki2021-11-126-14/+40
* ChromeOS: Replace with or add <types.h>Kyösti Mälkki2021-11-1122-9/+22
* intel/strago: Fix some CHROMEOS guardsKyösti Mälkki2021-11-112-8/+7
* Rename ECAM-specific MMCONF KconfigsShelley Chen2021-11-102-2/+2
* mb/intel/adlrvp: Set same size for CSE_RW and ME_RW_A/BReka Norman2021-11-091-2/+2
* pci_mmio_cfg: Always use pci_s_* functionsNico Huber2021-11-091-1/+1
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