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path: root/src/mainboard/lenovo/t60
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* mb/{i945,ich7}: Remove redundant write on V0CTLElyes HAOUAS2019-11-171-3/+0
* nb/intel/i945: Initialize console in bootblockArthur Heymans2019-11-152-1/+6
* nb/intel/i945: Move boilerplate romstage to a common locationArthur Heymans2019-11-151-68/+24
* sb/intel/i82801gx: Add common early codeArthur Heymans2019-11-141-41/+5
* sb/intel/i82801gx: Add common LPC decode codeArthur Heymans2019-11-122-17/+8
* ec/lenovo/h8: Make dock init in ramstage fully mainboard-specificBill XIE2019-11-121-1/+0
* src/mb: Remove redundant message befor 'system_reset()'Elyes HAOUAS2019-11-111-1/+0
* soc/intel/{IA-CPU/SOC}: Move sleepstates.asl into southbridge/intel/common/acpiSubrata Banik2019-11-011-1/+1
* mb/(ich7): Use macro instead of magic numberElyes HAOUAS2019-10-271-4/+4
* mb/lenovo/{t60,r60}: Add ThinkPad R60 support as variant boardMaccraft2019-10-255-17/+36
* mb/lenovo/{t60,x201,x60}/smihandler: Remove SMM reinitializationPeter Lemenkov2019-10-251-14/+0
* mb/lenovo/*/acpi: Remove unused include smi.hPeter Lemenkov2019-10-221-1/+0
* sb/intel/i82801gx: Move CIR init to a common placeArthur Heymans2019-10-111-25/+1
* mb/lenovo/t60: Switch to override treePeter Lemenkov2019-10-085-257/+135
* mb/lenovo/{t60,z61t}: Convert to variant boardPeter Lemenkov2019-10-089-5/+275
* soc/intel: Use common romstage codeKyösti Mälkki2019-08-261-1/+1
* cpu/intel: Enter romstage without BISTKyösti Mälkki2019-08-181-7/+2
* mainboards: Remove floating __PRE_RAM__ commentsKyösti Mälkki2019-08-181-2/+0
* intel/i945: Fix udelay() prototypesKyösti Mälkki2019-07-131-0/+1
* arch/x86: Avoid HAVE_SMI_HANDLER conditional with smm-classKyösti Mälkki2019-07-091-1/+1
* mb/lenovo/t60: Align ACPI C-state across the similar boardsPeter Lemenkov2019-07-071-1/+1
* intel/945 boards: Use smp_write_pci_intsrc()Kyösti Mälkki2019-06-251-15/+15
* mb/lenovo/t60/romstage: Remove unused includePeter Lemenkov2019-06-191-1/+0
* nb/i945: Drop CHANNEL_XOR_RANDOMIZATION selectionElyes HAOUAS2019-06-141-1/+0
* sb/intel/i82801gx: Detect if the southbridge supports AHCIArthur Heymans2019-06-061-1/+0
* sb/intel/i82801gx: Include chip.h directlyArthur Heymans2019-06-051-0/+1
* mb/lenovo: Unify thermal threshold handlingPeter Lemenkov2019-05-252-3/+38
* src: Remove unused include <halt.h>Elyes HAOUAS2019-05-061-1/+0
* src/mb: Use system_reset()Elyes HAOUAS2019-04-291-2/+2
* sb/intel/i82801gx: Use SOUTHBRIDGE_INTEL_COMMON_PMCLIBPatrick Rudolph2019-04-131-0/+1
* nb/intel/i945: Use DEBUG_RAM_SETUPKyösti Mälkki2019-03-241-3/+2
* src: Use 'include <string.h>' when appropriateElyes HAOUAS2019-03-202-2/+0
* mb/(ICH7): Remove initialization already done at early_init.cElyes HAOUAS2019-03-181-1/+0
* src: Drop unused include <arch/acpi.h>Elyes HAOUAS2019-03-061-1/+0
* device/pnp: Add header files for PNP opsKyösti Mälkki2019-03-041-0/+1
* arch/io.h: Add missing includesKyösti Mälkki2019-03-041-0/+1
* arch/x86/acpi: Remove obsolete acpi_gen_regaddr resv fieldElyes HAOUAS2019-03-041-3/+3
* device/pci: Fix PCI accessor headersKyösti Mälkki2019-03-012-0/+2
* cpu/intel: Rename socket_mFCPGA478 to socket_mNico Huber2019-02-282-2/+2
* nb/intel/i945: Use parallel MP initArthur Heymans2019-01-232-2/+0
* mb/lenovo/[xtz]60: Introduce and use RCBA64 macroPeter Lemenkov2019-01-141-4/+2
* mb/lenovo/*/romstage: Use macros instead of magic numbersPeter Lemenkov2019-01-141-6/+6
* cpu/intel: Use the common code to initialize the romstage timestampsArthur Heymans2019-01-091-5/+0
* sb/intel/i82801gx: Autodisable functions based on devicetreeArthur Heymans2019-01-081-3/+1
* device: Use pcidev_on_root()Kyösti Mälkki2019-01-061-1/+1
* mb/*/*/Kconfig: Remove useless commentElyes HAOUAS2018-11-281-1/+1
* sb/intel/i82801gx: Use common Intel SMM codeArthur Heymans2018-11-271-1/+1
* mb: Set coreboot as DSDT's manufacturer model IDElyes HAOUAS2018-11-231-2/+3
* ACPI: Fix DSDT's revision fieldElyes HAOUAS2018-11-211-1/+1
* src: Add required space after "switch"Elyes HAOUAS2018-11-191-2/+2
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