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* mb: Move timestamp_add_now to northbridge x4xElyes HAOUAS2019-01-101-7/+0
| | | | | | | | Change-Id: Iacbee658a4049e1c13a120dbc21425ffb6a1cabb Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/30750 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* cpu/intel: Use the common code to initialize the romstage timestampsArthur Heymans2019-01-096-27/+0
| | | | | | | | | | | | | The initial timestamps are now pushed on the stack when entering the romstage C code. Tested on Asus P5QC. Change-Id: I88e972caafff5c53d8e68e85415f920c7341b92d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30670 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
* sb/intel/i82801gx: Autodisable functions based on devicetreeArthur Heymans2019-01-084-11/+3
| | | | | | | | | | | This removes the need to synchronize the devicetree and the romstage writing to FD. Change-Id: I83576599538a02d295fe00b35826f98d8c97d1cf Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30244 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* nb/intel/gm45: Remove the C native graphic initArthur Heymans2019-01-072-2/+0
| | | | | | | | | | | | | | | Libgfxinit provides a better alternative to the native C init. While libgfxinit mandates an ada compiler, we want to encourage use of it since it is in much better shape and is actually maintained. This way libgfxinit also gets build-tested by Jenkins. Change-Id: I540cf08cef6ff7825694ebfa36e2e6437916e657 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/27016 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* src: Use "foo **bar" instead of "foo ** bar"Elyes HAOUAS2019-01-071-1/+1
| | | | | | | | | Change-Id: I8260424ee243c06827f2b5939e1568e52539b282 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/30624 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
* device: Use pcidev_on_root()Kyösti Mälkki2019-01-067-9/+9
| | | | | | | | | | Change-Id: Icf34b39d80f6e46d32a39b68f38fb2752c0bcebc Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/26484 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Piotr Król <piotr.krol@3mdeb.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* mb/lenovo/x200: Remove RCBA replayArthur Heymans2019-01-031-33/+0
| | | | | | | | | | | | This either sets unwanted or unnecessary settings. Tested. Everything still works fine. Change-Id: I0f552dea1b37cdc17c9dd26a0294b59063cdc2be Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30402 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
* src/mainboard: Use smm-$(CONFIG_HAVE_SMI_HANDLER)Elyes HAOUAS2019-01-034-4/+4
| | | | | | | | | | Use smm-$(CONFIG_HAVE_SMI_HANDLER) instead of smm-y Change-Id: I0f91bc3e6c8ab31d837ab89af62d700b35c1e01b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/30485 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* mb: Remove duplicated ENABLE_VMXElyes HAOUAS2019-01-034-4/+0
| | | | | | | | | | | ENABLE_VMX is CPU specific and it is already enabled here: src/cpu/intel/common/Kconfig Change-Id: I130738aa3758a9212bab10f90edb7b2ab6830597 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/30605 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* intel/gma/Makefile.inc: Add a helper function to add VBT binariesArthur Heymans2018-12-281-6/+0
| | | | | | | | | | | This adds a convenient helper function to add vbt binaries to cbfs. Change-Id: I80d9b3421f6e539879ad4802119fe81d7ea1e234 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30430 Reviewed-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* arch/x86: Drop spurious arch/stages.h includesKyösti Mälkki2018-12-281-1/+0
| | | | | | | Change-Id: I3b9217a7d9a6d98a9c5e8b69fe64c260b537bb64 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30388 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* smsc/sch5147: Implement ACPI handling of a few LDNArthur Heymans2018-12-191-1/+25
| | | | | | | | Change-Id: Ide30a7396b6248e2037041e177dc8514533718a4 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30240 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* mb/lenovo/thinkcentre_a58: Add mainboardArthur Heymans2018-12-1919-0/+751
| | | | | | | | | | | | | | | | | | | | | | | | | The following was tested: - Using two DDR2 DIMMs - S3 sleep and resume (on SeaBIOS it needs sercon disabled) - Ethernet NIC - Libgfxinit (native res and textmode) - SATA - USB - 800MHz FSB CPU (Pentium(R) E5200 @ 2.50GHz) - PS2 Keyboard - Serial output TODO: - Add ACPI code for SuperIO devices (done in a follow-up patch) - Add documentation TESTED with SeaBIOS (sercon disabled), Linux 4.19 Change-Id: I483e1143e4095b8a58fed142d31ca7f233a854e2 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30239 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mainboard: Remove useless include <device/pci_ids.h>Elyes HAOUAS2018-12-193-3/+0
| | | | | | | | Change-Id: I4ee3cc42302c44dc80ae1f285579a4d1775aec16 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/30199 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
* mb/intel/x200: Add data.vbtArthur Heymans2018-12-114-0/+30
| | | | | | | | | | | | | | There are 2 vendor BIOS's for the Lenovo X200 with the difference being the settings in the VBT blob to accommodate different backlight frequencies. Linux however sticks with the setting set by the firmware. Tested on Lenovo X200 with CCFL backlight. Change-Id: I4c4a7011ce03cdd511fa2e2160c2f006ba2707ba Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/29904 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mainboard/lenovo/t430s: Add ThinkPad T431s as a variantBill XIE2018-12-0722-220/+750
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The code is based on autoport and that for T430s Tested: - CPU i5-3337U - Slotted DIMM 2GiB - Soldered RAM 4GiB from samsung (There may be more models here) - Camera - pci-e and usb2 on M.2 slot with A key for wlan - sata and usb2 (no superspeed components) on M.2 slot with B key for wwan - On board SDHCI connected to pci-e - USB3 ports - libgfxinit-based graphic init - NVRAM options for North and South bridges - Sound - Thinkpad EC - S3 - TPM1 on LPC - EHCI debug on SSP2 (USB3 port on the left) - Linux 4.9.110-3 within Debian GNU/Linux stable, loaded from Linux payload (Heads), Seabios may also work. Not tested: - Fingerprint reader on USB2 (not present on mine) - Keyboard backlight (not present on mine) - "sticky_fn" flag in nvram Not implemented yet: - Fn locking in nvram (may not be identical to "sticky_fn") - C-based native graphic init (since T431s has eDP instead of LVDS) - Detecting the model of Soldered RAM at runtime, and loading the corresponding SPD datum (3 observed) from CBFS (the mechanism may be similar to that on x1_carbon_gen1 and s230u, but I do not know how to find gpio ports for that, and SPD data stored in vendor firmware.) Change-Id: Ic8062cacf5e8232405bb5757e1b1d063541f354a Signed-off-by: Bill XIE <persmule@gmail.com> Reviewed-on: https://review.coreboot.org/c/30021 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
* lenovo/h8,thinkpads: Re-do USB Always OnNathaniel Roach2018-12-0612-22/+2
| | | | | | | | | | | | | | | | | | | | | | | | | Re-write the UAO handling code as it had stopped working (#171) (the flag was not getting read from the RTC properly in SMM) Remove the SMM code as it's not needed (but EC flag won't be set upon entering S3 now) Set the EC flags on boot the same way other flags are set Document bitwise operators for clarity Propagate changes to other Thinkpads (updated X201 to have 2 bits for the flag as it only had 1) Per Nicola Corna's previous commits, 0x0d is set for "AC only" "AC only" does exhibit different behaviour - the USB port is turned on a few seconds after entering S3, rather than < 1 sec, regardless of AC status Tested on X220 Change-Id: If812cd1ef8fb1a24d7fadbe834f574b40cbcd56a Signed-off-by: Nathaniel Roach <nroach44@gmail.com> Reviewed-on: https://review.coreboot.org/c/29565 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
* mb/lenovo/t520/romstage: Remove unused includesPeter Lemenkov2018-12-061-6/+0
| | | | | | | | | | Tested - Lenovo t520 still builds fine with this patch. Change-Id: I82492c071ca760f0790b992acbdb86021f470cfe Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/30043 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
* mb/lenovo/x201/dsdt: Remove duplicated includePeter Lemenkov2018-12-051-1/+0
| | | | | | | | | | Change-Id: Ifb08c903e19ef4e93bdc9cbc9844cb1888a8d2fa Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/29811 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
* mb/lenovo/*/dsdt: Rearrange definesPeter Lemenkov2018-12-052-2/+4
| | | | | | | | | | | | | Sort mainboard-specific defines in the same order as in all other Lenovo boards. This is a purely cosmetic change which just makes diff between boards smaller. Change-Id: I4e379bb727b356fc6010e93de492f6d73f97a750 Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/29544 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
* mb/lenovo/*/dsdt: Move mainboard-specific defines out of ec.aslPeter Lemenkov2018-12-054-12/+12
| | | | | | | | | | | | | | Most Lenovo mainboards define their own specific defines in dsdt.asl. Let's make it consistent across all Lenovo mainboards. Tested - builds fine. Change-Id: I03fbeb09b25e42af2dfbb220c0f726e6abb73673 Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/29543 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
* sb/intel/common: Create a common PCH finalise implementationTristan Corrick2018-12-031-0/+1
| | | | | | | | | | | | | | | | | | | | | | The common finalise code is used by bd82x6x, Lynx Point, and Ibex Peak. Lynx Point now benefits from being able to write-protect the flash chip. For Lynx Point, writing the SPI OPMENU now happens in ramstage, as done in bd82x6x. Tested on an ASRock H81M-HDS (Lynx Point). When write-protection is configured, flashrom reports all flash regions as read-only, and does not manage to alter the contents of the flash chip. Also tested on an ASUS P8H61-M LX (Cougar Point). Everything seems to work as before. Change-Id: I781082b1ed507b00815d1e85aec3e56ae5a4bef2 Signed-off-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-on: https://review.coreboot.org/c/29977 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* cpu/intel/common: Use a common acpi/cpu.asl fileArthur Heymans2018-11-3013-13/+13
| | | | | | | | | Change-Id: Ifa5a3a22771ff2e0efa14fb765603fd5e0440d59 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/29894 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: David Guckian
* mb/*/*/Kconfig: Remove useless commentElyes HAOUAS2018-11-2817-17/+17
| | | | | | | | | | | Change-Id: Ibdff50761a205d936b0ebe067f418be0a2051798 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/29871 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hellsenberg <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: David Guckian Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
* sb/intel/i82801gx: Use common Intel SMM codeArthur Heymans2018-11-273-3/+3
| | | | | | | | | | | | | | | | | | Use the common Intel code to set up smm and the smihandler. This is expected to break S3 resume and other smihandler related functionality as this code is meant to be used with CONFIG_SMM_TSEG. Platforms (i945, pineview, x4x) using this southbridge will adapt the CONFIG_SMM_TSEG codepath in subsequent patches. Tested on Intel D945GCLF, still boots fine but breaks S3 resume support because it hangs on SMI. Change-Id: If7016a3b98fc5f14c287ce800325084f9dc602a0 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/25594 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* mb: Set coreboot as DSDT's manufacturer model IDElyes HAOUAS2018-11-2319-38/+58
| | | | | | | | | | | | | | Field 'OEMID' & "OEM Table ID" are related to DSDT table not to mainboard. So use macro to set them respectvely to "COREv4" and "COREBOOT". Change-Id: I060e07a730e721df4a86128ee89bfe168c69f31e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/29790 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: David Guckian
* ACPI: Fix DSDT's revision fieldElyes HAOUAS2018-11-2118-18/+18
| | | | | | | | | | | | | DSDT revision is =1 for ACPI v1 and =2 for greater ACPI version. This will cause the AML interpreter to use 32-bit integers and math if the version is 1, and 64-bit if the version is >=2. Current spec version is 2 for ACPI 6.2-a. Change-Id: I77372882d5c77b7ed52dcdd88028403df6f6fa7f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/29626 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* src: Add required space after "switch"Elyes HAOUAS2018-11-193-6/+6
| | | | | | | | Change-Id: I85cf93e30606bc7838852bd300a369e79370629a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29623 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* src: Remove unneeded include <cbfs.h>Elyes HAOUAS2018-11-161-1/+0
| | | | | | | | Change-Id: Iab0bd1c5482331a0c048a05ab806bf5c4dbda780 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29303 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* src/mainboard: Remove unused "HW_MEM_HOLE_SIZE_AUTO_INC"Elyes HAOUAS2018-11-161-4/+0
| | | | | | | | Change-Id: I10e89de270a20dbd28647e8b0f8a2425c515b350 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29589 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* mb/{lenovo,roda}: Remove DISPLAY_DEVICE_2_IS_LCD_SCREEN macroPeter Lemenkov2018-11-162-2/+0
| | | | | | | | | | | This macro is no longer used since commit dd2bc3f8 with Change-Id I556769e5e28b83e7465e3db689e26c8c0ab44757 ("igd.asl rewrite"). Change-Id: Iabf927d8462673cb96851c01318d826d4c422e0d Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/29537 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes HAOUAS <ehaouas@noos.fr>
* src: Remove unneeded include <lib.h>Elyes HAOUAS2018-11-1610-10/+0
| | | | | | | | Change-Id: I801849fb31fe6958e3d9510da50e2e2dd351a98d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29304 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* src: Get rid of duplicated includesElyes HAOUAS2018-11-161-1/+0
| | | | | | | | Change-Id: I252a1cd77bf647477edb7dddadb7e527de872439 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29582 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
* src: Remove unneeded include <pc80/keyboard.h>Elyes HAOUAS2018-11-161-1/+0
| | | | | | | | Change-Id: I0dcdfb1fa782c7936a19de11adcf17387f49d9db Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29309 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
* mb/*/*/Kconfig: Use CONFIG_VARIANT_DIR for devicetreePeter Lemenkov2018-11-162-4/+2
| | | | | | | | | Change-Id: Ic9620cfa1630c7c085b6c244ca80dc023a181e30 Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/29595 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
* mb/lenovo/x60/dsdt: Remove unused includePeter Lemenkov2018-11-161-2/+0
| | | | | | | | | | Tested - builds fine with this patch. Change-Id: I4666a8c9dd0e03ee32770844019dfc032e07e460 Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/29068 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes HAOUAS <ehaouas@noos.fr>
* mb/*/*: Harmonise FD and devicetree on boards featuring ICH7Arthur Heymans2018-11-123-0/+20
| | | | | | | | | | | | | | | On some boards the devicetree and Function Disable register did not match. In this case the FD values are put in the devicetree as these were the values that were actually used in practice. A complete devicetree will make it easier to automatically disable devices in ramstage. Change-Id: I1692ca5f490ea84e2fc520d3f66044ad7514f76e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/27122 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* intel/i945: Factor out ram init time stampsPaul Menzel2018-11-123-6/+0
| | | | | | | | | | | | Instead of having the code for the RAM init time stamps in each mainboard’s `romstage.c`, factor it out to the northbridge code, done in commit 771328f7 (intel/i945: add timestamps in romstage). Change-Id: Ibb699a1fea2f0b1f3c6564d401542d2fb3249f5a Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://review.coreboot.org/17994 Reviewed-by: Elyes HAOUAS <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* src: Remove unneeded include "{arch,cpu}/cpu.h"Elyes HAOUAS2018-11-125-8/+0
| | | | | | | | Change-Id: I17c4fc4e3e2eeef7c720c6a020b37d8f7a0f57a4 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29300 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* mb/lenovo/t400: Improve docking codePatrick Rudolph2018-11-103-41/+80
| | | | | | | | | | | | | | | | | | | | | * Remove dead code * Add support for types 2504 and 2505 * Print dock info at romstage entry * Improve dock disconnect for type 2505 * Move defines into dock.h for future ACPI code * Reduce timeouts according to spec to decrease boot time on error * Fix no docking detection (reduces boot time by 1 second) * Configure GPIO LDN before reading GPIOs * Use Kconfig values instead of fixed defines * Add documentation Tested on Lenovo T500 with docking 2504 and 2505. Change-Id: Ic4510ffadc67da95961cecd51a6d8ed856b3ac99 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/29418 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* mb/{lenovo/x201,packardbell/ms2290}/romstage: Fix commentsPeter Lemenkov2018-11-071-7/+7
| | | | | | | | | | | | | | RCBA address numbers in comments looks wrong and confusing. Let's fix them. This is a cosmetic change since no actual data is added or removed. Change-Id: I0e521acdac17959586bc0af7d8a2f7182f1e6721 Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/29511 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
* mb/lenovo/*/*: Fix non-local header treated as localPeter Lemenkov2018-11-074-4/+4
| | | | | | | | | | | | | See also commit 4ad1446b with Change-Id I036208a111d009620d8354fa9c97688eb4e872ad ("Fix non-local header treated as local"). Change-Id: Idea19b52198e6f46b0da6022558a46246a52f2e7 Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/29501 Reviewed-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/lenovo/x201: Remove unnecessary include - delay.hPeter Lemenkov2018-11-072-2/+0
| | | | | | | | | | Change-Id: Ia997c5188aef0c18d871658209c2d5f718ee2a19 Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/29499 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* mb/lenovo/x201/gpio: Use reset structurePeter Lemenkov2018-11-071-0/+1
| | | | | | | | | | | This structure was defined but never used. Let's use it. Change-Id: I73baf428a7300e64fa486699e82ef62c6a53ea60 Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/29498 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* mainboard: Remove unneeded include <console/console.h>Elyes HAOUAS2018-11-059-9/+0
| | | | | | | | Change-Id: Ib3aafcc586b1631a75f214cfd19706108ad8ca93 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29285 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* amd: Fix non-local header treated as localElyes HAOUAS2018-11-052-3/+3
| | | | | | | | | Change-Id: I0668b73cd3a5bf5220af55c29785220b77eb5259 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29103 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/lenovo/t430: Set USB always on when calling SMI sleepPeter Lemenkov2018-10-291-2/+2
| | | | | | | | | | | | Looks like we must do it in the same way as in l520, t420, t420s, t430s, t520, t530, x201, x220, x230 models. No idea why t430 should be handled differently. Change-Id: Ic4851022267caca267b667b4e3c327838e0a0b66 Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/29031 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/lenovo/t400: Use acpi_s3_resume_allowed()Paul Menzel2018-10-291-10/+10
| | | | | | | | | | | | | | | | | Apply commit 12d681b2 (intel/i945 gm45: Use acpi_s3_resume_allowed()) also to the Lenovo T400. See also commit 42ae0bae with Change-Id I4e1e0ccf2abbe175c0e5ddcbb6ee7bf6afb1ae88 (mb/lenovo/x200: Use acpi_s3_resume_allowed()) Change-Id: I9d4ac711375977a979a8b3e5606e2197847e88de Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/29147 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
* mb/lenovo/x200: Link gpio map instead of including a headerArthur Heymans2018-10-273-8/+4
| | | | | | | | | | | | | | | | | | Linking should allow to link depending on possible future variants. E.g. in Makefile.inc romstage-$(CONFIG_'VARIANT0') += gpio_variant0.c etc. This commit follows up on commit 7dee9745 with Change-Id I88b5ef8e12ac606751952a493f626e1b146e98f7 ("mb/lenovo/x201: Link gpio map instead of including a header"). Change-Id: Ibdb96deafbe422bf50fd2e1fc56a57ae53ccd5a0 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/29286 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* mb/lenovo/*/acpi_tables: Remove comment about IGD displaysPeter Lemenkov2018-10-275-10/+0
| | | | | | | | | | | | | | | IGD display handling was rewritten with commit dd2bc3f8 with Change-Id I556769e5e28b83e7465e3db689e26c8c0ab44757 ("igd.asl rewrite"). These comments were removed as well (with some accidentally left behind). Let's remove them and those who were introduced later with new ports. Change-Id: I8d3e12d0c3b03b0de38e65f36b94ed706fbf893c Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/29271 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-14 10:45:33 +0000