| Commit message (Collapse) | Author | Age | Files | Lines |
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Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ib7beed7218f317bc2352b65a6191ef1cdaa0742d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80597
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
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Change-Id: Ib1bbf22480783f63fc2d729b94251e755d2f1720
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80593
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This port is not connected on the X230, X230i, X230t.
When X230 support was introduced and pei_data was filled in, this port
was disabled, but after commit 3dc12c1e1918
(bd82x6x: Consolidate early native USB init) it has become enabled.
Change-Id: I952193798c0894b256b21d9fb3f238074ff5f0f0
Signed-off-by: Alexei Sorokin <sor.alexei@meowr.ru>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80468
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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There is a modification for the x230 which uses the 2nd DP from the
dock as the integrated panel's connection, which allows using a custom
eDP panel instead of the stock LVDS display.
There are several adapter boards present on the market and all of them
use the same method of enabling the custom eDP panel.
To make this work with coreboot, the internal LVDS connector should be
disabled in libgfxinit. Additionally, VBT has been modified to keep
brightness controls functional on the adapter boards that use LVDS for
the job.
The modifications done to the VBT are:
- Remove the LVDS port entry.
- Move the DP-3 (which is the 2nd DP on the dock) entry to the first
position on the list.
- Set the DP-3 as internally connected.
This has been reported to work with the following panels:
- LP125WF2-SPB4 (1920*1080, 12.5")
- LQ125T1JW02 (2560*1440, 12.5")
- LQ133M1JW21 (1920*1080, 13.3")
- LTN133HL10-201 (1920*1080, 13.3")
- B133HAN04.6 (1920*1080, 13.3")
- B133QAN02.0 (2560*1600, 13.3")
Other eDP panels not on this list should work as well.
Change-Id: I0355d39a61956792e69bccd5274cfc2749d72bf0
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Signed-off-by: Alexei Sorokin <sor.alexei@meowr.ru>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/28950
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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This is the de facto method and should be enforced to keep things
consistent.
Change-Id: I7eee77f7fd49bc38e27cb0e6be0a4a6555098cc7
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80422
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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The name LEDLOGO comes from schematics. It's the red indicator, embedded
in the dot of the 'i' of the ThinkPad logo on laptop's lid.
In vendor firmware, this led starts fading in-and-out, or, in other
words, pulsing, when laptop is put to S3. It helps to determine whether
the laptop is in S3 just by taking a look at the logo.
As of now, coreboot doesn't do anything with this particular indicator,
it's always in enabled (on) state, which is not very convenient.
This patch fixes it.
Tested on T440p.
Change-Id: I85fb69c8c1bed8635a1b31e9b8385c7036bb46dd
Signed-off-by: Evgeny Zinoviev <me@ch1p.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80437
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The .inc suffix is confusing to various tools as it's not specific to
Makefiles. This means that editors don't recognize the files, and don't
open them with highlighting and any other specific editor functionality.
This issue is also seen in the release notes generation script where
Makefiles get renamed before running cloc.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I4790adb41cb62c8c8dd44261a2926dfb6350955a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80111
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
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Since all devicetrees from lenovo/x230 are using the reference names for
PCI devices now, remove the equivalent comments documenting their
function.
Change-Id: Ia06f976ef1439377ff22149044feaa3463d2aeb8
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79964
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
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Since all devicetrees from lenovo/t430 are using the reference names for
PCI devices now, remove the equivalent comments documenting their
function.
Change-Id: I84f432e89c41a02115715f7f1b56123dd0d81171
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79942
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
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Since all devicetrees from lenovo/t530 are using the reference names for
PCI devices now, remove the equivalent comments documenting their
function.
Change-Id: I5ba08843506bc22136aea42ac37936a4f5cad5ce
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79938
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
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Change-Id: I38ef315dbdadb140e8e7163e755a078bc906e1b5
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79963
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
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Change-Id: Ib94dd2778cf89ae8b97b43031d729c728f59a29e
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79941
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
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Change-Id: Ied9f37355432d58f83cb8453111a261c4eddc14a
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79937
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
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Since all devicetrees from lenovo/x220 are using the reference names for
PCI devices now, remove the equivalent comments documenting their
function.
Change-Id: Ic8bff0516811371e1fbb72765c8d03812a689701
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79940
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
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Change-Id: Ife8f3bc8b7fd14bb9a0e8dd4bc3d33b44c8f794f
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79939
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
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Since all devicetrees from lenovo/t520 are using the reference names for
PCI devices now, remove the equivalent comments documenting their
function.
Change-Id: I307dbf7a7d6fc9086e868d8315ba7a66b94a24e7
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79966
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
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Change-Id: I18ce899516fd38b21ded1e3144aa22e705c534b8
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79965
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Use same indent levels for switch/case in order to comply with the
linter.
Change-Id: I602cf024ec84b15b783d36014c725826f9d6595e
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79418
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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With commit adaeb1102186 (nb/intel/sandybridge: Clean up post Haswell SPD mapping API migration), raminit_native.h now only includes 4
other headers and offers no original content. Based on the idea that
all source files should include what they use directly, drop it in
favor of sandybridge.h (which it already includes anyway) and types.h
(replacing stdint.h because it also uses boolean constructs).
Board appears to not use anything sb/intel/bd82x6x/pch.h provides.
And the board still builds after dropping it.
Change-Id: I1b201fe4dd29bac5feb08f372d1e36353eac161d
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78783
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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- Disable unconnected PCH PCIe ports 1 + 3.
- Add smbios_slot_desc to WLAN PCIe port
- Add comment for PCIe port 7 that might have a
XHCI controller connected (some variants only).
Test: Lenovo X220 still boots and all devices are still working
fine. The WLAN slot is shown in dmidecode -t 9.
Change-Id: I3fdfbb7ad30e2ff8a289d9055eaef0557475fdff
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78291
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Boards without HAVE_SPD_IN_CBFS: Move SPD mapping into devicetree.
Boards with HAVE_SPD_IN_CBFS: Convert to Haswell-style SPD mapping.
Change-Id: Id6ac0a36b2fc0b9686f6e875dd020ae8dba72a72
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76967
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
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There is no enumerate_buses() today and also no trace of it in our
repository. Also, in current terms, mainboard_enable() is called
as the very first thing in our enumeration so the comment seems
misleading.
Change-Id: Iae620f83c8166c1cfc8b9fb9ef4a7025987bf1be
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79003
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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Just as in commit 38569d061099: ("mb/lenovo/{x230, x230s}: Disable
SuperSpeed capabilities for WWAN USB")
Although on ThinkPads with Panther Point PCH the usb port inside wwan
socket is usually wired to XHCI, it has actually no SuperSpeed lines,
so maybe it is okay to disable SuperSpeed capabilities, and wire them
to EHCI #2 by making use of XUSB2PRM and USB3PRM.
Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Change-Id: I61e61283a821686558f7f3fdfac7073bb3557e93
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78680
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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For Sandy Bridge boards with MRC raminit support, migrate as much
MRC settings to devicetree as possible, to stop mainboard code from
needlessly overwriting entire PEI data structure, so they will not
interfere with upcoming transition to one standard Haswell way of
providing SPD info to northbridge.
Some exceptions allowed are described below and in code comments.
SPD-related items are kept out of devicetree for now. They will be
migrated (with a different representation) with the Haswell SPD
transition.
google/{butterfly,link,parrot,stout} have max DDR3 frequency set in
pei_data to 1600 (2*800), but in devicetree to 666. The reason for the
difference seems to be problems with native raminit code. These are
converted into ternaries tied to CONFIG_USE_NATIVE_RAMINIT, with an
added "fix me" tag. asus/p8x7x-series also needs the same treatment,
based on testing various memory on p8z77-m hardware.
TEST=Builds on all affected boards. asus/p8z77-m still works with multiple RAM modules tested.
Change-Id: Ie349a8f400eecca3cdbc196ea0790aebe0549e39
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76962
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
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Selects should be done in the Kconfig file instead of Kconfig.name and
not mixed over both files.
Change-Id: I6b71c7c5c9e32e21c757c0ed0e9c6bd9d58a4f75
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78131
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I9b1e3ad668c332bebdaf48a2e95f1f9e2131d598
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77765
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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To help identify the licenses of the various files contained in the
coreboot source, we've added SPDX headers to the top of all of the
.c and .h files. This extends that practice to Makefiles.
Any file in the coreboot project without a specific license is bound
to the license of the overall coreboot project, GPL Version 2.
This patch adds the GPL V2 license identifier to the top of all
makefiles in the mainboard directory that don't already have an SPDX
license line at the top.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ic451e68b1ad9ccdf34484dd98bd7fca7e177ef22
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68982
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
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Select INTEL_GMA_HAVE_VBT so VBT files are added by default. This board
has two specific VBT files that are hard-coded in the Makefile. Hence
set an empty INTEL_GMA_VBT_FILE string.
Change-Id: I0508c8016da06b401d6fbefd6e5cec1af018a5c8
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75380
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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There is only a single place where we need the LVDS EDID string. Let's
call gm45_get_lvds_edid_str() right there. This simplifies the API and
helps to follow the execution flow.
The function is moved to avoid a forward declaration.
Change-Id: I86f3a88e6b661bcf60319edbe301e70304924727
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75378
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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The PCI resource should only be probed as part of the device
.init process. We can simply do that first and know that we
can use the global `gtt_res` from then on.
This simplifies the signature of gm45_get_lvds_edid_str(), and
makes changes to the API user (lenovo/x200) necessary.
Change-Id: I6c96f715abfa56dcb1cd89fde0fbaef3f1cb63ae
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75376
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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Its EDID string is "LTN121AT07L02". The vendor sets BLC_PWM_CTL to
0x31313131.
This frequency seems working well on the x200 with this panel, which
is said to be LED.
Change-Id: I8b0ec04c6f6fcb6d4027a5114698db87d7718191
Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74182
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Ioapic information in the devicetree was only used to set up mptables
but this generic driver was removed (ca5a793 drivers/generic/ioapic:
Drop poor implementation).
This removes the unused remainders from mainboard devicetrees.
Remove ioapic setup from sconfig.
Change-Id: Ib3fef0bf923ab3f02f3aeed2e55cf662a3dc3a1b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71789
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
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mainboard_vbt_filename() used to assume that it is called after a call
to get_blc_pwm_freq_value() with a valid parameter, but currently it
is the first call of get_blc_pwm_freq_value(NULL), and will return 0,
so "data_led.vbt" is always returned, regardless of the actual type of
the panel.
Combined with the previous commit, in this commit
mainboard_vbt_filename() will explicitly read EDID string via
gm45_get_lvds_edid_str() and use this string to call
get_blc_pwm_freq_value().
Resolves: https://ticket.coreboot.org/issues/475
Tested on my x200s with LTD121EQ3B (LED), and x200 with LTD121EWVB
(CCFL).
Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Change-Id: I2e080b29321b6989d1f26b6c67876b3d703042f4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74181
Reviewed-by: Swift Geek (Sebastian Grzywna) <swiftgeek@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
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This to fix following error using Clang-16.0.0:
/cb-build/coreboot-toolchain.0/clang/LENOVO_W500/mainboard/lenovo/t400/static.c:135:22: error: implicit truncation from 'int' to a one-bit wide bit-field changes value from 1 to -1 [-Werror,-Wsingle-bit-bitfield-constant-conversion]
.backlight_enable = 0x01,
^~~~
/cb-build/coreboot-toolchain.0/clang/LENOVO_W500/mainboard/lenovo/t400/static.c:136:23: error: implicit truncation from 'int' to a one-bit wide bit-field changes value from 1 to -1 [-Werror,-Wsingle-bit-bitfield-constant-conversion]
.dock_event_enable = 0x01,
^~~~
Change-Id: Icd35224877fee355e1bbb8a8e838cb047604babb
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73810
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
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This to fix following error using Clang-16.0.0:
/cb-build/coreboot-toolchain.0/clang/APPLE_IMAC52/mainboard/apple/macbook21/static.c:66:19: error: implicit truncation from 'int' to a one-bit wide bit-field changes value from 1 to -1 [-Werror,-Wsingle-bit-bitfield-constant-conversion]
.c4onc3_enable = 1,
^
/cb-build/coreboot-toolchain.0/clang/APPLE_IMAC52/mainboard/apple/macbook21/static.c:75:32: error: implicit truncation from 'int' to a one-bit wide bit-field changes value from 1 to -1 [-Werror,-Wsingle-bit-bitfield-constant-conversion]
.p_cnt_throttling_supported = 1,
^
Change-Id: I691b51a97b359655c406bff28ee6562636d11015
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73796
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
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Of the 13 mainboards that implement mainboard_should_reset_usb() hook,
all but one do the same: Stop MRC from resetting USB when resuming
from S3 suspend.
This hook turns out is only here to facilitate a USB reset workaround
on samsung/stumpy for an old ChromeOS kernel which is no longer needed.
Drop the workaround, the hook, and headers no longer used.
roda/rv11/early_init.c is left with no useful code after this patch,
so drop it entirely from both bootblock and romstage.
Change-Id: Ib3a5a00c0a6b1528e39435784919223d16b3914e
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72496
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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To deprecate VBOOT_VBNV_CMOS [1], replace VBOOT_VBNV_CMOS with
VBOOT_VBNV_FLASH for lenovo boards: t400, t410, t420, t420s, t430,
t430s, t520, t530, x131e, x1_carbon_gen1, x60, x200, x201, x220, x230. A
0x2000 RW_NVRAM region is allocated for them, with the COREBOOT size
reduced by 0x2000.
Also remove the VBOOT_VBNV_OFFSET config, since it's only used for
VBOOT_VBNV_CMOS.
[1] https://web.archive.org/web/20230115020833/https://issuetracker.google.com/issues/235293589?pli=1
BUG=b:235293589
TEST=./util/abuild/abuild -t LENOVO_T430S -a # with VBOOT enabled
Change-Id: I7e29db7eeceec499fbbcf902a26bfe9a2076de40
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72809
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Found-by: linter
Change-Id: I7c6d0887a45fdb4b6de294770a7fdd5545a9479b
Signed-off-by: Alexander Goncharov <chat@joursoir.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72795
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Removing default on/off from mainboard devicetrees is left as a follow-up.
Change-Id: I74c34a97ea4340fb11a0db422a48e1418221627e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69502
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
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If a discoverable device (e.g. a PCI device) does not appear in the
devicetree (typically because it is removable), coreboot enables it
by default. Disable the SATA2 (device for SATA ports 4 and 5, which
is not used in AHCI mode) and Thermal devices on W520 as well. Both
devices were only disabled on the T520.
Tested, this change fixes a long boot time when using MrChromebox's
edk2 payload on the W520, likely related to the following errors:
AHCI: Error interrupt reported PxIS: 40000001
Non data transfer failed at retry 0
AHCI: Error interrupt reported PxIS: 40000001
Non data transfer failed at retry 1
AHCI: Error interrupt reported PxIS: 40000001
Non data transfer failed at retry 2
AHCI: Error interrupt reported PxIS: 40000001
Non data transfer failed at retry 3
AHCI: Error interrupt reported PxIS: 40000001
Non data transfer failed at retry 4
Change-Id: I0b0483aae05fa84d97987a93db634b740f830e18
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71857
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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As per Kendo3-WS schematics, the conventional PCI bridge is not used.
Change-Id: Ic3aa11cc3a3028c31b06ad8f74875db8c5626a89
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71856
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I4f2f02623b060ef0ebefc5aceb713c77a8b1e9a6
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71523
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Change-Id: Id1078b14a805eea53d2a7c5a8183a5413f26e115
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71521
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Replace `Not (a, b)` with `b = ~a`.
Change-Id: I0f18119c8e91222e59a56b8509f12c6ece6d04ce
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71514
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Replace `And (a, b)` with `a & b`.
Change-Id: Id8bbd1a477e6286bbcb5fa31afd1c7a860b1c7dc
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70851
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Replace `And (a, b, c)` with `c = a & b`, respectively `c &= b` where
possible.
Change-Id: Ie558f9d0b597c56ca3b31498edb68de8877d3a2f
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70850
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Replace `Or (a, b, c)` with `c = a | b`, respectively `c |= b` where
possible.
Change-Id: Icf194b248075f290de90fb4bc4e9a0cd9d76ec61
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70846
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Replace `ShiftLeft (a, b)` with `a << b`.
Change-Id: I812b1ed9dcf3a5749b39a9beb9f870258ad6a0de
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70842
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Replace `ShiftLeft (a, b, c)` with `c = a << b`.
Change-Id: Ibd25a05f49f79e80592482a1b0532334f727af58
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70841
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Only IO trap #3 for lenovo/x60,t60 and getac/p470 have implemented
the IO trap handler.
Change-Id: Ibadce174f673e88380f4b6745fd9ed8b73177a13
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70367
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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