| Commit message (Collapse) | Author | Age | Files | Lines |
|
|
|
|
|
|
|
|
|
|
| |
Atlas uses IoT FSP.
Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: I4c20600e0b62367e6e58908cf9cf916f309e6362
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66368
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
|
|
|
|
|
|
|
|
|
|
|
|
| |
Set the default value for MAX_CPUS in the SoC config and drop it from
the mainboards where it is set to those values.
Change-Id: Ib56fdcfe770ef736a2c5e183481d9f9966570e6d
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52607
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
|
|
|
|
|
|
|
|
| |
Switch x86 uart output from EC to LPSS.
Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: I2756d139a72185ba6a5c6d1079d770ce33afdf71
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65985
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Introduce a new field in the board settings EEPROM region to control
whether BIOS menu is to be enabled. This field will be used in EDK2
payload.
Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: I0af81c9e70a0088caea6bc7e2b81eab9a123c0f7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65128
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
|
|
|
|
|
|
|
|
| |
Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: I7c50f770c3a7ab261d6ea41f945e2239ba53fd09
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64944
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
|
|
|
|
|
|
| |
Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: Ia5b6c5c72a1eafe1118e92e4579decb4f4abc9e5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64943
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
|
|
|
|
|
|
|
|
| |
Enable clk 1, LTR & AER for PCIe-to-i225 bridge.
Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: I9593f5d0b70f3d231fd1a8f4758b924645392d63
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64902
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
When device tcss_xhci is disabled, boot hang occurs at FSP-S
TcssInit(): "IomReadyCheck Failed!"
Enabling this device fixes the issue.
Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: Ie001bd56b403d511c397737fbc214ed64956910d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64901
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
|
|
|
|
|
|
| |
Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: Iea5312055305bc3354755607a7bfafa7980c6d21
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64900
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@tutanota.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
commit c6b041a12e refactor the TPM Kconfig. MAINBOARD_HAS_LPC_TPM
has changed to MEMORY_MAPPED_TPM.
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: Iff7e20ac271eb5b2afc9061819e2cc0cf2264cbf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63773
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Break TPM related Kconfig into the following dimensions:
TPM transport support:
config CRB_TPM
config I2C_TPM
config SPI_TPM
config MEMORY_MAPPED_TPM (new)
TPM brand, not defining any of these is valid, and result in "generic" support:
config TPM_ATMEL (new)
config TPM_GOOGLE (new)
config TPM_GOOGLE_CR50 (new, implies TPM_GOOGLE)
config TPM_GOOGLE_TI50 (new to be used later, implies TPM_GOOGLE)
What protocol the TPM chip supports:
config MAINBOARD_HAS_TPM1
config MAINBOARD_HAS_TPM2
What the user chooses to compile (restricted by the above):
config NO_TPM
config TPM1
config TPM2
The following Kconfigs will be replaced as indicated:
config TPM_CR50 -> TPM_GOOGLE
config MAINBOARD_HAS_CRB_TPM -> CRB_TPM
config MAINBOARD_HAS_I2C_TPM_ATMEL -> I2C_TPM && TPM_ATMEL
config MAINBOARD_HAS_I2C_TPM_CR50 -> I2C_TPM && TPM_GOOGLE
config MAINBOARD_HAS_I2C_TPM_GENERIC -> I2C_TPM && !TPM_GOOGLE && !TPM_ATMEL
config MAINBOARD_HAS_LPC_TPM -> MEMORY_MAPPED_TPM
config MAINBOARD_HAS_SPI_TPM -> SPI_TPM && !TPM_GOOGLE && !TPM_ATMEL
config MAINBOARD_HAS_SPI_TPM_CR50 -> SPI_TPM && TPM_GOOGLE
Signed-off-by: Jes B. Klinke <jbk@chromium.org>
Change-Id: I4656b2b90363b8dfd008dc281ad591862fe2cc9e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63424
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
|
|
|
|
|
|
|
|
|
|
| |
Enable SPI dTPM using eSPI bus.
Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: I18ca41c143ade024ee2840b619ba777b22a2a86a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63720
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
The PCI Local Bus Specification Revision 3.0 requires that
multi-function devices always implement function 0. Because of
this, enabling UFS (PCI device 12.7) requires ISH (PCI device 12.0)
to be enabled as well.
Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: Ia8b9561973640edc5f7d0f579dd640e805c0af17
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63719
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
|
|
|
|
|
|
| |
Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: I3f438a7b1dff1a44a81edc8adc983d08708fdd57
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63718
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Update Kconfig per Atlas usages:
1. Set EC I/O mapped UART as default UART output
2. Add EC IFD region & ACPI support
Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: I970de724237bcb08899aed7a4b87a23c5cdb0b48
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63464
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
|
|
|
|
|
|
|
|
|
|
|
|
| |
This implementation adds eSPI IO decode range for EC.
1. 0x800-0x8FF / 0x200-020F: EC host command range.
2. 0x900-0x9ff: EC memory map range.
Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: I787561287025e33a8622eb9b3565fa14d0416c46
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63465
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
|
|
|
|
|
|
|
|
| |
I225 doesn’t support ASPM, so disable it at the root port.
Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: I61fe3760c1cde60795c9b52c703e521ba4df504a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63466
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
|
|
|
|
|
|
|
|
| |
Update Atlas GPIOs for GPD11 & E7.
Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: I92a0d0797206cdba96d7c6efe264b0356b5157ea
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63411
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
| |
Update the SPD address as Atlas is using DIMM 0 & 1 in memory
controller 1 channel 1.
Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: Icefcd23b57a7f97e1ee25fed20b35d0e2cb51145
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63410
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
coreboot chip.h files mainly contains variable which allows board to
fill platform configuration through devicetree.
Since many of this configuration involves FSP UPDs, variable names were
in camel case which aligned with UPD naming convention.
By default coreboot follow snake case variable naming, so cleaning up
file to align all variable names as per coreboot convention.
During renaming process, this patch also removes unused variables
listed below:
-> SataEnable // Checked in SoC code based on PCI dev enabled status
-> ITbtConnectTopologyTimeoutInMs // SoC always passes 0, so not used
Note: Since separating out changes into smaller CL might break the
compilation for the patch set, this is being pushed as a single big CL.
BUG=None
BRANCH=firmware-brya-14505.B
TEST=All boards using ADL SoC compiles with the CL.
Change-Id: Ieda567a89ec9287e3d988d489f3b3769dffcf9e0
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62645
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Commit hash b8b40964 ( mb, soc: Add the SPD_CACHE_ENABLE) introduced
per mainboard logic to invalidate the mrc_cache.
This patch moves mrc_cache invalidating logic into IA common code and
cleans up the code to remove unused argument `dimms_changed` from SoC
and mainboard directory.
BUG=b:200243989
BRANCH=firmware-brya-14505.B
TEST=Able to build and boot redrix without any visible failure/errors.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I6f18e18adc6572571871dd6da1698186e4e3d671
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62738
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
This patch modifies `memcfg_init` and `variant_memory_init`functions
argument from FSP_M_CONFIG to FSPM_UPD.
This change in `memcfg_init()` argument will help to update the
architectural FSP-M UPDs from common code blocks rather than going
into SoC and/or mainboard implementation.
BUG=b:200243989
BRANCH=firmware-brya-14505.B
TEST=Able to build and boot redrix without any visible failure/errors.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I3002dd5c2f3703de41f38512976296f63e54d0c5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62736
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Shorten define names containing PCI_{DEVICE,VENDOR}_ID_ with
PCI_{DID,VID}_ using the commands below, which also take care of some
spacing issues. An additional clean up of pci_ids.h is done in
CB:61531.
Used commands:
* find -type f -exec sed -i 's/PCI_\([DV]\)\(EVICE\|ENDOR\)_ID_\([_0-9A-Za-z]\{2\}\([_0-9A-Za-z]\{8\}\)*[_0-9A-Za-z]\{0,5\}\)\t/PCI_\1ID_\3\t\t/g'
* find -type f -exec sed -i 's/PCI_\([DV]\)\(EVICE\|ENDOR\)_ID_\([_0-9A-Za-z]*\)/PCI_\1ID_\3/g'
Change-Id: If9027700f53b6d0d3964c26a41a1f9b8f62be178
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39331
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
In order to cache the spd data which reads from the memory module, we
add SPD_CACHE_ENABLE option to enable the cache for the spd data. If
this option is enabled, the RW_SPD_CACHE region needs to be added to
the flash layout for caching the data.
Since the user may remove the memory module after the bios caching the
data, we need to add the invalidate flag to invalidate the mrc cache.
Otherwise, the bios will use the mrc cache and can make the device
malfunction.
BUG=b:200243989
BRANCH=firmware-brya-14505.B
TEST=build pass and enable this feature to the brask
the device could speed up around 150ms with this feature.
Change-Id: If7625a00c865dc268e2a22efd71b34b40c40877b
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62294
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
The mainboard_memory_init_params takes the struct FSP_M_CONFIG as the
input which make the board has no chance to modify data in the
FSPM_UPD, for example, set FspmArchUpd.NvsBufferPtr = 0. After changing
the FSP_M_CONFIG to FSPM_UPD, the board can modify the value based on
its requirement.
BUG=b:200243989
BRANCH=firmware-brya-14505.B
TEST=build pass
Change-Id: Id552b1f4662f5300f19a3fa2c1f43084ba846706
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62293
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
| |
Add CPU & PCH PCIe configs and remove the unused devices.
Configures per Atlas schematics v6.
Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: Id3145156c4ab3ec1c2d3eb6c433108a1b1cab9e8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61296
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
|
|
|
|
|
|
|
|
|
|
| |
Configure SATA, USB & HSIO settings per Atlas schematics v6.
Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: I88c898d4b0c3bfeefbca71e13dad55e2c5fc846f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61277
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
| |
Introduce a new field in the board settings EEPROM region to control
whether VT-x is to be enabled.
Change-Id: If65c58dd6e5069dba1675ad875c7ac89e704350e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61507
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Marvin Drees <marvin.drees@9elements.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Since Tiger Lake platform, the HECI1 device can be disabled on
Alder Lake platform using two different mechanism:
A. Using PMC IPC command 0xA9.
B. Sending SBI message under SMM.
In current scope of Alder Lake the default implementation is using
(B) sending sbi message under SMM. A follow up patch to add the
possible options and let platform to choose the applicable one.
List of changes:
1. Drop `HeciEnabled` from dt and dt chip configuration.
2. Replace all logic that disables HECI1 based on the `HeciEnabled`
chip config with `DISABLE_HECI1_AT_PRE_BOOT` config.
3. Default enable HECI1 device in `chipset.cb` to ensure the HECI1
device can undergo the PCI enumeration and later based on the
mainboard policy the HECI1 device can be disabled.
Mainboards that choose to make HECI1 enable during boot don't override
`DISABLE_HECI1_AT_PRE_BOOT` config.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ie673e634fbc0bdece419c379d417b08dfb4819e2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60731
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
|
|
|
|
|
|
|
|
| |
Update GPIO settings as per schematics v3.
Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: I685d0b7274e3a6e707fec37d051f4818860169ed
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61116
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
This is a initial mainboard code cloned from adlrvp aimed to serve as
base for further mainboard check-ins. This commit copies the mainboard
directory and adjusts the naming to match the new board's name.
Besides, This commit also trims down major parts of adlrvp code except
some of ADL-P DDR5 RVP as Atlas is using it as main reference.
Follow-up commits will introduce the needed changes for the new
mainboard.
Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: Ia3129f68c73969604edcd290c3e50ad219cf88d9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60899
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
|
|
|
|
|
|
|
|
|
|
| |
Run the command below to fix all occurrences.
$ git grep -l 'configuration in bootblock\. \*/' | xargs sed -i 's,configuration in bootblock\. \*/,configuration in bootblock */,'
Change-Id: I84669341e2c8976953284dbaf113da3397857de3
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60248
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
| |
All Coffee Lake mainboards use the default value for the setting
`SataMode`. Thus, drop it from their devicetree.
Change-Id: Ibb329eb8b752c2220bb25f14fb6ae92dd8a308d6
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59889
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
The Hermes mainboard is used in different system configurations. The
current VBT for Poseidon systems is unsuitable for Avalanche systems
because display ports are connected differently.
Add a new field in the BMC config EEPROM layout and use it to choose
the correct VBT for every system configuration.
Change-Id: I2647f2ae3f496b9ad75980ba86beb7800fdb0668
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59838
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
The original RCOMP resistor and target values only apply to ULT CPUs and
do not make sense for the CFL-S CPUs Hermes uses. Fix the RCOMP settings
and the associated comments.
Tested, still boots.
Change-Id: I015797c58c914c6581d472e6d70d2dd7bad2b14f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58364
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Define a new field in the board config EEPROM layout for port B Vref.
Write port B Vref settings to unused non-volatile NID 0x12 instead of
NID 0x18, the actual port B NID. Because per-port Vref settings don't
persist after codec resets, a custom Realtek driver (ab)uses NID 0x12
to restore port B Vref after resetting the codec.
Change-Id: Iaa11ba9c74f643e94046d4983fbce65dbedd1025
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58879
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
|
|
|
|
|
|
|
|
| |
Update the pin configs for the front panel jacks.
Change-Id: I3760f0a25e964cf0eba99d180fd6f3e8488af868
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59545
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Use lowercase for hex numbers, sort includes alphabetically and avoid
relying on indirect inclusion. Include `<intelblocks/gpio.h>` instead
of `<intelblocks/gpio_defs.h>`, as the latter implcitly relies on one
definition from `<soc/gpio.h>`. Also drop useless dsdt.asl and fix up
the indentation of some includes.
Tested with BUILD_TIMELESS=1, Prodrive Hermes remains identical.
Change-Id: I3aeb9a644cf33cb4b1987174f40ef0fc7daccfa9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59672
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
There's no need to use a variant structure here. Only one variant is
used, and revision-specific differences are handled at run-time, and
it's unlikely that another variant will ever exist.
Reorganize the mainboard code to get rid of the variant structure.
Change-Id: I1543f5b76975b0e7183fbb759e9bae5c34151d06
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59671
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
|
|
|
|
|
|
|
| |
Change-Id: I943d0e2a91778df306f323e2b889cd4e928e0c2b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59837
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
The Prodrive Hermes mainboard has four i211 Ethernet NICs and an i210
Ethernet NIC, but their numbering isn't consistent with the PCIe root
port function numbers. With only a M.2 SSD plugged in, Linux uses the
following names:
PHY 0 ---> enp6s0
PHY 1 ---> enp4s0
PHY 2 ---> enp3s0
PHY 3 ---> enp1s0
PHY 4 ---> enp2s0
These names change after adding or removing PCIe devices in slots
connected to root ports that get enumerated before the NICs' root
ports, because the assignment of secondary bus numbers depends on
the enumeration order. Because of this, the "predictable" network
interface names are not at all predictable, which is awful.
To avoid this, describe the NICs using SMBIOS Type41 entries with the
correct instance numbers. With this patch, Linux uses these names:
PHY 0 ---> eno0
PHY 1 ---> eno1
PHY 2 ---> eno2
PHY 3 ---> eno3
PHY 4 ---> eno4
No matter what PCIe devices are present, these names don't change.
Change-Id: I7a527298f84172f9135006083ad7e748dcc27911
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58628
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
|
|
|
|
|
|
|
|
|
|
| |
The "internal audio connection" setting is actually about the front
panel audio. Rename functions and variables to reflect this.
Change-Id: I1be8f68ac3e8b91bc4983dc06daa37afb7bdf926
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58904
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin van Son <justin.van.son@prodrive-technologies.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Set the `PcieRpLtrEnable` option to enable the LTR capability on all PCH
PCIe root ports.
TEST=Verify LTR capability enabled in `DevCap2` using `lspci -vv`
Change-Id: I07ea37d178ea61d904c4f131fdea31479e899ef3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58326
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Map each PCIe clock source to the corresponding root port. Also, correct
the CLKREQ# mapping for clock sources not associated to any CLKREQ# pin.
The default `PcieClkSrcClkReq` value of 0 corresponds to CLKREQ# 0.
TEST=Check that Linux sees the same PCIe devices with this commit:
- All 5 onboard Ethernet NICs
- BMC
- Two random graphics cards in PEG0 and PEG1 slots
- M.2 M NVMe SSD
Change-Id: I0515877a36d42fb8858a0f0b3c0af1199a18d9af
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58368
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Correct the PCIe clock source configuration as per the schematics.
Apparently, FSP does not turn off unused PCIe clock sources when using
SPS (Server Platform Services) firmware, but it does when using CSME
firmware.
TEST=BMC and Ethernet NICs get detected when using CSME firmware.
Change-Id: Id25a34816f512510640db95251a7a792c1eebe62
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58065
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
|
|
|
|
|
|
|
|
|
|
| |
There's no need to have an overridetree with a single board variant.
TEST=Compare static.c and observe only device order has changed.
Change-Id: I2097e247c27d5d0c5479cb533b477cd490a4c827
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58367
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Move per-port PCIe settings inside the corresponding PCIe root port
device. Also, remove several unnecessary and/or redundant comments.
Tested with BUILD_TIMELESS=1, Prodrive Hermes remains identical.
Change-Id: I3f64d56b3b2c592194b18ae7b7c63ef41a1e060f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58325
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
|
|
|
|
|
|
|
|
|
| |
Enable SATA power optimizer as recommended by Intel. Tested, a SATA SSD
is still detected correctly by SeaBIOS (version 1.14.1).
Change-Id: Ia6d29de08583dfc0c2d38e8395adcaa2c540ec7b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57834
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Fixes commit bd5b4aa683a634a73a6a63d1f197e2bb74b6a80e
"soc/intel/cannonlake: Switch PMC to use device callbacks" as it
requires the PCI device 1f.2 to be present in the devicetree.
It was missing for this mainboard and caused a boot failure.
Change-Id: Iaf508b2d955578efa2a266af50c568f5c0a47aaf
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57574
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
|
|
|
|
|
|
|
|
|
| |
SoC code already sets this UPD to `CONFIG_IED_REGION_SIZE`, which
defaults to 0x400000 for soc/intel/cannonlake.
Change-Id: I6587e17a4a3425c561cffe6e3df0d932a2458168
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57260
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
|