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path: root/src/mainboard/siemens/mc_apl1
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* mb/siemens/mc_apl3: Enable LPSS UART 1Mario Scheithauer2019-07-121-2/+3
* mb/siemens/{baseboard,mc_apl3,mc_apl4,mc_apl5}: Fix GPIO_168Mario Scheithauer2019-07-114-4/+4
* mb/siemens/{mc_apl1,...,mc_apl5}: Reduce eMMC bus speed modeMario Scheithauer2019-07-115-5/+5
* siemens/mc_apl5: Change PTN interface settingsMario Scheithauer2019-06-211-1/+2
* siemens/mc_apl5: Enable TPM supportMario Scheithauer2019-06-213-2/+9
* siemens/mc_apl5: Add own GPIO tableMario Scheithauer2019-06-062-0/+420
* src/mainboard: Add missing 'include <types.h>'Elyes HAOUAS2019-05-298-0/+8
* mb/siemens/mc_apl2: Limit SD-Card speed to DDR50Werner Zeh2019-05-061-0/+20
* mb/siemens/mc_apl4: Remove usage of external RTCWerner Zeh2019-04-152-16/+1
* mb/siemens/mc_apl1: Enable HDA in devicetree for all mainboard variantsWerner Zeh2019-04-155-5/+5
* siemens/mc_apl5: Remove reduced clock rate for I2C0Mario Scheithauer2019-04-081-12/+0
* siemens/mc_apl4: Provide CLK on APL Pin PMU_SUSCLKUwe Poeche2019-04-041-1/+2
* mb/siemens/mc_apl1: use comment in Kconfig.nameThomas Heijligen2019-03-211-0/+2
* mb/mc_apl1/variants/mc_apl5: Drop unused '#include <lib.h>'Elyes HAOUAS2019-03-151-1/+0
* mb/siemens/{mc_apl1,mc_tcu3}: Fix typo on "Display"Elyes HAOUAS2019-03-063-3/+3
* device/mmio.h: Add include file for MMIO opsKyösti Mälkki2019-03-041-0/+1
* arch/io.h: Add missing includesKyösti Mälkki2019-03-041-0/+1
* device/pci: Fix PCI accessor headersKyösti Mälkki2019-03-011-0/+1
* siemens/mc_apl4: Enable HW SPI TPM on mainboard mc_apl4Uwe Poeche2019-02-132-1/+8
* siemens/mc_apl2: Remove double entry from devicetreeMario Scheithauer2019-02-131-1/+0
* mb/siemens/mc_apl1: Enable VTD for mc_apl2 and mc_apl5Werner Zeh2019-02-052-0/+6
* siemens/mc_apl2: Change SERIRQ modeMario Scheithauer2019-01-301-1/+0
* siemens/mc_apl2: Correct whitespace of devicetreeMario Scheithauer2019-01-301-10/+10
* siemens/mc_apl2: Activate TPM supportMario Scheithauer2019-01-303-2/+10
* siemens/mc_apl4: Change UART_FOR_CONSOLE indexMario Scheithauer2019-01-161-0/+3
* siemens/mc_apl1: Use INTEL_LPSS_UART_FOR_CONSOLEMario Scheithauer2019-01-111-0/+4
* siemens/mc_apl4: Enable RTC RX6110SA on this mainboardUwe Poeche2018-12-172-1/+16
* siemens/mc_apl4: Enable LVDS Display on mc_apl4Uwe Poeche2018-12-174-0/+299
* siemens/mc_apl4: Add GPIO configurationUwe Poeche2018-12-172-0/+392
* cpu/intel/common: Use a common acpi/cpu.asl fileArthur Heymans2018-11-301-1/+1
* siemens/mc_apl5: Disable PCI clock outputs on XIO bridgesMario Scheithauer2018-11-291-5/+16
* siemens/mc_apl5: Set bus master bit for on-board PCI deviceMario Scheithauer2018-11-291-0/+10
* siemens/mc_apl5: Enable SDCARDMario Scheithauer2018-11-291-1/+1
* siemens/mc_apl5: Adjust the settings for the PCIe root portsMario Scheithauer2018-11-271-12/+12
* siemens/mc_apl1/variants/mc_apl*: Remove unneeded PTN readMario Scheithauer2018-11-262-12/+0
* siemens/mc_apl4: Set CPU clock to minimum ratioWerner Zeh2018-11-231-0/+1
* mb: Set coreboot as DSDT's manufacturer model IDElyes HAOUAS2018-11-231-2/+3
* ACPI: Fix DSDT's revision fieldElyes HAOUAS2018-11-211-1/+1
* siemens/mc_apl5: Add new mainboard variant mc_apl5Mario Scheithauer2018-11-188-0/+517
* mb/siemens/mc_apl1/variants/mc_apl*: Remove unused BOARD_SIEMENS_MC_APL*_VARElyes HAOUAS2018-11-164-4/+4
* src: Remove unneeded include <lib.h>Elyes HAOUAS2018-11-162-2/+0
* mb/*/*/Kconfig: Use CONFIG_VARIANT_DIR for devicetreePeter Lemenkov2018-11-165-16/+4
* siemens/mc_apl4: Clean up ramstageMario Scheithauer2018-11-163-104/+0
* siemens/mc_apl4: Overwrite swizzle data for LPDDR4Mario Scheithauer2018-11-162-0/+70
* siemens/mc_apl4: Enable SDCARDMario Scheithauer2018-11-121-1/+1
* siemens/mc_apl4: Remove external RTC from I2C0Mario Scheithauer2018-11-121-21/+7
* siemens/mc_apl4: Enable all PCIe root portsMario Scheithauer2018-11-121-6/+6
* siemens/mc_apl4: Remove reduced clock rate for I2C0Mario Scheithauer2018-11-121-12/+0
* siemens/mc_apl4: Disable CLKREQ of PCIe root portsMario Scheithauer2018-11-121-5/+6
* siemens/mc_apl3: Disable PCI clock outputs on XIO bridgesMario Scheithauer2018-11-121-5/+17
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