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* mb/google/brya: move the common config to the baseboardZhuohao Lee2021-07-262-9/+2
| | | | | | | | | | | | | | | | | This patch moves the common config to the Kconfig under BOARD_GOOGLE_BASEBOARD_BRYA and removes the redundant config. BUG=b:191472401 BRANCH=None TEST=build pass Change-Id: Ie59299dfaba6bb23758d4a4c22a6dbbb4ba6520e Signed-off-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56387 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/brya: Enable BT offload conditionallySugnan Prabhu S2021-07-263-0/+39
| | | | | | | | | | | | | | | | | Currently, BT offload is disabled/enabled unconditionally based on the devicetree settings. BT offload uses I2S lines and cannot be enabled when a I2S based audio daughter card is active. So we need to enable BT offload only while using soundwire based audio daugther card. BUG=b:175701262 TEST=Verified BT offload on brya with soundwire audio daughter card BT offload enabled Change-Id: I6a9ad463e13e2cfcfc3b7de5a61a25cdef0641f7 Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55180 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/razer/blade_stealth_kbl/Kconfig: Fix up indentationAngel Pons2021-07-251-32/+32
| | | | | | | | | | | | Change-Id: I0ffae7408f11f4f517204a0a670845c11b3601a8 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56549 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/*/chip.h: Correct PSPP Enum ValueMatt Papageorge2021-07-243-3/+3
| | | | | | | | | | | | | | | | | | | | | | | It appears the pspp_policy enum is not the same as the FSP definition currently being used. This means that the incorrect PSPP value setting would get read by FSP. For Zork programs this meant we actually were setting links as DXIO_PSPP_BALANCED instead of DXIO_PSPP_POWERSAVE. This change adds DXIO_PSPP_DISABLED as the first enum value to properly match the FSP definition and adjusts non AMD Customer Reference Boards that reference the enum to still send the same value even though it has now change definitions. If we actually want DXIO_PSPP_POWERSAVE for those boards that can be adjusted in a future change. BUG=b:193495634 TEST=Boot to OS with Majolica and Guybrush and run 10G iperf on wifi with other server on local network. Change-Id: I287b6d3168697793a2ae8d8e68b4ec824f2ca5ef Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56463 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
* mb/google/guybrush: Update GPIOs settingsMartin Roth2021-07-242-19/+32
| | | | | | | | | | | | | | | | | | | - The WWAN card was being disabled later than desired. - The SD card was never being placed into reset on BoardID 1. - Enable Touchscreen power - Enable PCIe_RST1 at the same points as PCIe_RST - Remove Redundant Bootblock settings BUG=b:193036827 TEST=Build & Boot, look at GPIO states through boot process Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I5431da755d98e4ad0b300d01cac562d61db0bc08 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56498 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt Papageorge <matthewpapa07@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* soc/amd/stoneyridge/fch: change sb prefix of sb_clk_output_48Mhz to fchFelix Held2021-07-231-1/+1
| | | | | | | | | | | Stoneyridge has an integrated FCH and no south bridge, so change the sb prefix to fch. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I5154ae1158f864d4a2aca55e6bcce6a742c6afe1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56527 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* herobrine: get boardid from GPIO configurationRavi Kumar Bokka2021-07-232-0/+20
| | | | | | | | | | | | | | Getting boardid information for the different SKU variants BUG=b:182963902, b:193807794 TEST=Validated on qualcomm sc7280 development board Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org> Change-Id: I2b7625f9b98563438d1ac20e6f29411ef1058cf4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55950 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* mb/siemens/mc_ehl1: Add GPIO configurationWerner Zeh2021-07-231-256/+154
| | | | | | | | | | Provide a valid GPIO configuration based on the mainboard wiring. Change-Id: I36f0e8292a405b4bac74fbc5fde62e5e414387e7 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56519 Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/siemens/mc_ehl1: Remove SD-Card card detect GPIO in devicetreeWerner Zeh2021-07-231-3/+0
| | | | | | | | | | | Since there is no SD card interface on this mainboard do not set the card detect GPIO. Change-Id: Ibe6799c5c540538f97d1726ec16e79f3edbb16fd Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56489 Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/siemens/mc_apl{1,2,3,5,6}: Use PCI_ALLOW_BUS_MASTER_ANY_DEVICEWerner Zeh2021-07-235-5/+5
| | | | | | | | | | | | Use the Kconfig switch PCI_ALLOW_BUS_MASTER_ANY_DEVICE instead of PCI_ALLOW_BUS_MASTER to enable PCIe bus master bit as requested in CB:56441 during review. Change-Id: I433dbae0d9b15e41d1d0750298868341ce3d6b46 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56502 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
* mainboard/up/squared: Add one more DRAM configurationFlorian Laufenböck2021-07-231-1/+13
| | | | | | | | | | | | Add a new configuration option with more density for 8GB variants of the up squared board. Settings are taken from slimbootloader. Signed-off-by: Florian Laufenböck <florian@laufenbock.de> Change-Id: I217b04be94e913b75e2bac0a4ae1c43f2411a044 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56509 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* mb/google/veyron: Remove references to EC firmware board namesPatrick Georgi2021-07-231-9/+0
| | | | | | | | | | | | Chrome EC is relatively quick with retiring "old" boards from their tree so when upreving it, the last veyron in that list that wasn't commented out is gone as well. Change-Id: Ie1ef693c8d0947396ee01e5aa5f40ef36c8a317a Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56430 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/cherry: replace magic numbers by the I2C bus nameRex-BC Chen2021-07-232-6/+4
| | | | | | | | | | | | When accessing I2C, we should use the official names (I2Cx) instead of magic numbers. Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I17cc4c87f5ad26deeb5e529d1c106b697a53591b Reviewed-on: https://review.coreboot.org/c/coreboot/+/56504 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/guybrush: Setup EC_IN_RW GPIO and export to payloadKarthikeyan Ramasubramanian2021-07-223-1/+4
| | | | | | | | | | | | | | | | | | EC_IN_RW_OD signal is routed from Google Security Chip to GPIO_91 in the upcoming hardware build. The existing SD_EX_PRSNT signal is dropped in the upcoming hardware build because SD7 support is dropped. Export the EC_IN_RW GPIO for use by payload. BUG=None TEST=Build and boot to OS in Guybrush. Ensure that the device can boot successfully in both recovery and normal mode. Cq-Depend: chromium:3043702 Change-Id: I8986ba007a2d899c510be61664d90430b8d2d384 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56493 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/siemens/mc_ehl1: Disable GSPI in devicetreeWerner Zeh2021-07-221-27/+3
| | | | | | | | | | | Since this mainboard does not use GSPI at all, disable all GSPI ports. Change-Id: I60254e9f4047537d86c972151ec9e33552332959 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56488 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
* mb/siemens/mc_ehl1: Adjust I2C bus enablement in devicetreeWerner Zeh2021-07-221-12/+12
| | | | | | | | | | | | This mainboard uses I2C1 and I2C4 buses only. Disable all the others as they are not connected at all. Change-Id: I4743f6ea6b9a9987ad63b60f56ee9a597a08284b Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56487 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
* mb/siemens/mc_ehl1: Disable power management features for SATAWerner Zeh2021-07-221-2/+2
| | | | | | | | | | | | Features like DevSLP and Aggressive Link Power Management are not supported on this mainboard and are therefore disabled. Change-Id: I3bc650ea78be8587889fb7abfe7075cd9a122198 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56486 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
* mb/google/dedede/var/cret: Add Wifi SAR for cretIan Feng2021-07-223-0/+9
| | | | | | | | | | | | | | Add wifi sar for cret. BUG=b:194163601 TEST=enable CHROMEOS_WIFI_SAR in config of coreboot, emerge-dedede coreboot-private-files-baseboard-dedede coreboot chromeos-bootimage. Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Change-Id: Ic2f3dbc5822c1f4b1c935c87295ba9916e0e359e Reviewed-on: https://review.coreboot.org/c/coreboot/+/56474 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
* mb/siemens/mc_ehl1: Adjust PCIe settings in devicetreeWerner Zeh2021-07-221-8/+8
| | | | | | | | | | | | | This board does not use CLKREQ-signaling for PCIe, so disable the pin assignments. In addition only three clock outputs are used for PCIe, therefore disable all others to improve EMI. Change-Id: I545f890fa55a109df7f44d2c82170874fb769009 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56455 Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/siemens/mc_ehl1: Adjust USB port settings in devicetreeWerner Zeh2021-07-221-15/+15
| | | | | | | | | | | | | | | | | | There are in total three USB ports that are used on mc_ehl1: - Port 1: Type A connector connected to USB2/USB3 port 0 - Port 2: Type A connector connected to USB2/USB3 port 1 - Onboard: connected to USB2 port 2 None of the ports supports overcurrent reporting. Adjust the appropriate UPDs in devicetree to match the hardware configuration. Change-Id: I220637b8e9f03efccacd0955e82cfc0c7a6f53ee Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56454 Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/siemens/mc_ehl1: Remove display related UPDs from devicetreeWerner Zeh2021-07-221-7/+0
| | | | | | | | | | | | | Since mc_ehl1 does not have a display attached nor have a display connector available (pure headless design), remove display related settings from the devicetree. Change-Id: Id31c09fcfba15f55eed19134bd0c2fb887bd2478 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56453 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/brya/variants/redrix: Configure GPIOs according to schematicsWisley Chen2021-07-222-0/+125
| | | | | | | | | | | | | Update initial gpio configuration for redrix BUG=b:192052098 TEST=FW_NAME=redrix emerge-brya coreboot Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Change-Id: I2294fb3bdba832677038cfe24b5014014c7f03e9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56428 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mainboard/google/herobrine: Add configuration for SD card detect pinShaik Sajida Bhanu2021-07-222-1/+8
| | | | | | | | | | | | | | | | Without this configuration, even though there is no SD card it shows as SD card is present and host controller waits for card to respond. BUG=b:182963902 TEST=Validated on qualcomm sc7280 development board with SD card and without SD card, make sure if SD card not present then host controller should not wait for card to respond. Change-Id: I5dc5ba10c98d606d98e7d4f4c41c3e4f45e94452 Signed-off-by: Shaik Sajida Bhanu <sbhanu@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50584 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
* mb/google/brya/variants/primus: Update two GPIOsariel fang2021-07-211-2/+4
| | | | | | | | | | | | | 1. Move M2_SSD_PLN_L to GPP_D3 for power loss notify function. 2. Set GPP_E21 as NC to remove LCLW_DET function BUG=b:190643562 Signed-off-by: Ariel Fang <ariel_fang@wistron.corp-partner.google.com> Change-Id: Id3c60adeb5d35c79a1c700937f93a80ad3587c5e Reviewed-on: https://review.coreboot.org/c/coreboot/+/56420 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/brya: Program Unused Cnvi BT related GPIOs to NCMaulik V Vaghela2021-07-211-0/+13
| | | | | | | | | | | | Program unused Cnvi BT UART GPIOs as NC since we are using Bluetooth over USB mode for Brya. Change-Id: I33a37ceb8a91603d2a193de5bdd1b6885eb3c319 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55317 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/brya: Create taeko variantKevin Chang2021-07-218-0/+45
| | | | | | | | | | | | | | | | | | Create the taeko variant of the brya0 reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0.) BUG=b:193685558 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_TAEKO Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com> Change-Id: If738849bc3103c52a4c4d8a8aaef3f90a62ad5c1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56385 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/brya/var/gimble: Include SPD for MT53E1G32D2NP-046 WT:A and ↵Mark Hsieh2021-07-213-1/+6
| | | | | | | | | | | | | | | | | K4U6E3S4AA-MGCR Add SPD support to gimble for LPDDR4 memory part MT53E1G32D2NP-046 WT:A and K4U6E3S4AA-MGCR. BUG=b:191574298 TEST=USE="project_gimble emerge-brya coreboot" and verify it builds without error. Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: I4bfc18fd42c6ff2675e6f836c2ecc9617fac3aff Reviewed-on: https://review.coreboot.org/c/coreboot/+/56329 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/siemens/mc_apl{1,2,3,5,6}: Set PCI bus master bit only if allowedWerner Zeh2021-07-215-14/+21
| | | | | | | | | | | | Take Kconfig switch PCI_ALLOW_BUS_MASTER into account and set the PCI bus master bit for legacy devices only if it is allowed. Change-Id: I7798a767d528419bb093f301140ab68cc8b9c5ae Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56442 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
* mb/google/brya: Add variant specific soc chip config updateSugnan Prabhu S2021-07-212-0/+13
| | | | | | | | | | | This patch adds support for variant specific soc chip config update function. Change-Id: Ic3a3ae0b409433e6dfa102c5e7a6322d4f78f730 Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56411 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/octopus/variants/ampton: Resume from suspend on critical batteryJames Chao2021-07-211-0/+5
| | | | | | | | | | | | | | | | | | | | | | This patch makes Ampton EC wake up AP from s0ix when the state of charge drops to 2%. Demonstrated as follows: 1. Boot Ampton. 2. Run powerd_dbus_suspend. 3. On EC, run battfake 2. 4. System resumes. BUG=b:189540432 BRANCH=Octopus TEST=Verified on Ampton. Change-Id: I98d8e6ea185e8782ad675d4668678b341ca5d350 Signed-off-by: James Chao <james_chao@asus.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56341 Reviewed-by: Marco Chen <marcochen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/brya/variants/primus: add dram part idMalik_Hsu2021-07-213-2/+8
| | | | | | | | | | | | | | This change adds mem_parts_uesd.txt that contains the new memory parts used by primus and Makefile.inc generated by gen_part_id.go using mem_parts_used.txt. BUG=b:193813079 Signed-off-by: Malik_Hsu <malik_hsu@wistron.corp-partner.google.com> Change-Id: I6aa37114f3a164a4f3c35dfc9b43e1106b825bff Reviewed-on: https://review.coreboot.org/c/coreboot/+/56366 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/herobrine: Retrieve SKU ID from ECPhilip Chen2021-07-213-4/+4
| | | | | | | | | | | | BUG=b:186264627 BRANCH=none TEST=build herobrine Signed-off-by: Philip Chen <philipchen@google.com> Change-Id: Id3faf7af64c0129ec646a01085adc43b561225d2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56354 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
* mb/google/cherry: add mt6360 support for MT8195Rex-BC Chen2021-07-213-12/+55
| | | | | | | | | | | | For new MT8195 devices we will control mt6360 via EC, so we have to add ec function of controlling MT6360 and add CONFIG to separate them. Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: Ic2228f5b45173f0905ea66a3a1f00ec820e0f855 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56446 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* mb/google/cherry: initialize SD card reader using regulator interfaceRex-BC Chen2021-07-211-2/+2
| | | | | | | | | | TEST=boot kernel from sd card pass on Cherry board. Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: Ic20a2f3f053130ded202cf5ec861450f0f18eed0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56437 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/intel/ehlcrb: Update FIVR configsLean Sheng Tan2021-07-211-0/+16
| | | | | | | | | | | | | | | | | | This patch sets the optimized FIVR configs for ehlcrb customized based on the performance measurements to achieve the better power savings in sleep states. - Enable the external V1p05, Vnn, VnnSx rails in S0i3, S3, S4, S5 states. - Update the supported voltage states. - Update max supported current, voltage transition time and RFI spread spectrum. Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Change-Id: I1e30ff6d84bfe078fcce0f968fce6aaab7fd575b Reviewed-on: https://review.coreboot.org/c/coreboot/+/55981 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/cherry: add mt6360 ids for regulator.cRex-BC Chen2021-07-211-0/+4
| | | | | | | | | | Add MTK_REGULATOR_VCC and MTK_REGULATOR_VCCQ for regulator.c. Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: Iedb1036da3c87106157c51cc46b52545faba102c Reviewed-on: https://review.coreboot.org/c/coreboot/+/56436 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/mediatek/mt8195: modify mt6360 interfaceRex-BC Chen2021-07-212-6/+6
| | | | | | | | | | | | With the new definition of mt6360_regulator_id, merge the MT6360 LDO and PMIC interfaces into one. Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I7ccc32cb0a9481d5f55349c152267a44fe09d20a Reviewed-on: https://review.coreboot.org/c/coreboot/+/56435 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* soc/mediatek/mt8195: redefine mt6360_regulator_idRex-BC Chen2021-07-211-2/+2
| | | | | | | | | | | | On MT8195 platforms with BC1.2, we have to use EC to control MT6360 so the mt6360_regulator_id is redefined to match the numbers defined in EC driver. Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I9437edb9776442759ce04c31d315c3760078ffb3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56434 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/intel/adlrvp: Enable I2S audio codecs on ADL-M RVPAnil Kumar2021-07-214-1/+88
| | | | | | | | | | | | | | | | | | - Add configurability using FW_CONFIG field in CBI, to enable/disable I2S codec support for MAX98373 codecs - AUDIO=ADL_MAX98373_ALC5682I_I2S: enable max98373 codec using expansion board Bug=None Test=With CBI FW_CONFIG set to 0x100, check I2S audio output on expansion card Signed-off-by: Anil Kumar <anil.kumar.k@intel.com> Change-Id: If2649647e58c5f30e2b539d534adf2a4e68f4fda Reviewed-on: https://review.coreboot.org/c/coreboot/+/52221 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Revert "mb/google/brya: Enable south XHCI ports 1 and 2"Tim Wawrzynczak2021-07-211-6/+0
| | | | | | | | | | | | | | | | | | This reverts commit f7f715dff38c4a629139b2493ed6e0d7cc2eb36f. Reason for revert: FSP 2207.01 uses the UsbTcPortEn UPD for TCSS XHCI enable BUG=b:184324979 TEST=boot brya, all 3 USB Type-C ports still enumerate devices Change-Id: I82bae21d185247bc0f3580fd6f92abb8eece6732 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56132 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.corp-partner.google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/siemens/mc_ehl: Move SPD data to variant directoryWerner Zeh2021-07-205-3/+4
| | | | | | | | | | | Since the variants can have different memory move the SPD related content to the variant directory. Change-Id: I38aa5e7514437bfcc61c38d64f0ba6f19350810d Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56036 Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/volteer/variants/collis: Fix pen ejection eventFrankChu2021-07-201-1/+1
| | | | | | | | | | | | | | Modify PENH device GPIO GPP_E17 for pen ejection event. BUG=b:192511670,b:193093749 BRANCH=firmware-volteer-13672.B TEST=test pen insert and remove by evtest , SW_PEN_INSERT value 1 when insert pen to pen slot. SW_PEN_INSERT value 0 when remove pen from pen slot. Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com> Change-Id: Ida5e5b35464471a7896cef392e178a3d2c0ea1aa Reviewed-on: https://review.coreboot.org/c/coreboot/+/56331 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao@google.com>
* grunt/treeya: add Realtek ALC5682 codec supportKevin Chang2021-07-194-0/+84
| | | | | | | | | | | | | | | Replace audio codec from DA7219 to Realtek ALC5682. Add Realtek ALC5682 support. BUG=b:185972050 BRANCH=master TEST=check on treeya system ALC5682 audio codec is working normally. Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com> Change-Id: I49c673fd944b2c2a79c4283eee941a16596ba7fa Reviewed-on: https://review.coreboot.org/c/coreboot/+/56100 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
* mb/{google, intel}: Make use of `cpu/intel/cpu_ids.h'Subrata Banik2021-07-193-3/+3
| | | | | | | | | | | Remove inclusion of mp_init.h for getting CPUIDs and use dedicated cpu_ids.h file in SoC directory. Change-Id: I411f4f2c237a9e2d39038ee30f2957698ee053bd Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56412 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
* mb/google/zork/var/vilboz: Add new memory MT40A1G16RC-062E:BFrank Wu2021-07-173-0/+3
| | | | | | | | | | | | | | | Add new ram_id:1000 for memory part MT40A1G16RC-062E:B. BUG=b:193732051 TEST=Generate new spd file and build coreboot. Then boot from the DUT with new memory MT40A1G16RC-062E:B Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: I07c69f628da7871b990c91af4a8244430b4d96a0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56328 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Kangheui Won <khwon@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/intel/adlrvp: Update PMC Descriptor for Alder lake A0(906a0h) siliconSridhar Siricilla2021-07-171-0/+86
| | | | | | | | | | | | | | | | | | | The patch updates PMC Descriptor which is part of Descriptor Region if system equipped with Alder lake A0 silicon. This change allows to use unified Descriptor Region for Alder lake A0(CPU ID:0x906a0) and B0 (CPUD ID:0x906a1) silicons. The change has to be reverted before EOM is enableda on the system. BUG=B:187431859 TEST=Verified PMC Descriptor getting modified for Alder lake B0 silicon if not updated. Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I2a1f60fda7575212bb694fc423bd229452515903 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56073 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
* mb/google/volteer: Deduplicate lockdown configFelix Singer2021-07-1710-20/+0
| | | | | | | | | | | | | | | | The setting `chipset_lockdown` has the same configuration for all variants and they also match with the baseboard configuration. Thus, remove it from the variant overridetrees. Built google/delbin with `BUILD_TIMELESS=1` and coreboot.rom remains the same. Change-Id: I597e4487e7a0e1848d2a2f2c8f8ebd552994aac2 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56199 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/volteer/baseboard: Configure chipset_lockdown separatelyFelix Singer2021-07-171-1/+1
| | | | | | | | | | | | | | | | | | The configuration of the setting `chipset_lockdown` doesn't have any effect for most of the variants since their configuration of `common_soc_config` overwrites the configuration of the baseboard's devicetree. If `chipset_lockdown` is configured separately in the baseboard devicetree, the variant overridetrees reuse its configuration. Thus, move `chipset_lockdown` out of `common_soc_config` in the baseboard devicetree and configure it separately. Change-Id: I595c042cf62680d61f60965710d382bfdcd81671 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56209 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/kahlee/Kconfig: add board-specific MAINBOARD_PART_NUMBERFelix Held2021-07-161-1/+6
| | | | | | | | | | | | | Before the part number for all boards was "Grunt". This patch adds the correct part number/name for all variants. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: If506df0b1027fb09f5027d8b9653b776fe3bdc75 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55681 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/volteer/variants/collis: Redefine GPIO_EC_IN_RW to GPP_F17FrankChu2021-07-161-0/+4
| | | | | | | | | | | | | | | Redefine GPIO_EC_IN_RW to GPP_F17 BUG=b:193091165 BRANCH=firmware-volteer-13672.B TEST=verify FAFT firmware_DevMode Pass Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com> Change-Id: I24f4803dc99ef3fc78852241f3a9e86ec70293d9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56302 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-12 20:42:47 +0000