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* mb/google: Fix log messagesElyes Haouas2022-11-156-24/+13
| | | | | | | | | | Change 'printk(BIOS_DEBUG, "ERROR:' to printk(BIOS_ERR, "'. Change-Id: Id31c25f5b8686f951ab4f331682b82ff327d5e78 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69496 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* mb/google/nissa/var/craask: Remove RFIM settings for CraaskTyler Wang2022-11-151-6/+0
| | | | | | | | | | | | | | Request by RF team, remove RFIM related settings to disable it. BUG=b:239657092 Test=RF team test on DUT and check it's disable Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Change-Id: I1eb4d93c2821cb067628dc1228c6c522d292c739 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69466 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* nb/intel/ironlake: Hook up PCI domain and CPU ops to devicetreeArthur Heymans2022-11-143-0/+6
| | | | | | | | Change-Id: I9dd254eddc12966154776d8a2d43f002567e758f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69290 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/nissa/var/pujjo: Modify touch screen hid to ELAN901CLeo Chou2022-11-141-1/+1
| | | | | | | | | | | | | | Modify touch screen hid for Pujjo board. BUG=b:258586760 TEST=Use the value to boot on Pujjo successfully. Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com> Change-Id: Ia3b374de8cba2125c478814a1890a4b6831715b9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69430 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* drivers/generic/ioapic: Drop poor implementationKyösti Mälkki2022-11-138-125/+22
| | | | | | | | | | | | | | | | | | | | | | | | This disables MP table generation for the affected boards since interrupt routing entries would now be completely missing. The mechanism itself is flawed and redundant. The mapping of integrated PCI devices' INTx pins to IOAPIC pins is dependent of configuration registers and needs not appear in the devicetree.cb files at all. The write_smp_table implementation would skip writing any entry delivering to destination IOAPIC ID 0. This does not follow MP table specification. There were duplicate calls to register_new_ioapic_gsi0(), with another present under southbridge LPC device. Change-Id: I383d55ba2bc0800423617215e0bfdfad5136e9ac Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69488 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* mb/gigabyte/ga-945gcm-s2c,skl: Drop HAVE_MP_TABLEKyösti Mälkki2022-11-131-1/+0
| | | | | | | | | | | | | The weak implementation of write_smp_table() is not useful without DRIVERS_GENERIC_IOAPIC and related entries in devicetree.cb. No interrupt routing entries are present in the generated MP table. Change-Id: I71a209e95ae1fe8c1c90b61c6ac0fb0e7bcc7eca Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69490 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/asus/p5gc-mx: Drop HAVE_MP_TABLEKyösti Mälkki2022-11-131-1/+0
| | | | | | | | | | | | | The weak implementation of write_smp_table() is not useful without DRIVERS_GENERIC_IOAPIC and related entries in devicetree.cb. No interrupt routing entries are present in the generated MP table. Change-Id: Ib50a7656cef40d0d3ffcc408cc0858c1dae7b9e5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69487 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* mb/google/zork: rename baseboard GPIO table getter for clarityMatt DeVillier2022-11-134-5/+5
| | | | | | | | | | | | | | | | | Rename variant_pcie_gpio_table() to baseboard_pcie_gpio_table(), since the GPIO table comes from the baseboard (and is not overridden by any variant). Drop the __weak qualifier as this function is not overridden. This is similar to the change made for skyrim in CB:67809 Change-Id: Idd8ea3446ab7940b21265a3ed8080ba4029c4ff7 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69453 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* mb/emulation/qemu: Move packed attributeMartin Roth2022-11-131-1/+1
| | | | | | | | | | | | | | | The jenkins build complains about this now that clang has been added. src/mainboard/emulation/qemu-q35/cpu.c:37:1: error: attribute '__packed__' is ignored, place it after "union" to apply attribute to type declaration [-Werror,-Wignored-attributes] __packed union save_state { Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Id8faa24239505d808d09c00d825344edc7c4b7d9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69494 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* mb/google/brya/var/agah: Add RPL Support to AgahTarun Tuli2022-11-121-0/+1
| | | | | | | | | | | | | | Enable RPL support for Agah. BUG=b:258432915 TEST=build and boot ADL based Agah. RPL based testing when hardware becomes available. Change-Id: I5437dbf9e7812367a280d1ed659f286fb9b62a68 Signed-off-by: Tarun Tuli <taruntuli@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69398 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/rex: Add Write Protect GPIO to cros_gpiosIvy Jian2022-11-121-1/+3
| | | | | | | | | | | | | | This will enable crossystem to access WP GPIO BUG=b:258048687 TEST= wpsw_cur in crossystem reads the correct gpio Change-Id: I67f4a57025064dbf8c691255b0abae9d3fa0dbd3 Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69468 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/brya/variants/volmar: Disable the unused FP padsRen Kuo2022-11-121-0/+11
| | | | | | | | | | | | | | Disable the unused fingerprinter(FP) gpio for zavala by fw_config FPMCU_MASK field. BUG=b:250807253 TEST=build firmware and veriify the FP function on volmar DUT Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Change-Id: I0af1b7c3e4829ecab98525ead4f078c3eb6485d0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69465 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/brya/var/marasov: Enable ISH driver and firmware nameSubrata Banik2022-11-121-0/+4
| | | | | | | | | | | | | | | BUG=b:234776154 TEST=Build and boot Marasov UFS, copy ISH firmware to host file system /lib/firmware/intel/adl_ish_lite.bin check "dmesg |grep ish", it should show: ish-loader: ISH firmware intel/adl_ish_lite.bin loaded Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ic53a3cbdf83825adc27f37877a14f4f405d4a5ee Reviewed-on: https://review.coreboot.org/c/coreboot/+/69377 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
* mb/google/brya/var/marasov: Select ISH driverSubrata Banik2022-11-121-0/+1
| | | | | | | | | | | | | | | This patch ensures that Marasov selects the ISH driver for devices with UFS enabled. BUG=b:256566011 TEST=Able to build Marasov. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I97a0aa3bc6976be32ddbf1fc6b37c16bb62a62e5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69379 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
* ec/google/chromeec: Deprecate dev_index from google_chromeec_rebootCaveh Jalali2022-11-122-2/+2
| | | | | | | | | | | | | | | This removes the dev_index argument from the google_chromeec_reboot API. It's always set to 0, so don't bother passing it. BUG=b:258126464 BRANCH=none TEST=none Change-Id: Iadc3d7c6c1e048e4b1ab8f8cec3cb8eb8db38e6a Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69373 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/emulation/qemu-q35: Fix running qemu-i386 with SMMArthur Heymans2022-11-121-6/+36
| | | | | | | | | | | | | | | | Depending on whether qemu emulates an amd64 or i386 machine the SMM save state will differ. The smbase offsets are incompatible between those save states. TESTED: Both qemu-system-i386 and qemu-system-x86_64 (v7.0.50) have a working smihandler, ASEG and TSEG. Change-Id: Ic6994c8d6e10fd06655129dbd801f1f9d5fd639f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55138 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* soc/intel/broadwell: Hook up PCI domain and CPU cluster ops to devicetreeArthur Heymans2022-11-124-0/+8
| | | | | | | | | Change-Id: I77a333827552741453d8b575f2a8009b3e1bf8f1 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69301 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* mb/google/brya/var/gladios: Add GL9750 SD card reader supportKevin Chiu2022-11-121-0/+1
| | | | | | | | | | | BUG=b:239513596 TEST=emerge-brask coreboot Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com> Change-Id: I7411e10348c36786000c6918b9b154b7329f3cd0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69436 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* mb/google/brya/var/gladios: Include GL9763E driver for eMMC supportKevin Chiu2022-11-121-0/+1
| | | | | | | | | | | | | Support GL9763E as a eMMC boot disk. BUG=b:239513596 TEST=emerge-brask coreboot Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com> Change-Id: I2b29309615df381f1e24f29fc048c6f9bf216b7f Reviewed-on: https://review.coreboot.org/c/coreboot/+/69425 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/clevo/l140mu: make use of the new clevo/it5570e ec driverMichael Niewöhner2022-11-1110-0/+92
| | | | | | | | | | | | | | | | | | | | | | | Hook up the new EC driver. Tested: - Fn hotkeys work (brightness, display, volume, tp toggle, ...) - Display lid - Sleep/wake - Camera (including Fn toggle) - Bluetooth (both CNVi and PCIe card) - Wi-Fi (both CNVi and PCIe card) - CMOS options Known issues: - Touchpad toggle needs OS setup; see CB:68791 - UCSI is not implemented; see CB:68791 Change-Id: I6c4637936761cd62571b5d19fe2afd65560f49a0 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59850 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/clevo/l140cu: make use of the new clevo/it5570e ec driverMichael Niewöhner2022-11-1110-2/+91
| | | | | | | | | | | | | | | | | | | | | | | Hook up the new EC driver. Tested: - Fn hotkeys work (brightness, display, volume, tp toggle, ...) - Display lid - Sleep/wake - Camera (including Fn toggle) - Bluetooth (both CNVi and PCIe card) - Wi-Fi (both CNVi and PCIe card) - CMOS options Known issues: - Touchpad toggle needs OS setup; see CB:68791 - UCSI is not implemented; see CB:68791 Change-Id: I28ac401ada2945bb58fe862895458b10fed505fe Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68795 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/clevo/l140cu: drop System76 ECMichael Niewöhner2022-11-116-45/+0
| | | | | | | | | | | Drop System76 EC, since the ODM board does not use it. Clevo EC FW support will be added and hooked up cleanly in the follow-up changes. Change-Id: I06abbde238be6d25842472a6a82159413ab52ef5 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59816 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/brya/var/gladios: use i2c1 for TPM supportKevin Chiu2022-11-111-0/+1
| | | | | | | | | | | | | | | This change sets DRIVER_TPM_I2C_BUS to the i2c 1 bus for TPM for the gladios variant. BUG=b:239513596 TEST=emerge-brask coreboot Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com> Change-Id: Id6f2bf2a79df883bcb70171051cec4c577ca3bc4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69424 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com>
* aopen/dxplplusu: Add early GPIO settingsKyösti Mälkki2022-11-112-1/+109
| | | | | | | | | | | Required for 2nd COM port to work. Change-Id: Ib211e9c4b487fadec3d3487f9d745f44d8ca4579 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52815 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* sb,soc/intel: Use acpi_create_madt_ioapic_from_hw()Kyösti Mälkki2022-11-101-16/+3
| | | | | | | | Change-Id: I9fd9cf230ce21674d1c24b40f310e5558e65be25 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55311 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* soc/intel/xeon_sp: Move SMBIOS type 4 override functions from mainboardJingleHsuWiwynn2022-11-101-11/+0
| | | | | | | | | | | | | | | | to soc Move SMBIOS type 4 override functions from mainboard to soc so that all xeon family cpus share same functions without implementing again. Tested=On OCP Deltalake, dmidecode -t 4 shows expected info. Signed-off-by: JingleHsuWiwynn <jingle_hsu@wiwynn.com> Change-Id: I17df8de67bc2f5e89ea04da36efb2480a7e73174 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69363 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
* mb/google/skyrim: Enable SOC_AMD_COMMON_BLOCK_I2C3_TPM_SHARED_WITH_PSPJan Dabros2022-11-101-0/+1
| | | | | | | | | | | | | | | | | | | Skyrim platforms have I2C3 controller which is shared between PSP and X86. In order to enable cooperation, PSP acts as an arbitrator. Enable SOC_AMD_COMMON_BLOCK_I2C3_TPM_SHARED_WITH_PSP, so that proper driver is binded on the OS side. BUG=b:241878652 BRANCH=none TEST=Build kernel and firmware. Run on skyrim and verify TPM functionality. Signed-off-by: Jan Dabros <jsd@semihalf.com> Change-Id: I2a3de8cb2b9241e2d81e02df49f317ac0408d5bb Reviewed-on: https://review.coreboot.org/c/coreboot/+/67675 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* mb/google/herobrine: Update comment of modem status infoVenkat Thogaru2022-11-101-1/+2
| | | | | | | | | | | | | Updated comment as per guidelines. BUG=b:232302324 TEST=none Signed-off-by: Venkat Thogaru <quic_thogaru@quicinc.com> Change-Id: I6a925477a926e7e9d54e42d662768536318ec8e0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69296 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
* mb/amd/chausie/ec.c: Enable WLANFred Reitberger2022-11-101-12/+27
| | | | | | | | | | | | Enable WLAN power and deassert the various radio disables. TEST=boot chausie Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I2d21905001fa776c0d5c864d83dcd697e3febe0a Reviewed-on: https://review.coreboot.org/c/coreboot/+/69319 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
* mb/amd/chausie: Correct naming of EC FWFred Reitberger2022-11-102-5/+5
| | | | | | | | | | | | Change the EC FW CBFS filename prefix to a more accurate "ec/" TEST=build and boot chausie Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: Ib9ee24ca06b29c74cc0a91f9e4789df00ba1ba53 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69276 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
* mb/google/brya/var/marasov: use RPL FSP headersFrank Chu2022-11-101-0/+1
| | | | | | | | | | | | | | | | | | | To support an RPL SKU on marasov, marasov must use the FSP for RPL. Select SOC_INTEL_RAPTORLAKE for marasov so that it will use the RPL FSP headers for marasov. BUG=b:254365935 BRANCH=None TEST=FW_NAME=marasov emerge-brya intel-rplfsp coreboot-private-files-baseboard-brya coreboot chromeos-bootimage Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com> Change-Id: I7874420c0fb51b9cc616cd979ffc9349c381602e Reviewed-on: https://review.coreboot.org/c/coreboot/+/69367 Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
* mb/google/brya/var/marasov: Generate SPD ID for supported memory partsFrank Chu2022-11-103-2/+20
| | | | | | | | | | | | | | | | | | | | | | Add supported memory parts in mem_parts_used list, and generate SPD ID for these parts. DRAM Part Name ID to assign MT62F512M32D2DR-031 WT:B 0 (0000) H9JCNNNBK3MLYR-N6E 1 (0001) MT62F1G32D4DR-031 WT:B 4 (0100) H9JCNNNCP3MLYR-N6E 5 (0101) BUG=b:254365935 BRANCH=None TEST=run part_id_gen to generate SPD id Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com> Change-Id: Ifa0637b47d0017cdb9e26ed32328f4405c0df3f7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69311 Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
* mb/google/brya/var/marasov: Update devicetree setting for marasovFrank Chu2022-11-101-2/+242
| | | | | | | | | | | | | | | update devicetree setting per the schematic BUG=b:254365935 BRANCH=None TEST=Built successfully Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com> Change-Id: Ifa4cb18b8e1a7b162f505ff12612ef808fb7061a Reviewed-on: https://review.coreboot.org/c/coreboot/+/69364 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/nissa/var/craask: Disable stylus GPIO pins based on fw_configTyler Wang2022-11-101-0/+12
| | | | | | | | | | | | | | BUG=b:257879909 Test:Boot to OS on craask and check stylus GPIO pins Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Change-Id: I7e3a2583187c8a8e2616a5272b5a7a61debe982b Reviewed-on: https://review.coreboot.org/c/coreboot/+/69138 Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/nissa/var/craask: Modify DPTF related settingsTyler Wang2022-11-101-8/+8
| | | | | | | | | | | | | | | | | | | | | | Request by thermal team, make below changes: 1) tdp_pl2_override: 12 --> 25 2) pl1.min_power: 3000 --> 5500 3) pl1.time_window_max: 32 * MSECS_PER_SEC --> 28 * MSECS_PER_SEC 4) pl2.min_power: 12000 --> 25000 5) pl2.max_power: 12000 --> 25000 6) pl2.time_window_min: 28 * MSECS_PER_SEC --> 1 7) pl2.time_window_max: 32 * MSECS_PER_SEC --> 1 BUG=b:239495499 TEST=emerge-nissa coreboot Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Change-Id: I88c8c4e6798ec5bc2930dd713e8c8b2c543cfaf9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68523 Reviewed-by: Reka Norman <rekanorman@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Vidya Gopalakrishnan <vidya.gopalakrishnan@intel.com>
* mb/google/nissa/var/pujjo: Update register parameters for SX9324 tunningVictor Ding2022-11-101-13/+32
| | | | | | | | | | | | | | | Update SX9324 related settings based on tunned values from the ODM. This patch supports both legacy and upstream Linux's SX9324 driver. BUG=b:242662878 TEST=i2cdump -y -f 13 0x28 (Verified register values on Pujjo) Signed-off-by: Victor Ding <victording@google.com> Change-Id: I34d8073ffe93e6939f8da0cd7efb8667c0e9ac37 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69366 Reviewed-by: Reka Norman <rekanorman@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/kontron/bsl6/romstage.c: Clean up includesElyes Haouas2022-11-101-5/+4
| | | | | | | | Change-Id: Ie3a08799294729beec83faf819fb1f249c6461cd Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69329 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* Revert "mb/aopen/dxplplusu: Remove board"Kyösti Mälkki2022-11-0917-0/+920
| | | | | | | | | | | | | | | This reverts commit eb76a455cd39ec59b7f2ba28baeec9538befd59e and applies minor fixes to make it build again. PARALLEL_MP was working prior to board removal and no relevant SMI handlers were implemented. So NO_SMM choice is now selected. Change-Id: Ia1cd02278240d1b5d006fb2a7730d3d86390f85b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69339 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* cpu/*: Drop PARALLEL_MP leftoversArthur Heymans2022-11-091-33/+1
| | | | | | | | | | These symbols and codepaths are unused now so drop them. Change-Id: I7c46c36390f116f8f8920c06e539075e60c7118c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69361 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/picasso/acpi: include pci_int_defs.asl from soc.aslFelix Held2022-11-093-9/+0
| | | | | | | | | | | | | | | | | | | Instead of including pci_int_defs.asl in each board's DSDT, include it in the common soc.asl. This moves the PRQM OperationRegion and the PRQI IndexField defined in pci_int_defs.asl into the \_SB scope, but those are defined inside the \_SB scope both in the Picasso reference code and for the AMD SoCs from Cezanne on. TEST=Both Linux and Windows still boot and don't show ACPI errors on Mandolin after moving this inside the \_SB scope Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib4e7bfb15de184cc43cd17c8249be0f59405793f Reviewed-on: https://review.coreboot.org/c/coreboot/+/69188 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
* soc/amd/picasso/acpi: rename pcie.asl to pci_int_defs.aslFelix Held2022-11-093-3/+3
| | | | | | | | | | | | | | This aligns Picasso more with the newer AMD SoCs and also makes it a bit clearer what this file does. Also remove the unneeded tabs at the beginning of each line. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie6e5ee815e4346004bc864a6111a255dc689eae8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69187 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
* nb/intel/haswell: Hook up PCI domain and CPU cluster ops to devicetreeArthur Heymans2022-11-0910-0/+20
| | | | | | | | Change-Id: I955274bc6bda587201f130762c0735c36f5501d1 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69289 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/intel/harcuvar: Fix strict prototype warningArthur Heymans2022-11-091-1/+1
| | | | | | | | | | Clang warns on both the declaration and the definction. Change-Id: I94d979fcdbe41349c59248656066615bffd215b6 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69308 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* mb/prodrive/hermes: Fix format mismatchArthur Heymans2022-11-091-1/+1
| | | | | | | | Change-Id: I2a6947c1a39b115a7c7f5da1c9becfd51f45fad9 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69239 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/siemens/mc_ehl2: Provide I2C timing parameter for SSDTWerner Zeh2022-11-091-0/+12
| | | | | | | | | | | | | | | Provide timing parameter for SSDT generation to achieve the requested 100 kHz speed with a high accuracy. Test: Measure I2C bus clock, high and low times during I2C access from Linux and confirm they match the specification. Change-Id: Ifb6019421b612133b8f25c076519bc0e7200dad8 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69307 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* mb/siemens/mc_ehl2: Add dummy I2C devices to limit the I2C speed in OSWerner Zeh2022-11-091-1/+14
| | | | | | | | | | | | | | | In Linux, the I2C speed defaults to 400 kHz if there is no device registered in ACPI which requests a different speed. Due to board limitations (layout, bus load), 400 kHz are too fast which results in a timing violation. Therefore, add a dummy I2C device to both used I2C buses (I2C1 and I2C2) with a speed of 100 kHz. This will limit the bus speed in Linux accordingly. Change-Id: I507c53c9ec7f763cef18903609231b1a66ed98fa Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69306 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
* mb/google/nissa/var/craask: Add wifi sar tableTyler Wang2022-11-094-0/+25
| | | | | | | | | | | | | | | Add wifi sar table for craask/craaskbowl. Use fw_config to separate different project settings. BUG=b:247652032,b:251287099,b:251287101 Test=emerge-nissa coreboot Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Change-Id: I5c92f0ab53ece12a97068f09241e5298909116aa Reviewed-on: https://review.coreboot.org/c/coreboot/+/68660 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* soc/amd/common/block/spi: Mainboard to override SPI Read ModeKarthikeyan Ramasubramanian2022-11-093-3/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | On certain mainboards due to hardware design limitations, certain SPI Read Modes eg. (Dual I/O 1-2-2) cannot be supported. Add ability to override SPI read modes in boards which do not have hardware limitations. Currently there is an API to override SPI fast speeds. Update this API for mainboards to override SPI read mode as well. BUG=b:225213679 TEST=Build and boot to OS in Skyrim. Observe a boot time improvement of ~25 ms with 100 MHz SPI speeds. Before: 11:start of bootblock 688,046 14:finished loading romstage 30,865 16:FSP-M finished LZMA decompress (ignore for x86) 91,049 Total Time: 1,972,625 After: 11:start of bootblock 667,642 14:finished loading romstage 29,798 16:FSP-M finished LZMA decompress (ignore for x86) 87,743 Total Time: 1,943,924 Change-Id: I160b56f6201a798ce59e977ca40301e23ab63805 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68946 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jon Murphy <jpmurphy@google.com>
* mb/google/nissa/var/xivu: Add Hynix new memory supportIan Feng2022-11-093-1/+3
| | | | | | | | | | | | | | | | | | | Add new ram_id:0 (0000) for memory part H9JCNNNCP3MLYR-N6E. DRAM Part Name ID to assign H9JCNNNCP3MLYR-N6E 0 (0000) BUG=b:257867226 TEST=Use part_id_gen to generate related settings and emerge-nissa coreboot Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Change-Id: If663afbcd2e0457636f4a1c7475f1e3e40f0dd96 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69312 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com>
* drivers/i2c/sx9324: Add support for Linux's SX9324 driverVictor Ding2022-11-093-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SX9324 driver is updated per Linux's documentation found at https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/iio/proximity/semtech,sx9324.yaml Supporting logic for the deprecated SX932x driver is hence guarded by DRIVERS_I2C_SX9324_SUPPORT_LEGACY_LINUX_DRIVER This patch by itself does not introduce functional changes to any board. The legacy SX932x Linux driver never reached upstream Linux and is only available in ChromeOS kernel fork of 4.4 and 5.4. Linux later accepted a different implementation named SX9324 and has been available since 5.4. Ideally all variants should adopt the new driver; however, during the transition phase, coreboot must support both drivers. It is better to have a single firmware build that can work with both Linux kernel drivers by specifying both sets of properties. Legacy driver support should be deleted once all variants finish migration. BUG=b:242662878 TEST=Dump ACPI SSDT then verify _DSD entries related to the legacy SX932x driver are identical w/ and w/o this patch (Tested on Craask and Nivviks) Change-Id: I42cd6841c3a270c242ed2e739db245e858eadb3b Signed-off-by: Victor Ding <victording@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69192 Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-10 18:48:44 +0000