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* mb/amd/chausie: Add Kconfig prompts to EC stringsMarshall Dawson2022-08-071-2/+2
| | | | | | | | | | | | Make the default Microchip EC firmware path/to/file values overridable by adding prompts to the strings. Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: I300f78a11960dbe193165fcb379b7190e3de4545 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66446 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* mb/google/rex: Remove depedency on board id for early GPIO configTarun Tuli2022-08-071-5/+16
| | | | | | | | | | | | | | | | | | This adds a default early GPIO table in the case of us not being able to identify a valid board ID. Primarily, this is useful in the case of EC issues to ensure that debug interfaces (e.g. UART) are always up and available. BUG=b:238165977 TEST=Boots and no errors on simics Signed-off-by: Tarun Tuli <taruntuli@google.com> Change-Id: I135dc6c29bc23195afe5c78eb79992691652d9e4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66394 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* mb/google/brya/variants/agah: update dptf settingTony Huang2022-08-071-8/+46
| | | | | | | | | | | | | | | | 1. Add active policy 2. Set critical policy trigger point to 105C 3. Correct TSR location BUG=b:240634844 TEST=emerge-draco coreboot values provided and verified by thermal team Change-Id: I0d91bad03cbdeea5c84b533580ac98072ce0110b Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66351 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
* mb/google/brya/acpi: Fix PERST# handling in GC6 exitTim Wawrzynczak2022-08-071-1/+1
| | | | | | | | | | | | | | | PERST# is supposed to be de-asserted in GC6 exit, but the original patch used the CTXS Method, which drives a GPIO low, instead of STXS, because PERST# is active-low. This patch fixes that. BUG=b:214581763 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ib0adb8efe5e2cc733ae2228614c58c124ba3f11b Reviewed-on: https://review.coreboot.org/c/coreboot/+/66402 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
* mb/google/brya/var/ghost: Disable LID_SHUTDOWNCaveh Jalali2022-08-071-0/+1
| | | | | | | | | | | | | | | | The lid sensor is on a daughterboard which can cause unintended shutdowns when not connected. Disable lid sensor based shutdown behavior in depthcharge until we have a better solution. BUG=b:240005819 BRANCH=firmware-brya-14505.B TEST=booted ghost, no longer shuts down due to missing lid sensor Change-Id: I69f70255dee1b69e05b112c0174f5f52d1368837 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66295 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/brya/acpi: Fix NVJT subfunction IDsTim Wawrzynczak2022-08-071-2/+2
| | | | | | | | | | | | | | | | The POWERCONTROL and PLATPOLICY NVJT subfunctions were incorrectly set to 2 and 3, respectively. While looking at the ACPI code, Nvidia noticed these are supposed to be 3 and 4, also respectively, so this patch fixes that. BUG=b:214581763 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I0f808aba7072b943ee2fad20e06ff39a9b54903d Reviewed-on: https://review.coreboot.org/c/coreboot/+/66374 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
* mb/google/rex: Add memory config for rexTarun Tuli2022-08-061-2/+57
| | | | | | | | | | | | | Configure the rcomp, dqs and dq tables based on the schematic dated July 17/2022 and Intel Kit #573387. TEST=Built successfully Signed-off-by: Tarun Tuli <taruntuli@google.com> Change-Id: I092f42db252052382d377a4ae48dc25f73080a3b Reviewed-on: https://review.coreboot.org/c/coreboot/+/66202 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/brya/var/vell: Set GPP_B2 NC for RGB keybaordRobert Chen2022-08-051-1/+1
| | | | | | | | | | | | | | | When GPP_B2 output high, there is a leakage path. This patch fix it by setting the pin NC. BUG=b:233959105 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot Change-Id: I3c833d5d62c715960dcb27494a0b9b93c91e8f2f Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66382 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
* mb/intel/adlrvp: shorten MAINBOARD_PART_NUMBER to fix buildNick Vaccaro2022-08-041-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Building firmware for Brya is currently broken due to the RO_FWID region for adlrvp_m_ext_ec bloating past 64 characters. The CONFIG_MAINBOARD_PART_NUMBER is catenated onto the CONFIG_MAINBOARD_VENDOR string, which for Intel, makes for a very long trunk string that the kernel version will then be added to form the RO_FWID string. For Intel, that trunk string is already pretty long at : "Intel Corporation_Alder Lake Client Platform". Shortening the CONFIG_MAINBOARD_PART_NUMBER should address this issue for now. BUG=b:241273391 TEST="emerge-brya coreboot chromeos-bootimage" and verify it builds successfully Change-Id: Ie862c87dd9a24743f249f1b10862ca6f3295db23 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66397 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
* mb/google/skyrim: Enable PSP verstageKarthikeyan Ramasubramanian2022-08-031-1/+8
| | | | | | | | | | | | | Enabling required config items to execute verstage in PSP. BUG=b:217414563 TEST=Build and boot to OS in Skyrim with PSP verstage. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: Iee14dc80cb6691acb5cb59a21da5a3dff69f7dd2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66135 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/geralt: Implement SKU ID and RAM codeRex-BC Chen2022-08-033-0/+94
| | | | | | | | | | | | | | | | - Retrieve the SKU ID for Geralt via CBI interface. If that failed (or no data found), fall back to ADC channels for SKU ID. - The RAM code is implemented by the resistor straps that we can read and decode from ADC. TEST=build pass BUG=b:236331724 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I31626e44bd873a3866c9bd1d511b476737f15a20 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66275 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/geralt: Configure GPIOsRex-BC Chen2022-08-033-1/+25
| | | | | | | | | | | | | | | | | | | Configure ChromeOS specific GPIOs: - Open-drain pins to high-z mode: GPIO_EC_AP_INT_ODL, GPIO_GSC_AP_INT_ODL and GPIO_WP_ODL. - GPO mode: GPIO_AP_EC_WARM_RST_REQ, GPIO_EN_SPKR and GPIO_XHCI_INIT_DONE. This patch is based on MT8188G_GPIO_Formal_Application_Spec_V0.3. TEST=build pass BUG=b:236331724 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I84d3f62ec8a3966fe1982d5d4cf6ff270450d4bf Reviewed-on: https://review.coreboot.org/c/coreboot/+/66274 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/geralt: Configure TPMRex-BC Chen2022-08-034-0/+27
| | | | | | | | | | | | | Initialize I2C bus 1 for TPM control. TEST=build pass BUG=b:236331724 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: If5807c9bb39260315ecbc55305def483bd2b8c51 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66273 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/dedede/var/beadrix: Update SoC gpio pin of DMICTeddy Shih2022-08-031-0/+5
| | | | | | | | | | | | | | | | | | | | Update SoC GPIO setting of unused DMIC channel according to beadrix schematics. GPP_S2 : NF2 -> NC (DMIC1_CLK) GPP_S3 : NF2 -> NC (DMIC1_DATA) BUG=b:203113413, b:237224862 BRANCH=None TEST=on beadrix, validated by beadrix's DMIC working properly. Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com> Change-Id: Ibe2f432cd74b546218ff4ee6e428e9eed9ac611f Reviewed-on: https://review.coreboot.org/c/coreboot/+/65381 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ivan Chen <yulunchen@google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* mb/google/dedede/var/drawcia: Add Wifi SAR for oscinoShon Wang2022-08-031-2/+15
| | | | | | | | | | | | | | | | | | | | Add wifi sar for oscino BUG=b:240373077 BRANCH=dedede TEST=enable CHROMEOS_WIFI_SAR in config of coreboot, emerge-dedede coreboot-private-files-baseboard-dedede coreboot chromeos-bootimage. Cq-Depend: chrome-internal:4893022 Change-Id: I44cbe8ee08d6136ed116623046893c9749795e50 Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66176 Reviewed-by: Ivan Chen <yulunchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* mb/google/dedede/var/beadrix: Update SoC gpio pin of BC1.2Teddy Shih2022-08-032-0/+3
| | | | | | | | | | | | | | | | | | | | Update SoC GPIO setting of adding BC1.2 SLGC55545 according to beadrix schematics. GPP_A18 : NC -> NF1 (USB_OC0_N) BUG=b:214393595, b:226294980 BRANCH=None TEST=on beadrix, validated by beadrix's Type A working properly. Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com> Change-Id: I746931582cc12f49f7f1c667563350ebac8ddfa1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65377 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Super Ni <super.ni@intel.corp-partner.google.com> Reviewed-by: Ivan Chen <yulunchen@google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* mb/prodrive/atlas: Select FSP_TYPE_IOTLean Sheng Tan2022-08-031-0/+1
| | | | | | | | | | | Atlas uses IoT FSP. Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: I4c20600e0b62367e6e58908cf9cf916f309e6362 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66368 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Christian Walter <christian.walter@9elements.com>
* mb/google/brya: Enable DRIVERS_GENESYSLOGIC_GL9755 for kuldaxDavid Wu2022-08-031-0/+1
| | | | | | | | | | | | | Enable DRIVERS_GENESYSLOGIC_GL9755 support for kuldax. BUG=b:232858957 TEST=build pass Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I1b2c0bff8497d727c697ea6287078055a39bd1f3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66332 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
* mb/google/brya/variants/agah: set tcc_offset to 3Tony Huang2022-08-031-0/+1
| | | | | | | | | | | | | | | | Set tcc_offset value to 3 in devicetree for Thermal Control Circuit (TCC) activation feature. This value is suggested by Thermal team. BUG=b:240600260 TEST=emerge-draco coreboot verified by thermal team Change-Id: I3044643d52f1d6e883beb3ec87a77f32d086f46c Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66252 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
* mb/google/herobrine: Add support to enable displayVinod Polimera2022-08-032-0/+41
| | | | | | | | | | | | | | | This change adds support to enable edp gpios, display init for herobrine. BUG=b:182963902,b:216687885 TEST=Validated on qualcomm sc7280 development board. Monitor name: LQ140M1JW49 Change-Id: I01dbe23afbb3d41d87f24cb7dcfa456cb7f133fb Signed-off-by: Vinod Polimera <quic_vpolimer@quicinc.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64885 Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/dedede/var/pirika: Add Elan touchscreen supportFrankChu2022-08-021-1/+21
| | | | | | | | | | | | | Enable I2C2 and register touchscreen ACPI device for pirika. BUG=b:236564261 TEST=touch screen is functional. Signed-off-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com> Change-Id: Id2fd5606b7126eabc1c88bf516198ff00b5d75dd Reviewed-on: https://review.coreboot.org/c/coreboot/+/65967 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* mb/google/brya/var/ghost: Enable AMP powerEric Lai2022-08-021-2/+2
| | | | | | | | | | | | | | | Follow latest schematic, GPP_A17 is used to enable AMP power. BUG=b:240006200 BRANCH=firmware-brya-14505.B TEST=Check I2C scan can see the AMP return ACK. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: Ia6c52302a12ddec68303714ac07e96a65a8f8fb8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66325 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Caveh Jalali <caveh@chromium.org>
* mb/system76: Change touchpad detection methodTim Crawford2022-08-0212-14/+14
| | | | | | | | | | | | | | | | | | Use the new "detect" method instead of "probed". Fixes an uncommon issue where i2c-hid fails to initialize the device on Linux. Tested on: gaze15, gaze16-3060, lemp10, oryp8 Tested: - Linux: Touchpad works across 50 reboots - Windows: Touchpad is still detected as an I2C HID device - Windows: Extra I2C HID devices are not shown in Device Manager Change-Id: I6a899c64a6d77b65a2ae57ab8df81cd84b568184 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66129 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
* mb/google/geralt: Enable Chrome ECRex-BC Chen2022-08-025-7/+26
| | | | | | | | | | | | | Initialize SPI bus 0 for Chrome EC control. TEST=build pass BUG=b:236331724 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I6de5ea8a0273a3b0c725e4cdbcf69f4db74c5db7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66272 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* mb/google/nissa/craask: Add eMMC DLL tuning valueSimon Yang2022-08-021-0/+45
| | | | | | | | | | | | | | | | Configure eMMC DLL tuning values for Craask board. BUG=b:238985924 TEST="Use the value to boot on Nivviks and Craask successfully." Change-Id: I14f3e2329404cca94e14034d1fb52fcb99a2ddc9 Signed-off-by: Simon Yang <simon1.yang@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66218 Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Reka Norman <rekanorman@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Henry Sun <henrysun@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
* mb/google/rex: Enable CSE Lite SKUSubrata Banik2022-08-021-0/+1
| | | | | | | | | | | | | | | The first CSE Lite SKU is available, therefore enable the Kconfig option to have the CSE reboot the system into its RW FW during a cold boot. BUG=b:240228892 TEST=TBD Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I00ef4176cf08cbeed06e446cfe68f06cb1ea27b4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66287 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/herobrine: Add PCIe domain supportVeerabhadrarao Badiganti2022-08-011-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add PCIe domain support for herobrine by enabling it in the devicetree. BUG=b:182963902,b:216686574,b:181098581 TEST=Verified on Qualcomm sc7280 development board with NVMe card (Koixa NVMe, Model-KBG40ZPZ256G with FW AEGA0102). Confirmed NVMe is getting detected in response to 'storage init' command in depthcharge CLI prompt. Output logs: ->dpch: storage init Initializing NVMe controller 1e0f:0001 Identified NVMe model KBG40ZPZ256G TOSHIBA MEMORY Added NVMe drive "NVMe Namespace 1" lbasize:512, count:0x1dcf32b0 * 0: NVMe Namespace 1 1 devices total Also verified NVMe boot path, that is depthcharge is able to load the kernel image from NVMe storage. Change-Id: Ied8fbbc8d20698ee081d93ba184b7d0291bb6a76 Signed-off-by: Veerabhadrarao Badiganti <quic_vbadigan@quicinc.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65137 Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/brya: Disable the Package C-state demotionZhixing Ma2022-08-011-0/+4
| | | | | | | | | | | | | | | | | | | | Disabling the Package C-state demotion feature for brya baseboard as a work around to the S0ix issue and also this doesn't have any impact on the power and performance measured and verified by the PNP team. This feature will be enabled after its functionality is verified with no issues and also based on its impact on PNP. BUG=none BRANCH=firmware-brya-14505.B TEST=Boot and verified that S0ix issue is resolved. Signed-off-by: Zhixing Ma <zhixing.ma@intel.com> Change-Id: Id3941c8870d41b25488c8ac5d38534fa94664d4a Reviewed-on: https://review.coreboot.org/c/coreboot/+/65805 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
* mb/hp/z220_series: Improve the port for z220_sff_workstationBill XIE2022-07-302-2/+6
| | | | | | | | | | | | | | | | | | | - Move configs for PCIe ports not present on z220_sff_workstation from the devicetree.cb of base board to the overridetree.cb of z220_cmt_workstation. - Add a note for ME/AMT Flash Override jumper, for it is hard to flash from OEM firmware either internally or externally without closing this jumper. - Add a side note for similar HP Compaq Elite 8300 SFF. Signed-off-by: Bill XIE <persmule@hardenedlinux.org> Change-Id: I35d8b97f52a83910a61c12b1f7367ee7a19a9ad7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65703 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/brask/variants/moli: Add DPTF setting in MoliRaihow Shi2022-07-301-0/+74
| | | | | | | | | | | | | DPTF Policy and temperature sensor values from thermal team. BUG=b:236294162 TEST=emerge-brask coreboot Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com> Change-Id: Iebcfb74c4bc719e6d8d8d9317435becd912eaf85 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65657 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
* mb/google/rex: Perform display configuration overrideSubrata Banik2022-07-291-0/+11
| | | | | | | | | | | | | | This patch enables display port configuration as per the Rex schematics. TEST=Able to dump FSP UPD to ensure the override is successful. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I9e81d037416e46e52cb72344425d6d8725dae192 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66209 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com>
* mb/google/nissa/var/pujjo: Enable OZ711LV2LN SD card controllerStanley Wu2022-07-291-0/+1
| | | | | | | | | | | | | | Pujjoflex support OZ711LV2LN SD card controller, Select the Bayhub LV2 driver for OZ711LV2LN SD card. BUG=b:215487382 TEST=Build FW and checking SD card work as expected in OS. Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com> Change-Id: I6759fde1eaf24599a1fdb364d6e78f4e4e12f311 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66178 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
* mb/google/rex: Add LP5 RAM IDsTarun Tuli2022-07-293-0/+6
| | | | | | | | | | | | | | | | | | Create RAM IDs for: DRAM Part Name ID to assign MT62F512M32D2DR-031 WT:B 0 (0000) MT62F1G32D2DS-026 WT:B 1 (0001) MT62F2G32D4DS-026 WT:B 2 (0010) BUG=b:240289148 TEST=emerge-rex coreboot Signed-off-by: Tarun Tuli <taruntuli@google.com> Change-Id: Ib24e07bca363984db3484aa500f7d6ea4817e517 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66164 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
* mb/google/geralt: Initialize RTC and clk_buf in romstageRex-BC Chen2022-07-291-0/+4
| | | | | | | | | | | | TEST=build pass. BUG=b:233720142 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I869c0879d09e00cf66882adb728c9ccb6ac57e03 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66183 Reviewed-by: Yidi Lin <yidilin@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/rex: Enable CNVi BT CoreSubrata Banik2022-07-291-0/+3
| | | | | | | | | | This patch override `CnviBtCore` FSP UPD. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I90c9b360969aada0b0e031d62b48476fac5cee0e Reviewed-on: https://review.coreboot.org/c/coreboot/+/66208 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* mb/google/brya/var/ghost: Enable CS42L42 codecEric Lai2022-07-293-2/+21
| | | | | | | | | | | | | | | Add CS42L42 support in device tree. BUG=b:240006200 BRANCH=firmware-brya-14505.B TEST=Check cs42l42 driver can probe successfully in kernel. cs42l42 i2c-10134242:00: Cirrus Logic CS42L42, Revision: B1 Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I861f47c12f4cebb016a4cfbe225f97d34d55e233 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66223 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org>
* mb/google/brya/var/ghost: Update all I2C buses speed to fastEric Lai2022-07-291-23/+5
| | | | | | | | | | | | | | | Remove the parameter and set I2C bus speed to fast. Will fill the tuning value after real tuning. BUG=b:240006200 BRANCH=firmware-brya-14505.B TEST=build passed. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: Iba7fe4551959617ecfa49719c1124bf85d624c31 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66220 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org>
* mb/google/brya: Create gaelin variantRaymond Chung2022-07-295-0/+28
| | | | | | | | | | | | | | | | | | Create the gaelin variant of the brask reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:239514438 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_GAELIN Signed-off-by: Raymond Chung <raymondchung@ami.corp-partner.google.com> Change-Id: I7f1ff8690c7c57f8960e004d0490d5cede8667f3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66177 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao@google.com>
* mb/google/dedede/var/drawcia: Enable weida touchscreenShon Wang2022-07-291-0/+14
| | | | | | | | | | | | | | | Add weida touchscreen support for drawcia. BRANCH=dedede TEST=Build and verify that touchscreen works on drawcia. Change-Id: Ic76f3529771c6eeeafef7ca50fc400065aac2211 Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65471 Reviewed-by: Ivan Chen <yulunchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Henry Sun <henrysun@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* mb/google/nissa/var/joxer: Correct i2c address for touchscreenMark Hsieh2022-07-281-1/+1
| | | | | | | | | | | | | set i2c address to 0x14 for Goodix touchscreen BUG=b:239180430 TEST=USE="project_joxer emerge-nissa coreboot" Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: I11a2d9c684bc511b3942f88f74a2495e796bc3c2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66192 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
* mb/google/brya/acpi: Add L23 entry/exit sequences during dGPU GCOFFTim Wawrzynczak2022-07-281-0/+2
| | | | | | | | | | | | | | | | | | When the dGPU is entering GCOFF, the link should first be placed into L2/L3 as appropriate for the design, then when exiting, the link should be placed back into L0. This patch fixes that oversight. BUG=b:239719056 TEST=build Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ia3bdfe5641216675e06ebe82ffe58bf8c049b26b Reviewed-on: https://review.coreboot.org/c/coreboot/+/66200 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
* mb/google/brya/var/agah: Modify GPP_A8 programmingTim Wawrzynczak2022-07-281-1/+1
| | | | | | | | | | | | | | | | The EEs noticed this pin was misbehaving; it was accidentally set to a low output, but should be open-drain (NC). This patch fixes that. BUG=b:237837108 TEST=verified by EEs Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ie76a951320c49b9fbc1f23b96f04c9f86ad44d42 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66204 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
* mb/google/brya/var/agah: Modify GPP_F14 programmingTim Wawrzynczak2022-07-281-0/+2
| | | | | | | | | | | | | | | | | | For some yet unknown reason, when this GPIO is locked, there is an interrupt storm for IRQ #9 apparently caused by GPE 0x66. GPP_F14 is set to GPE 0x64 on the ADL platform, so this doesn't quite make sense. This patch removes the lock and fixes this IRQ storm, but the root cause is not identified yet. BUG=b:236997604 TEST=`grep ' 9:' /proc/interrupts` shows a reasonable value now Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I3d1c66fac80a173798ae33e48b1776d9f4fb5eaa Reviewed-on: https://review.coreboot.org/c/coreboot/+/66201 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
* mb/google/brya/var/agah: Optimize dGPU GCOFF entryTim Wawrzynczak2022-07-282-4/+1
| | | | | | | | | | | | | | | | | | | | | After staring at lots of scope shots, the EE has determined that a few modifications to the GCOFF sequence can be made: - Remove delay between PERST# assertion and GPU_ALLRAILS_PG deassertion - Remove delay after ramping down FBVDD This patch implements these minor changes. BUG=b:240199017 TEST=verified by EE Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I7d492b3e65a231bc5f64fe9c3add60b5e72eb072 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66199 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
* mb/google/brya/var/agah: Update ASPM settings for dGPUTim Wawrzynczak2022-07-282-5/+1
| | | | | | | | | | | | | | | | | | After some debugging, it has been determined that the ASPM L0s substate is functional, but there is still some problem with ASPM L1 substates, so this patch updates ASPM status for the dGPU from disabled to L0s only. BUG=b:240390998 TEST=tested with nvidia tools Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I584bdbf26eda20246034263446492bf4daf5f3b6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66198 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
* mb/google/brya/var/anahera{4es}: Add H54G68CYRBX248 supportWisley Chen2022-07-286-2/+6
| | | | | | | | | | | | | | Generate SPD id for hynix H54G68CYRBX248 BUG=b:239899929 BRANCH=firmware-brya-14505.B TEST=run part_id_gen to generate SPD id Change-Id: I96babe340678ca9b82b06d3193b93a7676f23fef Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66072 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/brya/var/redrix{4es}: Add H54G68CYRBX248 supportWisley Chen2022-07-286-2/+6
| | | | | | | | | | | | | | Generate SPD id for Hynix H54G68CYRBX248 BUG=b:239888704 BRANCH=firmware-brya-14505.B TEST=run part_id_gen to generate SPD id Change-Id: I9412b988bcdb0c744e016f3add6dacda8185d6db Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66071 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/brya/var/ghost: Correct CNVi pinsEric Lai2022-07-281-11/+11
| | | | | | | | | | | | | | | | GPP_F0 to GPP_F4 is for CNVi and should be NF1. GPP_F5 is for CNVi CLK_REQ, and should be NF3 CRF_XTAL_CLKREQ. BUG=b:240006200 BRANCH=firmware-brya-14505.B TEST=CNVi wifi can get probed in kernel. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: Ice3fde3a457f6f5c058c0a7d3ca2e63775bda96c Reviewed-on: https://review.coreboot.org/c/coreboot/+/66175 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* google/trogdor: Add new variant Pazquel360Yunlong Jia2022-07-282-0/+5
| | | | | | | | | | | | | | | This patch adds a new variant called Pazquel360 \ that is identical to Pazquel for now. BUG=b:239987191 TEST=make Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com> Change-Id: I0a9ca4a59fb44256d0d8fcdbdf2a7db533c84412 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66150 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Bob Moragues <moragues@google.com>
* mb/google/rex: Initial setup for ramstage/early gpio configTarun Tuli2022-07-281-19/+417
| | | | | | | | | | | | | | | This adds the initial gpio configuration for the rex initial variant. BUG=b:238165977 TEST=Boots and no errors on simics Change-Id: I55ab31c7943e22df9cec8db4a9f0c3ab6f065ae1 Signed-off-by: Tarun Tuli <taruntuli@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65952 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-23 09:14:38 +0000