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* mb/google/rex: Set GPIO Tier-1 GPEs in devicetreeKapil Porwal2022-07-251-0/+5
| | | | | | | | | | | | | | | | | Set GPE route as GPE0_DW0 -> GPP_A GPE0_DW1 -> GPP_E GPE0_DW2 -> GPP_F BUG=b:224325352 TEST=Verified in emulator that there is no regression Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I5e3e09cfc06d2556ea32cca23b3dae114a510498 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66011 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* mb/google/rex: Override LP5 CCC configSubrata Banik2022-07-251-1/+3
| | | | | | | | | | | | | | | | This patch overrides `Lp5CccConfig` UPD as per the CCC mapping data captured from the Rex schematics dated 07/16. BUG=b:224325352 TEST=Able to build Google/Rex. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ia1d9e3665cff74a803e730c76f62773996efb3dd Reviewed-on: https://review.coreboot.org/c/coreboot/+/66049 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/starlabs/lite: Add support for VBOOTSean Rhodes2022-07-254-0/+44
| | | | | | | | | | | Add the required files to support VBOOT for when it is enabled. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I083107b21c23f42193fc88aa174ec22850f45bc8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65705 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
* mb/google/nissa/var/pujjo: Add new supported memory partLeo Chou2022-07-253-0/+3
| | | | | | | | | | | | | | | | | Add pujjo new supported memory parts in mem_parts_used.txt. Generate SPD id for this part. Micron MT62F1G32D4DR-031 WT:B BUG=b:239776504 TEST=Use part_id_gen to generate related settings Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com> Change-Id: I95eb194ecbd5d39f66eb566132e75af056899325 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66039 Reviewed-by: Reka Norman <rekanorman@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
* mb/google/rex: Add memory configuration board strapsSubrata Banik2022-07-252-2/+15
| | | | | | | | | | | | | | | | This patch reads various memory configuration GPIOs to fill in below details: 1. variant_memory_sku() 2. variant_is_half_populated() BUG=b:224325352 TEST=Able to build Google/Rex. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I23bad8c78523cb56008e6d67e7776e57e42fbeb9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66041 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
* mb/lenovo: Integrate W541 into haswell mainboardFelix Singer2022-07-2420-321/+14
| | | | | | | | | | | Lots of code from lenovo/haswell can be reused for lenovo/w541. Thus, integrate it into lenovo/haswell and make it a variant. Change-Id: If99d842cff777fe27ff63baabc447e69b9d0333c Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63514 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
* mb/lenovo/haswell: Make INT15 support T440p specificFelix Singer2022-07-244-2/+2
| | | | | | | | | | | In preparation to CB:63514, make the INT15 support specific for the T440p variant since the W541 doesn't support it currently. Change-Id: I8dfcc061e1b8a831f75bf9a8035770cb678a85d4 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66106 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/lenovo/haswell: Hook up variants MakefileFelix Singer2022-07-241-0/+2
| | | | | | | | Change-Id: I36091118d98f71dc4141aca4e45858a22d519a9b Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66107 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* mb/google/rex: Add GBB related configsSubrata Banik2022-07-231-1/+8
| | | | | | | | | | | | | | | | This patch adds more GBB related configs. Select `HAS_RECOVERY_MRC_CACHE` config. Additionally, move VBOOT_LID_SWITCH config under VBOOT config. TEST=Able to build the Google/Rex. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I28976200cbd70dc23f58868ee89c0ac700793be9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66007 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com>
* mb/google/brya/var/skolas4es: Correct _PLD valuesNick Vaccaro2022-07-231-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | This patch is to denote the correct value of ACPI _PLD for USB ports. +----------------+ | | | Screen | | | +----------------+ C2 | | A0 C0 | MLB DB | C1 | | +----------------+ BUG=b:216490477 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot Change-Id: I96202b9ac9586975e960d6577d279c995c67f34e Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66031 Reviewed-by: Won Chung <wonchung@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/system76/tgl-u: Convert galp5 to a variantTim Crawford2022-07-2322-377/+46
| | | | | | | | Change-Id: I49185352002f6df2f9e9ab9c39d44cc9247b41b5 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64527 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* mb/system76/tgl-u: Convert darp7 to a variantTim Crawford2022-07-2322-377/+19
| | | | | | | | Change-Id: I6b3fe8f4acbb5a2f9fca605e07854ebcc3f2a065 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64526 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* mb/system76/tgl-u: Convert lemp10 to variant setupTim Crawford2022-07-2322-151/+159
| | | | | | | | Change-Id: I11f2ebb94b0e9a3e2c18c5b2071ccc3e03c16655 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64525 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* soc/intel/cannonlake: Set MAX_CPUS based on the SoC and PCHFelix Singer2022-07-237-25/+0
| | | | | | | | | | | | Set the default value for MAX_CPUS in the SoC config and drop it from the mainboards where it is set to those values. Change-Id: Ib56fdcfe770ef736a2c5e183481d9f9966570e6d Signed-off-by: Felix Singer <felixsinger@posteo.net> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52607 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* mb/google/skyrim/var/skyrim: Add two supported memory partsAmanda Huang2022-07-233-3/+8
| | | | | | | | | | | | | | | | Add two memory parts and generate the associated DRAM part ID. 1) Hynix H9JCNNNBK3MLYR-N6E 2) Hynix H58G56AK6BX069 BUG=b:228415394 TEST=none Change-Id: I0f5ca291e02e209032e2533f4b2d4241b5e62e42 Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66062 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* mb/google/nissa/var/xivu: Disable WFC and pen garage based on fw_configIan Feng2022-07-233-3/+55
| | | | | | | | | | | | | | | | | | Use fw_config Bit 0 and Bit 1 to control: Bit 0 = 0 --> enable WFC Bit 0 = 1 --> disable WFC Bit 1 = 0 --> enable pen garage wake Bit 1 = 1 --> disable pen garage wake BUG=b:238045498 TEST=emerge-nissa coreboot chromeos-bootimage Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Change-Id: I85bc4753bfd16fd460286aa2b3bb5f3341049f61 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66043 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
* mb/starlabs/lite: Simplify the flash layoutSean Rhodes2022-07-221-99/+53
| | | | | | | | | | Remove the sections that coreboot doesn't need to know about. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ide6c0d44f1f9ad9b962d2b8e14ac91e87f5ca031 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65453 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/brya/var/skolas4es: add WFC definitions to fw_configNick Vaccaro2022-07-221-1/+5
| | | | | | | | | | | | | | | | | | | | Reserve bits 15 and 16 in the fw_config to be used to specify WFC population status. Possible values for field WFC bits include: option WFC_ABSENT 0 option_WFC_MIPI_OVTI5675 1 option WFC_MIPI_OVTI8856 2 BUG=b:239613517 BRANCH=firmware-brya-14505.B TEST='emerge-brya coreboot' and make sure it compiles successfully. Change-Id: If797b79f0d094816eeb3df7bfded06e92e4e6a32 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65989 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/rex: Add TPM device to Kconfig and devicetreeKapil Porwal2022-07-223-1/+24
| | | | | | | | | | | | | | | | | | Add TPM device for Rex. Device details: I2C Controller/Bus = 4 I2C Slave Address = 0x50 GPE = GPE0_DW1_03/GPP_E03 BUG=b:224325352 TEST=Verified in emulator that there is no regression Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: Ifa3a5b503a203e3900049f27a54025156e22a285 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66014 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Revert "mb/google/brya/var/kinox: Configure TDC current"Dtrain Hsu2022-07-221-26/+0
| | | | | | | | | | | | | | | | | | | | | This reverts commit 58f68fb0cb8e9824256a115d1ebdc840c281e987. Reason for revert: ODM thermal team request that change IA/GT TDC current back to 20A. BUG=b:237230877 TEST=Build and boot to Chrome OS Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: I6a5cfdc18afb6fe43a3d630e5fa3d77c19640fc2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65980 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Baieswara Reddy Sagili <baieswara.reddy.sagili@intel.corp-partner.google.com> Reviewed-by: Vinay Kumar <vinay.kumar@intel.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Reviewed-by: John Su <john_su@compal.corp-partner.google.com>
* mb/google/rex: Enable EC_GOOGLE_CHROMEEC_BOARDID KconfigTarun Tuli2022-07-221-0/+1
| | | | | | | | | | | | | | Enables the EC_GOOGLE_CHROMEEC_BOARDID feature so we can read board_id() on rex. TEST=Verified builds succeed and code is linked Change-Id: Id202019519fc4a05c80374bc97663e59fdca3d76 Signed-off-by: Tarun Tuli <taruntuli@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66018 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* mb/google/geralt: Add eMMC and SD card configurationsAndy-ld Lu2022-07-222-0/+5
| | | | | | | | | | | | | | Geralt reference design has both eMMC and SD card interfaces, so we configure both in mainboard_init() in ramstage. TEST=boot to kernel using emmc successfully. BUG=b:236331724 Signed-off-by: Andy-ld Lu <andy-ld.lu@mediatek.corp-partner.google.com> Change-Id: I200a065ab96584d824153480e594e19baae97f9c Reviewed-on: https://review.coreboot.org/c/coreboot/+/65976 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/geralt: Implement regulator interfaceHui Liu2022-07-222-0/+78
| | | | | | | | | | | | | Control regulator more easily with regulator interface. TEST=measure 3.0V in VMCH and VMC. BUG=b:236331724 Signed-off-by: Hui Liu <hui.liu@mediatek.corp-partner.google.com> Change-Id: I9727475774b3b9a8dcd49e5e60e133f9d745b407 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65875 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/brya/var/ghost: Split ghost4adl into 3 variantsJack Rosenthal2022-07-2211-5/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | We plan to make 3 firmwares which differ only by Kconfig options and can share a common variant directory. ghost4adl: Board with an ADL chip. ghost4es: Board near identical but has RPL-ES chip. ghost: Will have final RPL silicon. Since they will only differ by Kconfig options and Intel binary blobs, let's not duplicate the variant directory but instead share it in common. BUG=b:239456576 BRANCH=firmware-brya-14505.B TEST="make menuconfig", verify layout of board selection Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Change-Id: I94f2048bbe6675a807f8eba986a1ded0a4167733 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65956 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
* mb/google/brask/variants/moli: set customized_leds for RTL8111KRaihow Shi2022-07-221-1/+1
| | | | | | | | | | | | | | Follow the LED modification request in ADL_Moli_SC_MB_2022_0601.pdf and set the customized_leds to 0x0482 based on 7.4 Customizable LED Configuration in "REALTEK+RTL8111K-CG+SPEC+0116" for RTL8111K in moli. BUG=b:218985167 TEST=emerge-brask coreboot and check RTL8111K LED behaviour Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com> Change-Id: Ia154d15ecf14b32a4d589abf27b9573693339a8a Reviewed-on: https://review.coreboot.org/c/coreboot/+/65958 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/brya/var/brya0: add WFC definitions to fw_configNick Vaccaro2022-07-221-1/+5
| | | | | | | | | | | | | | | | | | | | Reserve bits 15 and 16 in the fw_config to be used to specify WFC population status. Possible values for field WFC bits include: option WFC_ABSENT 0 option_WFC_MIPI_OVTI5675 1 option WFC_MIPI_OVTI8856 2 BUG=b:239613517 BRANCH=firmware-brya-14505.B TEST='emerge-brya coreboot' and make sure it compiles successfully. Change-Id: I23bdaf7feaff2e6a4979c3da789ab877e6ac3af2 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65988 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/kahlee: Increase VRAM from 16 to 32 MiBMatt DeVillier (AMD)2022-07-226-6/+6
| | | | | | | | | | | | | | | | | | | | | | While adequate for ChromeOS, 16MiB VRAM is insufficient for current mainline Linux and Windows amdgpu drivers to operate properly. Under Linux, the driver fails to allocate a framebuffer and causes multiple kernel panics. Under Windows, the driver fails to load due to insufficient resources available. Revert the VRAM allocation to the previous amount of 32MiB. This change reverts commit 87dcd0061af4 ("mainboard/google/kahlee: Reduce VRAM to 16MB") Test: build/boot Linux 5.17.x on google/liara, verify framebuffer allocation succeeds and no kernel panic reported. Change-Id: I1967a203fed80456a20af00943eba21bc1c0577b Signed-off-by: Matt DeVillier (AMD) <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66022 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/brya/acpi: Poll more frequently in GPPLTim Wawrzynczak2022-07-221-2/+3
| | | | | | | | | | | | | | | | | | | The full dGPU power-on sequence, when executed from ACPI, is taking roughly 15ms or so, which puts it close to the maximum of 20ms required from the Nvidia spec. Changing the polling period to 100 us instead of 1 ms drastically reduces the time required for this sequence, now taking typically 7 ms or so. This gives a lot more margin during the power on sequence. BUG=b:238466724 TEST=Sequence verified by EE on a scope Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I3ba676c5fac983a0c1ad1d60c3863d06ed33fa27 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66020 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* herobrine: Create Zoglin variantShelley Chen2022-07-222-0/+6
| | | | | | | | | | | | | | | Zoglin is like Hoglin, but with a smaller flash size, which requires us to create a new variant. BUG=b:239851866 BRANCH=None TEST=Make sure BOARD_GOOGLE_ZOGLIN builds Change-Id: Id1401a052061dcfc1d1ee41b88ce4a11fd9f3d01 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66055 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* mb/google/brya/var/baseboard/skolas: set BOARD_ROMSIZE_KB_32768Nick Vaccaro2022-07-211-1/+2
| | | | | | | | | | | | | | | | | | | | Skolas baseboard needs to set BOARD_ROMSIZE_KB_32768, so this change sets it. BUG=b:239628052 BRANCH=firmware-brya-14505.B TEST="emerge-brya coreboot" and verify that the following configs are set as: CONFIG_BOARD_ROMSIZE_KB_32768=y CONFIG_COREBOOT_ROMSIZE_KB_32768=y CONFIG_COREBOOT_ROMSIZE_KB=32768 CONFIG_ROM_SIZE=0x02000000 Change-Id: I0846b8e69c8b65e010eef9a8f4a88606197cd0c6 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65854 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google: Use boolean type for "enable" argument for regulatorRex-BC Chen2022-07-212-11/+11
| | | | | | | | | | | | | | | Because 0 and 1 are the only possible values, 1. Change input argument "enable" of mainboard_enable_regulator to bool. 2. Change return value of mainboard_regulator_is_enabled() to bool. TEST=build pass BUG=b:233720142 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: Iae09c5fedf8f7394bfbb677e5aee37ed061304fd Reviewed-on: https://review.coreboot.org/c/coreboot/+/65997 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google: Replace some strings in regulator.cRex-BC Chen2022-07-215-13/+10
| | | | | | | | | | | | | | | | From comments of CB:65875, we replace *_vol to *_voltage. s/mainboard_set_regulator_vol/mainboard_set_regulator_voltage/ s/mainboard_get_regulator_vol/mainboard_get_regulator_voltage/ TEST=build pass BUG=b:233720142 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: Iadf0408e8914d6e32915464f93979978c4634eaf Reviewed-on: https://review.coreboot.org/c/coreboot/+/65994 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* mb/google/geralt: Initialize PMICs in romstageBo-Chen Chen2022-07-211-1/+6
| | | | | | | | | | | | TEST=build pass BUG=b:233720142 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I71cc69c74dd618f441140790af351095ead3f6f9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65759 Reviewed-by: Yidi Lin <yidilin@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mg/google/corsola: Enable TI50_FIRMWARE_VERSION_NOT_SUPPORTEDYu-Ping Wu2022-07-211-0/+2
| | | | | | | | | | | | | | | | | | | | | Ti50 hasn't implemented version reading yet. To avoid the confusing error message Did not recognize Cr50 version format enable TI50_FIRMWARE_VERSION_NOT_SUPPORTED to make clear that this feature is not supported. BUG=b:234533588 TEST=emerge-corsola coreboot BRANCH=none Change-Id: I18dd4b5bc05c2af06627275968e49aba048ba05e Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65839 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@chromium.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
* mb/google/rex: Pulling GPIO programming early to get debug msgSubrata Banik2022-07-211-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch moves the early GPIO programming from `bootblock_mainboard_init` to `bootblock_mainboard_early_init`. It will help to get the early debug prints as below. TEST=Without this CL the initial report platform information was missing as below: [DEBUG]  VBOOT: Loading verstage. [DEBUG]  FMAP: Found "FLASH" version 1.1 at 0x1c04000. [DEBUG]  FMAP: base = 0xfe000000 size = 0x2000000 #areas = 33 [DEBUG]  FMAP: area COREBOOT found @ 1c09000 (4157440 bytes) [INFO ]  CBFS: mcache @0xfef84a00 built for 18 files, used 0x414 of 0x2000 bytes [INFO ]  CBFS: Found 'fallback/verstage' @0x24d240 size 0x133d0 in mcache @0xfef84d50 With this CL the complete bootblock serial msg is coming. [NOTE ]  coreboot-.mtl.po.ww29.5 Fri Jul 15 21:47:36 UTC 2022 bootblock starting (log level: 8)... [DEBUG]  CPU: Genuine Intel(R) 0000 @ [DEBUG]  CPU: ID a06a0, MeteorLake A0, ucode: f0270108 [DEBUG]  CPU: AES supported, TXT supported, VT supported [DEBUG]  MCH: device id 7d14 (rev 00) is MeteorLake P [DEBUG]  PCH: device id 7e01 (rev 00) is MeteorLake SOC [DEBUG]  IGD: device id 7d55 (rev 00) is MeteorLake-P GT2 [DEBUG]  VBOOT: Loading verstage. [DEBUG]  FMAP: Found "FLASH" version 1.1 at 0x1c04000. [DEBUG]  FMAP: base = 0xfe000000 size = 0x2000000 #areas = 33 [DEBUG]  FMAP: area COREBOOT found @ 1c09000 (4157440 bytes) [INFO ]  CBFS: mcache @0xfef84a00 built for 18 files, used 0x414 of 0x2000 bytes [INFO ]  CBFS: Found 'fallback/verstage' @0x24d240 size 0x133d0 in mcache @0xfef84d50 Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I3e092cd749359e54fe518de21671275af4b03062 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65986 Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
* mainboard/google/guybrush: Update Wake-On-LAN functionalityRobert Zieba2022-07-202-3/+5
| | | | | | | | | | | | | | | | The generic wifi driver currently contains a lot of intel specific functionality that results in it not working properly on AMD platforms. This commit updates the base device tree to use the generic PCIe driver instead. BUG=none TEST=Ran on nipperkin device, dumped SSDT and checked wakeup sources Change-Id: Iafbc68c1ae33ccc260889f0b39fc5fe8a59d7aca Signed-off-by: Robert Zieba <robertzieba@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65990 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mainboard/google/skyrim/baseboard: Enable Wake-On-LAN functionalityRobert Zieba2022-07-202-3/+5
| | | | | | | | | | | | | | | | The generic wifi driver currently contains a lot of intel-specific functionality that interferes with enabling wake-on-lan. This commit changes the device tree to use the generic PCIe driver which better supports this functionality. BUG=b:237682766 TEST=Booted on skyrim device and verified that wake on LAN works Signed-off-by: Robert Zieba <robertzieba@google.com> Change-Id: I5d15d33fd0a152eb3bf2bfe78e802483a701e750 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65800 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/brya/var/agah: Adjust I2C speedTony Huang2022-07-201-0/+9
| | | | | | | | | | | | | Adjust I2C speed for codec, TPM, touchpad. BUG=b:237691531 TEST=Built and verified adjusted I2C speed < 400KHz Change-Id: I203d137d61019235ddf38ef74607427db2a7e975 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65957 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* arch/arm64,arm: Prepare for !SEPARATE_ROMSTAGEArthur Heymans2022-07-207-16/+68
| | | | | | | | | | Prepare platforms for linking romstage code in the bootblock. Change-Id: Ic20799b4d6e3f62cd05791a2bd275000a12cc83c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63420 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* mb/prodrive/atlas: Swtich from EC UART to LPSS UARTLean Sheng Tan2022-07-201-1/+1
| | | | | | | | | | Switch x86 uart output from EC to LPSS. Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: I2756d139a72185ba6a5c6d1079d770ce33afdf71 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65985 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* google/herobrine: Add Evoker variantSheng-Liang Pan2022-07-202-0/+5
| | | | | | | | | | | | | BUG=b:238571507 BRANCH=None TEST=emerge-herobrine coreboot Change-Id: Ie596e5c4b72de84d16571043db4291bbd0825c78 Signed-off-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65947 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Bob Moragues <moragues@chromium.org>
* soc/amd/sabrina, mb/google/skyrim: Call espi_switch_to_spi1_padsKarthikeyan Ramasubramanian2022-07-201-0/+3
| | | | | | | | | | | | | | | | | Skyrim uses second SPI pads for ESPI. Switch to it initialize ESPI in verstage. BUG=b:217414563 TEST=Build Skyrim BIOS image. Ensure that ESPI init is successful in PSP verstage. Change-Id: I6e3462e95c50d256b6c159ae1d854dd69a538bb0 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65862 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
* mb/google/skyrim: Regenerate SPD part IDsKarthikeyan Ramasubramanian2022-07-203-34/+2
| | | | | | | | | | | | | | | | | Now that the speed is limited to 5500 Mbps for all memory parts used in Skyrim, regenerate the part IDs. Remove any custom generated part IDs and the associated SPDs. BUG=b:238074863 TEST=Build and boot to OS in Skyrim. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I6d8326208580a971e781887a7ec83355bb085c7f Reviewed-on: https://review.coreboot.org/c/coreboot/+/65709 Reviewed-by: Robert Zieba <robertzieba@google.com> Reviewed-by: Jon Murphy <jpmurphy@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/brya/acpi: Add support for D Notify event from the Chrome ECTim Wawrzynczak2022-07-203-0/+52
| | | | | | | | | | | | | | | | | | | | | The agah EC code includes a driver to keep track of the current D Notify level that the GPU should be at. When it changes, it will send a host event to the ACPI FW, which will then pass that Notify on to the kernel driver. This patch adds support for that feature, which is described in the Nvidia Software Design Guide. BUG=b:229405562 TEST=add Printf() calls to the ACPI, and work through the various scenarios on the EC that will cause D Notify levels to change; this will cause the Printfs() to show up in the kernel log. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I5cd8bd7d177ea10a165613ed0726a6d6fd86c226 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65486 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Robert Zieba <robertzieba@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* mb/google/nissa/var/craask: Change craask to use 16M SPI flashTyler Wang2022-07-191-1/+0
| | | | | | | | | | | | BUG=b:236175568 TEST=Build and test on MB, system can boot to OS. Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Change-Id: I779355dcc69eed08703bcb8bb943dcfeeb1fdea1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65945 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
* mb/google/brya/var/skolas: fix comment for I2C connectionsEran Mitrani2022-07-191-3/+3
| | | | | | | | | | | | | | For brya/skolas, I2C1 is cr50, and I2C3 is Touchscreen BUG=None BRANCH=firmware-brya-14505.B TEST=None Signed-off-by: Eran Mitrani <mitrani@google.com> Change-Id: I4058e0f33b2bb6227a0af92941ed4e2eb56ba542 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65792 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
* mb/google/dedede/var/beadrix: Update memory part and generate DRAM IDTeddy Shih2022-07-193-1/+3
| | | | | | | | | | | | | | | | | | This change adds memory part used by variant beadrix to mem_part_used.txt and generates DRAM ID allocated to the part. BUG=b:236750116 BRANCH=None TEST=Run part_id_gen to generate SPD id Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com> Change-Id: I3f29609d9fe5143b0bfe4b78279d0780cd7e5097 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65306 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Super Ni <super.ni@intel.corp-partner.google.com> Reviewed-by: Henry Sun <henrysun@google.com> Reviewed-by: Ivan Chen <yulunchen@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* mb/google/rex: Refactor baseboard/variant gpio pad configurationSubrata Banik2022-07-193-10/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch tries to simplify the baseboard/variant GPIO programming starting with Google/Rex. The idea is to let each variant maintain its own complete GPIO PAD configuration table instead of having a back-and-forth call between baseboard and variants. With this patch coreboot performing GPIO programming is now much simpler where the common code block calls into respective variants and gets the gpio table prior to the pad configuration. BUG=b:238165977 (Simplify baseboard/variant GPIO programming starting with Google/Rex) TEST=Able to build and boot the Google/Rex board. AP firmware log with DEBUG_GPIO kconfig lists the early GPIOs being configured from the `rex0` variant. gpio_padcfg [0xd3, 08] DW0 [0x44000300 : 0x40000400 : 0x40000400] gpio_padcfg [0xd3, 08] DW1 [0x00000020 : 0x00000000 : 0x00000020] gpio_padcfg [0xd3, 08] DW2 [0x00000000 : 0x00000000 : 0x00000000] gpio_padcfg [0xd3, 08] DW3 [0x00000000 : 0x00000000 : 0x00000000] gpio_padcfg [0xd3, 09] DW0 [0x44000300 : 0x40000400 : 0x40000400] gpio_padcfg [0xd3, 09] DW1 [0x00000021 : 0x00000000 : 0x00000021] gpio_padcfg [0xd3, 09] DW2 [0x00000000 : 0x00000000 : 0x00000000] gpio_padcfg [0xd3, 09] DW3 [0x00000000 : 0x00000000 : 0x00000000] Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I8ec5c6991ec90a3884464e7f15f33327bfe4839a Reviewed-on: https://review.coreboot.org/c/coreboot/+/65674 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* mb/google/brask/variants/moli: correct USB3 port2 tx_de_empRaihow Shi2022-07-191-0/+6
| | | | | | | | | | | | | | | Set USB3 port2 tx_de_emp 0x2B by "11th Gen Intel Core Processors for IoT Platforms EDS Addendum_rev1.6" then fix the USB3 port2 Gen2 RX failed. BUG=b:236661824 TEST=emerge-brask coreboot and check USB3 port2 RX pass Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com> Change-Id: I7a5add20f055a8d871c6b4f33734fb8a397cba76 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65848 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/sabrina/fsp_m_params: add UPD pointer parameter to mb callbackFelix Held2022-07-191-1/+1
| | | | | | | | | | | This allows the mainboard code to change FSP-M parameters depending on parameters that are only known at run time and not at build time. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I3e0e196a5d861acd7635c59db44ecf1970b73ce2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65855 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-13 14:56:54 +0000