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* mb/prodrive/atlas: Add data.vbt for 4 DPs supportLean Sheng Tan2022-06-052-2/+3
| | | | | | | | Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: Ia5b6c5c72a1eafe1118e92e4579decb4f4abc9e5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64943 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* mb/google/octopus: Demote NHLT log messages from error to infoMatt DeVillier2022-06-051-5/+5
| | | | | | | | | Change-Id: Ib2d0c6a23b66e6e61cc8ea09a443e19a4b37c66d Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63287 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
* mb/prodrive/atlas: Update pcie config for i225Lean Sheng Tan2022-06-051-3/+4
| | | | | | | | | | Enable clk 1, LTR & AER for PCIe-to-i225 bridge. Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: I9593f5d0b70f3d231fd1a8f4758b924645392d63 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64902 Reviewed-by: Christian Walter <christian.walter@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/prodrive/atlas: Fix FSP debug boot hangLean Sheng Tan2022-06-051-0/+1
| | | | | | | | | | | | | | | When device tcss_xhci is disabled, boot hang occurs at FSP-S TcssInit(): "IomReadyCheck Failed!" Enabling this device fixes the issue. Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: Ie001bd56b403d511c397737fbc214ed64956910d Reviewed-on: https://review.coreboot.org/c/coreboot/+/64901 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/prodrive/atlas: Add display configs for 4 DisplayPortsLean Sheng Tan2022-06-051-0/+8
| | | | | | | | Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: Iea5312055305bc3354755607a7bfafa7980c6d21 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64900 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
* mb/google/brya/var/kinox: Update gpio configurationDtrain Hsu2022-06-051-4/+4
| | | | | | | | | | | | | | | | | Follow GPIO_Table_0527.xlsx to update gpio configuration. - Set GPP_A15 to NC. - Set GPP_A20 to TCP_DP1_HPD (native function1). BUG=b:225384873 TEST=Build and boot to Chrome OS. Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: I1c7a211c3bef1f1fe4f94345186c33363a90e11f Reviewed-on: https://review.coreboot.org/c/coreboot/+/64786 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ricky Chang <rickytlchang@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
* mb/google/brya/var/mithrax: Update DPTF parameters for MithraxJohn Su2022-06-031-5/+5
| | | | | | | | | | | | | | | | | Follow thermal table from thermal team. Chang list: 1. Update TEMP_PCT of Active Policy for TSR1. BUG=b:230829301 TEST=emerge-brya coreboot Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Change-Id: I2a3fbdbe0dbb00597d5785c90c6e4d6ace54f13c Reviewed-on: https://review.coreboot.org/c/coreboot/+/64856 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* mb/google/brya/variants/nereid: Add DPTF passive and critical policies for ↵Vidya Gopalakrishnan2022-06-031-0/+52
| | | | | | | | | | | | | | | | | | | Nereid BUG=b:233030505 BRANCH=None TEST=Build FW and test on Nereid board. Verified thermal throttling successfully when participant reaches temp threshold as per Passive Policy. Also, verified system shutdown when Temperature of participants are reaching threshold as per Critical policy. Signed-off-by: Vidya Gopalakrishnan <vidya.gopalakrishnan@intel.com> Change-Id: I195f4b507ee57948751f0119735d8350dfce984b Reviewed-on: https://review.coreboot.org/c/coreboot/+/64468 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Jesper Lin <jesper_lin@wistron.corp-partner.google.com>
* mb/google/nissa/craask: Configure the external V1p05/Vnn/VnnSxTyler Wang2022-06-031-0/+15
| | | | | | | | | | | | | | | | | | | | This patch configures external V1p05/Vnn/VnnSx rails for Craask to achieve the better power savings. * Enable the external V1p05, Vnn, VnnSx rails in S0i1, S0i2, S0i3, S3, S4, S5 , S0 states. * Set the supported voltage states. * Set the voltage for v1p05 and vnn. * Set the ICC max for v1p05 and vnn. BUG=b:233717182 TEST=emerge-nissa coreboot Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Change-Id: I95d24c0836f3ee02006868341ccc72d762c155d3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64632 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
* mb/google/nissa/var/nivviks: Enable ISH when UFS is presentReka Norman2022-06-031-0/+3
| | | | | | | | | | | | | | | | | | | | | In order to enable the UFS controller (PCI device 12.7), the PCI specification says that the device at function 0 in the same slot must also be enabled, which is the ISH. Therefore, enable ISH when UFS is present. For more context on why this is necessary, see CB:62662 which enabled UFS and ISH for adlrvp_n. BUG=b:234136500 TEST=Build test. Will test that UFS works once we have hardware. Signed-off-by: Reka Norman <rekanorman@chromium.org> Change-Id: Ib60d44322cfbd8f82c33ecac7598881dfb1d0c3c Reviewed-on: https://review.coreboot.org/c/coreboot/+/64845 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Daniil Lunev <dlunev@chromium.org>
* mb/purism/librem_mini: Hide Linux GPIO LED from WindowsMatt DeVillier2022-06-021-0/+1
| | | | | | | | | | | | | | | | | Hide the Linux gpio-led ACPI device from Windows by setting the device status (_STA) to 0xB (enabled, hidden) so Windows doesn't show an unknown device/missing drivers in Device Manger. Linux doesn't care about the _STA value. Test: build/boot Windows (10/11) and Linux (PureOS 10) on a Librem Mini v2, verify LED works under Linux, is ignored under Windows Change-Id: If3ee0db685a2f7dab505602afa98c3c2d5adf5d3 Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64710 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
* mb/google/brya: Add new skolas baseboardNick Vaccaro2022-06-0220-1/+2176
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit adds the skolas baseboard, which is basically the brya baseboard, but using an Intel Raptor Lake-P SoC instead of an Alder Lake SoC. This commit also adds the skolas baseboard variant skolas4es. Since this baseboard is identical to the brya baseboard with the exception of the SoC used, the new baseboard and the new baseboard's first variant will be a copy of the current brya baseboard and brya0 variant. For now, the skolas baseboard and skolas4es variant will continue to use ADL-P. This allows for two benefits: 1. software to be proven out on existing hardware prior to RPL SoC support landing, and 2. allows us not to have to wait for RPL SoC changes prior to getting the mainboard changes in place Once the RPL SoC code has merged, I will update the skolas baseboard and skolas4es variant to use RPL instead of ADL. BUG=b:229134437 TEST=util/abuild/abuild -p none -t google/brya -x -a -c max Change-Id: Iec100306dca2320eaf2432797f3acc31db2543d3 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63891 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
* mb/google/brya/variants/osiris: Remove KB_MT from overridetreeDavid Wu2022-06-021-4/+0
| | | | | | | | | | | | | | All Osiris SKUs use the new RGB gaming keyboard, so don't need the fw_config to decide keyboard matrix. BUG=b:220800586 TEST=FW_NAME="osiris" emerge-brya coreboot chromeos-bootimage Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I19211c345de0b315d65ec64efc70826e81315810 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64813 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
* mb/intel/adlrvp: Enable DPTF for ADL-N RVPVidya Gopalakrishnan2022-06-021-0/+101
| | | | | | | | | | | | | | | BUG=None BRANCH=None TEST=Build FW and test on adln_rvp board Verified thermal throttling successfully when participant reaches temp threshold as per Passive Policy. Verified fan control successfully when participant reaches temp threshold as per Active Policy. Also, verified system shutdown when Temperature of participants are reaching threshold as per Critical policy. Signed-off-by: Vidya Gopalakrishnan <vidya.gopalakrishnan@intel.com> Change-Id: Icafacfca6a026ec3b42906790831f11fd2f1b085 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64570 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
* mb/intel/adlrvp: Set power limits dynamically for ADL-N SKUsVidya Gopalakrishnan2022-06-021-0/+4
| | | | | | | | | | | | | | | | This patch adds support for the ADL-N SKUs based on the PCH ID. Document reference: 645548 (ADL-N EDS Volume 1). BUG=None BRANCH=None TEST=Build FW and test on adln_rvp board Signed-off-by: Vidya Gopalakrishnan <vidya.gopalakrishnan@intel.com> Change-Id: Ie49398b8a7de8d8cff3536eae6a5e893980f9c26 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64569 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
* mb/google/nissa/var/craask: Disable PCIe WLAN pinsTyler Wang2022-06-021-0/+4
| | | | | | | | | | | | | | Craask uses CNVi WLAN, so disable the PCIe-related GPIOs. BUG=b:229040345 Test=emerge-nissa coreboot Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Change-Id: I7bcf041503dcee448758dac46b1c9711d0b02ba3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64461 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
* mb/lenovo/w541/Kconfig: sort alphabeticallyPeter Lemenkov2022-06-011-1/+1
| | | | | | | | Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Change-Id: I9cefa29738b42dd08cb00489ad6e8644e3fc405e Reviewed-on: https://review.coreboot.org/c/coreboot/+/63997 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* mb/lenovo/t440p/Kconfig: remove duplicates and sort alphabeticallyPeter Lemenkov2022-06-011-3/+1
| | | | | | | | Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Change-Id: I47fded50377ab624e4bceb320a5e069a7f36c2fb Reviewed-on: https://review.coreboot.org/c/coreboot/+/63996 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* mb/lenovo/t440p/hda_verb: WhitespacePeter Lemenkov2022-06-011-1/+1
| | | | | | | | Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Change-Id: I92c167bf95e605e098324b9e80cfaab8f589dcab Reviewed-on: https://review.coreboot.org/c/coreboot/+/63995 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* mb/lenovo/w541/hda_verb: WhitespacePeter Lemenkov2022-06-011-1/+1
| | | | | | | | Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Change-Id: I284a5e39ca4b0032ed0c8e3a92c095db319d1691 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63994 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* mb/lenovo/w541/dsdt.asl: Remove redundant commentFelix Singer2022-06-011-1/+0
| | | | | | | | | Signed-off-by: Felix Singer <felixsinger@posteo.net> Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Change-Id: Ide938a40ed1f6869ee248ed46f6bf29f95649490 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63993 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* mb/lenovo/t440p/cmos: Remove unused optionsPeter Lemenkov2022-06-011-4/+0
| | | | | | | | Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Change-Id: I9bf95ed74468e283bab79a5f25aee758d37d926a Reviewed-on: https://review.coreboot.org/c/coreboot/+/63992 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* mb/google/brya/var/agah: Enable EC keyboard backlightTony Huang2022-06-011-0/+3
| | | | | | | | | | | BUG=b:210970640 TEST=emerge-draco coreboot chromeos-bootimage Change-Id: I90d9f2e298e54832bc077eae1c8be0e39c151d90 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64808 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* mb/google/brya/var/kinox: Set memory SMBus addresses based on board revDtrain Hsu2022-06-011-2/+10
| | | | | | | | | | | | | | | Starting with id 2, boards switched the memory SMBus slave address, and use 0x50, 0x52. BUG=b:233975373 TEST=Build and boot to Chrome OS Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: I5e683ffdbc0727259ee796610cd97a6e378bf335 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64810 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ricky Chang <rickytlchang@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/corsola: Add new board 'steelix'Zanxi Chen2022-06-012-0/+5
| | | | | | | | | | | | | | Add a new kingler follower 'steelix'. BUG=b:232195941 TEST=make # select steelix Change-Id: Idd2ed1404cde72ecdb6cc3a262e793a6272aa871 Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64789 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: wen zhang <zhangwen6@huaqin.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* mb/emulation/qemu-q35: Support PARALLEL_MP with SMM_ASEGArthur Heymans2022-06-013-3/+16
| | | | | | | | | | | Tested with SMI_DEBUG: SMM prints things on the console. Change-Id: I7db55aaabd16a6ef585c4802218790bf04650b13 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61494 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* mb/google/brya/var/craask: Add ACPI _PLD custom valuesWon Chung2022-06-011-8/+16
| | | | | | | | | | | | | | | | | | | | | | | | This patch uses ACPI _PLD macros to add custom values for USB ports. +----------------+ | | | Screen | | | +----------------+ C0 | | C1 A0 | MLB DB | A1 | | +----------------+ BUG=b:232256907 TEST=emerge-brya coreboot Signed-off-by: Won Chung <wonchung@google.com> Change-Id: Ia288937ef3a4229088b60d87d31ea88057377a71 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64731 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
* mb/google/brya/var/nivviks: Add ACPI _PLD custom valuesWon Chung2022-06-011-8/+16
| | | | | | | | | | | | | | | | | | | | | | | | This patch uses ACPI _PLD macros to add custom values for USB ports. +----------------+ | | | Screen | | | +----------------+ C0 | | C1 A0 | MLB DB | A1 | | +----------------+ BUG=b:232256907 TEST=emerge-brya coreboot Signed-off-by: Won Chung <wonchung@google.com> Change-Id: If2a77c0239646759e0192b72ba1991d334dd15aa Reviewed-on: https://review.coreboot.org/c/coreboot/+/64730 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
* mb/google/brya/var/nereid: Add ACPI _PLD custom valuesWon Chung2022-06-011-8/+16
| | | | | | | | | | | | | | | | | | | | | | | | This patch uses ACPI _PLD macros to add custom values for USB ports. +----------------+ | | | Screen | | | +----------------+ C0 | | C1 A0 | MLB DB | A1 | | +----------------+ BUG=b:232256907 TEST=emerge-brya coreboot Signed-off-by: Won Chung <wonchung@google.com> Change-Id: I47b069377046652ba4d278733a15bbca98bdb739 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64729 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
* mb/google/brya/var/kinox: Add delay time for BH799BB rtd3Dtrain Hsu2022-06-011-0/+2
| | | | | | | | | | | | | | | | | | This CL adds the delay time into the RTD3 sequence, which will turn off the eMMC controller (a true D3cold state) during the RTD3 sequence. We checked power on sequence requires enable pin prior to reset pin delay of 50ms and add delay of 20ms to meet the sequence on various eMMC SKUs. Based on BH799BB_Preliminary_DS_R079_20201124.pdf in chapter 7.2. BUG=b:232327947 TEST=Build and suspend_stress_test -c 2500 pass Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: I42cde5336f73a446cf5157e78f955fef8d70ae7e Reviewed-on: https://review.coreboot.org/c/coreboot/+/64686 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/dedede/beadrix: Add fw_config probe for ALC5682-VD & VSTeddy Shih2022-06-011-1/+25
| | | | | | | | | | | | | | | | | | | | | | ALC5682-VD/ALC5682I-VS load different kernel driver by different hid name. Update hid name depending on the AUDIO_CODEC_SOURCE field of fw_config. Define FW_CONFIG bits 41 - 43 (SSFC bits 9 - 11) for codec selection. ALC5682-VD: _HID = "10EC5682" ALC5682I-VS: _HID = "RTL5682" BRANCH=dedede BUG=b:226910787,b:232057623 TEST=on beadrix, verified by FW_NAME=beadrix emerge-dedede coreboot. Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com> Change-Id: I059b750743ab3b29d17c50d0d4301fbae4873acc Reviewed-on: https://review.coreboot.org/c/coreboot/+/64025 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Super Ni <super.ni@intel.corp-partner.google.com> Reviewed-by: Ivan Chen <yulunchen@google.com>
* sc7280: Improve performance by removing delays in cpucp initSudheer Kumar Amrabadi2022-06-011-0/+2
| | | | | | | | | | | | | | As cpucp prepare takes 300 msec moving to before ramstage BUG=b:218406702 TEST=Validated on qualcomm sc7280 development board observed total timestamp as 1.73 sec from 1.97 sec Change-Id: I1a727514810a505cd1005ae7f52e5215e404b3bb Signed-off-by: Sudheer Kumar Amrabadi <quic_samrabad@quicinc.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63085 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
* mb/starlabs/lite/glk: Don't configure GPIO's 147 through 156Sean Rhodes2022-05-311-24/+1
| | | | | | | | | | These are configured by the TXE, so they do not need to be configured. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ia1bf4e32aa156a0e1a74df2f62eb31cdadb376a9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64454 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
* mb/starlabs/lite/glk: Simplify GPIO macrosSean Rhodes2022-05-311-111/+53
| | | | | | | | | | Use shorter macros to configure GPIOs. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I91961658dca0902080576134e63e6d8a7c78d711 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64453 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
* mb/starlabs/lite/glk: Disconnect unused GPIOsSean Rhodes2022-05-311-78/+61
| | | | | | | | | | | | Disconnect GPIOs that are unused or not connected. Also, update comments that are vague or have errors. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ic83797b8a8e05eed99db0356f360a329f6fbf347 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64452 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
* mb/google/nissa/var/craask: Generate SPD ID for supported memory partTyler Wang2022-05-313-2/+5
| | | | | | | | | | | | | | | | Add supported memory parts in mem_parts_used.txt, and generate SPD id for this part. K3LKLKL0EM-MGCN BUG=b:229938024 TEST=emerge-nissa coreboot Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Change-Id: Ie022dd95929549ddd403d4c1d1c52174fd3fd721 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64678 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
* mb/google/brya/var/kinox: Select VBT based on FW_CONFIGDtrain Hsu2022-05-313-0/+26
| | | | | | | | | | | | | Select vbt bin files based on DB_DISPLAY field of FW_CONFIG. BUG=b:233690293 TEST=emerge-brask coreboot Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: Idb92be66927259732bfd27e4db2c9f242da7d200 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63918 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao@google.com>
* mb/google/brya/var/taniks: Modify DPA value to 100 for taniksLeo Chou2022-05-311-0/+1
| | | | | | | | | | | | | | In order to meet the OEM's acoustic specifications, the pre-wake randomization time (DPA) is set to 100. BUG=b:228410327 TEST=build FW and checked DPA value by fsp log. Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com> Change-Id: Idaf3f931a2c0f2373445948e5f53a82328ec7ba2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64372 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/nissa: Add and default to 16 MB layoutKangheui Won2022-05-314-2/+59
| | | | | | | | | | | | | | Future nissa devices will mostly use 16MB SPI flash. Add 16MB layout and make it default for nissa. BUG=b:202783191 TEST=build nissa and brya firmware, check they're still 32MB Signed-off-by: Kangheui Won <khwon@chromium.org> Change-Id: I04ae46d62d3e018610ca2533c186dda980bd67bc Reviewed-on: https://review.coreboot.org/c/coreboot/+/64716 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
* mb/lenovo: Rename t440p to haswellFelix Singer2022-05-3122-1/+1
| | | | | | | | | | | | In preparation to follow-up commits, rename the mainboard folder from t440p to haswell, which will have more variants later. Change-Id: I4a9d68d54d5f0821bbf85faaa620855d456c97f3 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63511 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
* mb/starlabs/lite/{glk/glkr}: Configure prt0_gpioSean Rhodes2022-05-312-0/+4
| | | | | | | | | | | PERST_0 is not used, so set this to GPIO_PRT0_UDEF (undefined) to ensure that an undefined address is not added to GNVS. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Iac9b116b2fa28824a89db28911188364dc9a1a53 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64446 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
* mb/asrock/h81m-hds: Reorder selects alphabeticallyFelix Singer2022-05-301-1/+1
| | | | | | | | Change-Id: I18398efefcb4171496c39462c23514ad61659213 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64775 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* mb/asrock/b85m_pro4: Reorder selects alphabeticallyFelix Singer2022-05-301-1/+1
| | | | | | | | Change-Id: Ic22fcbb7923ecac4c70147ae642ac28fac3e6e6d Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* mb/lenovo/t530: Reorder selects alphabeticallyFelix Singer2022-05-301-18/+17
| | | | | | | | Change-Id: I772ef94c860a26214bdae367d9863a56d5df9469 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64757 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
* mb/lenovo/t530: Select board-specific options per boardFelix Singer2022-05-301-1/+1
| | | | | | | | | | | Move board-specific selects out of common configuration and add them to each board where necessary. Change-Id: I9940ad2e963458e4bc50c2a2957bb72cbd4109be Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64756 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
* mb/lenovo/t530: Move selects from Kconfig.name to KconfigFelix Singer2022-05-302-2/+6
| | | | | | | | | | | Move selects from Kconfig.name to Kconfig so that the configuration is at one place and not distributed over two files. Change-Id: I8ef0e67a8f26b98acea777afb26ed221bfa90153 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64755 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
* mb/google/brya/var/vell: Move SPK0/SPK1 to I2C7eddylu@ami.corp-partner.google.com2022-05-301-21/+38
| | | | | | | | | | | | | | | | To support speaker AMP CS35L53-CWZR'S I2C needs to split to two I2C ports BUG=b:207333035 BRANCH=none TEST=built and verified speaker Signed-off-by: Eddy Lu <eddylu@ami.corp-partner.google.com> Change-Id: I8095abc4fc3233b21b818a508c84cd59b39fc1d6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63756 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com> Reviewed-by: Shon Wang <shon.wang@quanta.corp-partner.google.com>
* Revert "mb/google/brya/var/vell: Remove unused i2c7 settings"Shon Wang2022-05-302-5/+15
| | | | | | | | | | | | | | | | | This reverts commit bd9cec8ae5755e898d107fd061fc2e2f983552b9. Reason for revert: Enable i2c7 for amp changing to 2 channel because vell setting amp on i2c0 and i2c7 on next phase BUG=b:229334701 TEST=emerge-brya coreboot chromeos-bootimage && $powerd_dbus_suspend && checks EC log and ensures the DUT could enter s0ix. Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com> Change-Id: I5988cd9926b2c9ced1d111774abaa897bef91537 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64627 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/brya/var/kinox: Correct the target of DPTF active policyDtrain Hsu2022-05-301-4/+4
| | | | | | | | | | | | | | | Kinox has four temperature sensors. Modify the target of DPTF active policy to map correct temperature sensor. BUG=b:231380286 TEST=Boot to Chrome OS and doesn't see "DPTF: Invalid sensor ID" from ec comsole. Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: Icb5c285a6f483e2a1b6510a962ff7f7f6e9a79e3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64722 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/biostar/a68n_5200: Use pci_or_config8()Elyes Haouas2022-05-291-10/+4
| | | | | | | | Change-Id: I4be0a4ad980b4167eaaafc22399b680abf011553 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63971 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-01 12:58:45 +0000