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* google/kahlee: Fix GPIO ASLMarc Jones2017-09-272-6/+9
| | | | | | | | | | | | | | | | Use a single define and set the CROS GPIO ASL device to match the Stoney Ridge GPIO HID. Update the GPIO number to 142. Also, add a DDN field in the GPIO ASL. This addresses the TEST indicated below. BUG=b:65597554 BRANCH=none TEST=grep ^ /sys/devices/platform/chromeos_acpi/GPIO.*/* reports AMD0030. Change-Id: I1d6c42c6c9a0eef25e0e99aed6d838c767f5e01f Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/21614 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* asus/p2b-f: Move to EARLY_CBMEM_INITKeith Hui2017-09-261-1/+0
| | | | | | | | | | | It shares the same northbridge, cpu, romstage with asus/p2b-ls, which is already on EARLY_CBMEM_INIT as of commit e14d7de. Change-Id: I8e7c468f0363a5cb9885020bc116e5ae3480ec17 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/21647 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
* asus/p2b-d[s]: Move to EARLY_CBMEM_INITKeith Hui2017-09-263-2/+2
| | | | | | | | | | | Boot tested on p2b-ds. Migrate p2b-d as well because they share the same mainboard romstage. Change-Id: I3e4b98cc6191d557325fc5da97744902996673af Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/21646 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
* mainboard/google/fizz: Enable EC-EFS supportDaisuke Nojiri2017-09-261-0/+1
| | | | | | | | | | | | BUG=b:65028930 BRANCH=none TEST=emerge-fizz coreboot. Verify Depthcharge recognize VBSD_EC_EFS. Change-Id: Ie18536982e172a45703600eec6e183c1e7c12746 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://review.coreboot.org/21640 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mainboard/google/fizz: Enable cros_ec_keyb deviceKevin Cheng2017-09-261-0/+3
| | | | | | | | | | | | | | | | | This is required to transmit button information from EC to kernel. BUG=b:65980005 BRANCH=None TEST=Verified using evtest that kernel is able to get button press/release information from EC. Change-Id: I3cd524aec47ca988d6044cb089e7aa7636e64ab2 Signed-off-by: Kevin Cheng <kevin.cheng@intel.com> Reviewed-on: https://review.coreboot.org/21633 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
* Use stopwatch_wait_until_expired where applicableJonathan Neuschäfer2017-09-262-4/+2
| | | | | | | | Change-Id: I4d6c6810b91294a7e401a4a1a446218c04c98e55 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/21590 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
* mainboard/winnet/g170: drop the redundant vendor nameLubomir Rintel2017-09-261-1/+1
| | | | | | | | | | | "WinNET WinNET G170" doesn't look too cool :( Change-Id: Iae0a8725645b9d6321b64ccbad10633e0049d477 Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Reviewed-on: https://review.coreboot.org/21612 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
* mainboard/winnet/g170: disable use of upper memory for SeaBIOSLubomir Rintel2017-09-262-0/+8
| | | | | | | | | | | | | | | | | | Otherwise the USB init gets unhappy: |3df52000| EHCI init on dev 00:10.4 (regs=0xfd010010) |3df3d000| WARNING - Timeout at ehci_wait_td:515! |3df3d000| ehci pipe=0x3df52880 cur=00000000 tok=00000000 next=3df3ddc0 td=0x3df3ddc0 status=80e80 |3df3e000| WARNING - Timeout at ehci_wait_td:515! |3df3e000| ehci pipe=0x3df52a80 cur=3df3ee00 tok=00000d00 next=3df3edc0 td=0x3df3edc0 status=80e80 |3df3e000| WARNING - Timeout at ehci_wait_td:515! |3df3e000| ehci pipe=0x000ee680 cur=00000000 tok=00000000 next=3df3ecc0 td=0x3df3ecc0 status=1f0c80 Change-Id: I69f1fe38503b0f8d6015b515637d8376726490c0 Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Reviewed-on: https://review.coreboot.org/18905 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
* mainboard: use SeaBIOS config only when it's the payload of choiceLubomir Rintel2017-09-263-0/+3
| | | | | | | | | | | | It makes no sense for Das U-Boot which uses the same setting. Change-Id: I1629aecf33cb62bb1e6856ef5627748a7dc74d8a Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Reviewed-on: https://review.coreboot.org/21611 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Martin Roth <martinroth@google.com>
* mb/google/*: Use newly added Chrome EC boardid functionFurquan Shaikh2017-09-2636-357/+10
| | | | | | | | | | | | Instead of duplicating code across multiple mainboards, use newly added helper function to read boardid from Chrome EC. Change-Id: I1671c0a0b87d0c4c45da5340e8f17a4a798317ca Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/21682 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* binaryPI boards: Fix indirect AGESA.h includeKyösti Mälkki2017-09-269-0/+9
| | | | | | | | Change-Id: I3f6030879da61168adf42db0a4913d70a737594e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21649 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* AGESA cimx: Move cb_types.h to vendorcodeKyösti Mälkki2017-09-262-2/+2
| | | | | | | | | | | | This file mostly mimics Porting.h and should be removed. For now, move it and use it consistently with incorrect form as #include "cbtypes.h". Change-Id: Ifaee2694f9f33a4da6e780b03d41bdfab9e2813e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21663 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* AGESA: Remove heap allocations from OemCustomize.cKyösti Mälkki2017-09-2624-1845/+624
| | | | | | | | | | We can simply declare these structures const. Change-Id: I637c60cc2f83e682bd5e415b674f6e27c705ac91 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21631 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* AGESA binaryPI boards: Fix some whitespaceKyösti Mälkki2017-09-2634-622/+622
| | | | | | | | Change-Id: I150d4a71536137a725f43d900d483e7e35592bb3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21629 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
* amd/torpedo: Drop PlatformGnbPcieComplex.hKyösti Mälkki2017-09-262-67/+0
| | | | | | | | | | | | Copy-paste, was not really used at all. Change-Id: I9a916f6fa0f6a48de6ac62be6f366cee0e406a8f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21648 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
* google/snappy: Override SKU ID by VPDKevin Chiu2017-09-261-0/+43
| | | | | | | | | | | | | | | | Since snappy PCB may have over 9 SKU and current GPIO board ID GP16/GP17 is insufficient to use. Using VPD to control could prevent H/W change. BUG=b:65339688 BRANCH=reef TEST=emerge-snappy coreboot Change-Id: I55ab741354797e022dd945da9c8499ee5e041316 Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/21533 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
* mainboard/google/reef: expose sku strapping helper functionAaron Durbin2017-09-262-3/+12
| | | | | | | | | | | | | | | | variant_board_sku() callback exists to allow some of the variants to report the sku id differently based on board implementation. However, there are cases where there are multiple ways to encode the sku id, but the original way should be used as a fallback. As such expose a helper function, sku_strapping_value(), such that there isn't code duplication for the common fallback case. BUG=b:65339688 Change-Id: I1e917733eb89aebc41a483e2001a02acfda31bf4 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/21645 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soraka: Ensure I2C5 frequency is less than 400kHzFurquan Shaikh2017-09-261-2/+2
| | | | | | | | | | | | | | | | Update I2C5 bus parameters to obtain clock frequency <400kHz. BUG=b:65062416 TEST=Verified using an oscilloscope that I2C5 bus frequency in factory is ~397kHz. Change-Id: I3d0b0388343d4c6c5e7eabf3e06799d059307517 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/21669 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* mb/lenovo/x2?0/devicetree: Fix regression of BDC detectionPatrick Rudolph2017-09-252-6/+10
| | | | | | | | | | | | | | | | The x220 and x230 do have BDC detection, but it's broken. Disable BDC detection on those two boards, and add a comment why it doesn't work. The issue has been reported and tested on Lenovo X220. Change-Id: Id1ccc2c4387370e284ff8964e1c41d945cefe74c Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/21587 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
* mb/intel/dg43gt: Add romstage timestampsArthur Heymans2017-09-231-0/+6
| | | | | | | | | Change-Id: I0383dd9b582d5c77be66ecd74bcf1a438f874cc7 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/21635 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
* mb/intel/dg43gt: Set SuperIO gpio correctlyArthur Heymans2017-09-231-5/+9
| | | | | | | | | | Set SuperIO GPIO like vendor firmware. Change-Id: I46a48776382eb0d9be9727691c68912991e14dfe Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/21627 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
* mb/*/*: Remove rtc nvram configurable baud rateArthur Heymans2017-09-23226-1737/+195
| | | | | | | | | | | | | | | | There have been discussions about removing this since it does not seem to be used much and only creates troubles for boards without defaults, not to mention that it was configurable on many boards that do not even feature uart. It is still possible to configure the baudrate through the Kconfig option. Change-Id: I71698d9b188eeac73670b18b757dff5fcea0df41 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19682 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* mb/asrock/g41c-gs: Fix the SATA clock output on ck505Arthur Heymans2017-09-222-0/+7
| | | | | | | | | | | | | | | | | | | | With reset default of the clockgen on this board the SATA clock which needs to be 100MHz depends on FSB BSEL straps. This explains why SATA was originally tested to be working but fails with CPUs operating at different FSB. This change sets a bit in the clockgen configuration which fixes the SATA clock. TESTED on with a 1333MHz FSB CPU. Change-Id: Ic2b8ca91920f015ae3265871bc092023302fefdc Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/21257 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
* mb/intel/d510mo: Use common ramstage driver to configure the ck505Arthur Heymans2017-09-223-6/+14
| | | | | | | | | | | TESTED, the screen doesn't jiggle (caused by wrong clock on reset default clockgen configuration) Change-Id: Icfa22daf90f9e2eff13b4fc5994664e96903dd1e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/21222 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
* mainboard/intel/cannonlake_rvp: enable SATABora Guvendik2017-09-222-0/+8
| | | | | | | | | | Set sata enable FSP parameters. Change-Id: Ie4723b37f0a2028d22f0a344e45a1ded51deecd0 Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/21407 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/purism/librem13v2: Remove redundant MAINBOARD_VENDOR settingJonathan Neuschäfer2017-09-221-4/+0
| | | | | | | | | | | | Unlike Chromebooks, Purism laptops are only sold under one vendor name, so MAINBOARD_VENDOR only needs to be set in src/mainboard/purism/Kconfig. Change-Id: If0b33df01ff3327272d089b7efb8e64fa1233fdf Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/21591 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Youness Alaoui <snifikino@gmail.com>
* google/celes: add new board as variant of cyan baseboardMatt DeVillier2017-09-2112-0/+792
| | | | | | | | | | | | | | | | | | Add support for google/celes (Samsung Chromebook 3) as a variant of the cyan Braswell baseboard. - Add board-specific code as the new celes variant - Add new trackpad I2C device to the baseboard for potential reuse by other variants Sourced from Chromium branch firmware-celes-7287.92.B, commit 9f0760a: Revert "Revert "soc/intel/braswell: Populate NVS SCC BAR1"" Change-Id: Id52d3c523bae7745b3dc04da012ab65c1fb37887 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/21572 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
* google/banon: add new board as variant of cyan baseboardMatt DeVillier2017-09-2111-0/+745
| | | | | | | | | | | | | | | | Add support for google/banon (Acer Chromebook 15 CB3-531) as a variant of the cyan Braswell baseboard. - Add board-specific code as the new banon variant Sourced from Chromium branch firmware-strago-7287.B, commit 02dc8db: Banon: 2nd source DDR memory (Micro-MT52L256M32D1PF) Change-Id: If29e95deee88b79522547e16fc80c2d5378da7c7 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/21571 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
* google/terra: add new board as variant of cyan baseboardMatt DeVillier2017-09-2119-0/+1624
| | | | | | | | | | | | | | | | | | Add support for google/terra (Asus Chromebook C202SA/C300SA) as a variant of the cyan Braswell baseboard. - Add board-specific code as the new terra variant - Add code to the baseboard to handle terra's unique thermal management - Add new shared SPD files to baseboard Sourced from Chromium branch firmware-terra-7287.154.B, commit 153f08a: Revert "Revert "soc/intel/braswell: Populate NVS SCC BAR1"" Change-Id: Ib2682eda15a989f2ec20c78317561f5b6a97483a Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/21570 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
* amd/gardenia: Fix number of memory channelsMarc Jones2017-09-211-1/+1
| | | | | | | | | | | Gardenia (with Stoney Processor) has a single memory channel, not two. This corrects DMI type 17 reporting and the memory clear functions. Change-Id: If49b6a9f37b2687ea2f64105fb9e476a89aa87ed Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/21602 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* superio/winbond/*: Unify w*_set_clksel_48()Keith Hui2017-09-2112-12/+12
| | | | | | | | | | | | | | | | | This function is identical throughout all Winbond superios in the tree, so move it into superio/winbond/common/early_init.c, renamed from early_serial.c because it now does more than just early serial. Change all affected mainboards to use the unified function. Change-Id: If05e0db93375641917e538d83aacd1b50fbd033b Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/21331 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
* siemens/mc_apl1: Move SCI to IRQ 10Mario Scheithauer2017-09-211-0/+2
| | | | | | | | | | | | IRQ 9 is used for different purpose on this mainboard so move SCI away to IRQ 10. Change-Id: I7f055447f5d92bc4696b38e8103a7aebde95d9d3 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/21586 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* mb/google/{poppy,soraka}: Enable LTR for Root portRizwan Qureshi2017-09-212-2/+6
| | | | | | | | | | | | | | | Enable LTR for Root port 0, where wifi card is connected. BUG=b:65570878 TEST=After enbaling LTR on port 0 on the MB devicetree, No errors reported by AER driver for root port 0. Change-Id: I222a87fe2094c8424760ccf578e32b9ac042f014 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/21548 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rajat Jain <rajatja@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
* vboot: reset vbnv in cmos when cmos failure occursAaron Durbin2017-09-201-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | There's an occasional issue on machines which use CMOS for their vbnv storage. The machine that just powers up from complete G3 would have had their RTC rail not held up. The contents of vbnv in CMOS could pass the crc8 though the values could be bad. In order to fix this introduce two functions: 1. vbnv_init_cmos() 2. vbnv_cmos_failed() At the start of vboot the CMOS is queried for failure. If there is a failure indicated then the vbnv data is restored from flash backup or reset to known values when there is no flash backup. BUG=b:63054105 Change-Id: I8bd6f28f64a116b84a08ce4779cd4dc73c0f2f3d Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/21560 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
* google/kahlee: Prevent AGESA memory clearMarc Jones2017-09-201-0/+2
| | | | | | | | | | | | | | | | The Linux Pstore area must not be cleared on a reboot. Set the option to not clear the memory in AGESA. BUG=b:64193190 BRANCH=none TEST=Memory clear isn't called in AGESA. Change-Id: I9b8286ade718fa80bf3badd478ab9a7df643ab98 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/21596 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* google/kahee: Fix number of memory channelsMarc Jones2017-09-201-1/+1
| | | | | | | | | | | | | | | | | Kahlee has a single memory channel, not two. This corrects DMI type 17 reporting and the memory clear functions. BUG=b:65403853, b:64193190 BRANCH=none TEST=AGESA DMI reports the correct number of DIMMs. Change-Id: Ic263d2677a480448beaf3850391b1a3d4ed38657 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/21595 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* mainboard/intel/cannonlake_rvp: Add PCI, PCIE IRQs to DSDT tableBora Guvendik2017-09-191-0/+5
| | | | | | | | Change-Id: Id0b2b9e9ae2755ed89cee337a1a085fc4e95b073 Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/21531 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* AGESA binaryPI: Clean up amdfamXX.h includeKyösti Mälkki2017-09-19105-105/+0
| | | | | | | | Change-Id: Iba8b8d33e1f10e28745234988d97d4fafd04c798 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21583 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
* mb/google/poppy: Add lens_focus property for OV13858 camera moduleV Sowmya2017-09-161-1/+3
| | | | | | | | | | | | | | | | | Add lens_focus property with reference to VCM device for OV13858 camera module to register the corresponding v4l2 sub-device asynchronously. BUG=b:64133998 BRANCH=none TEST=Build and boot soraka. Dump DSDT and verified that it has the required entries and verified the camera functionality. Change-Id: Ib22403f668dd07d6b9226fe2c22b533223b69473 Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/21512 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* google/lulu,gandof: set kb backlight on bootMatt DeVillier2017-09-162-2/+8
| | | | | | | | | | | | | | | | | | | Set keyboard backlight to 75% on boot, except when resuming from S3. This enables the backlight at a reasonable level prior to the OS driver taking over, providing early proof-of-life and enhanced usability in grub etc. Uses same method as other google boards with a keyboard backlight (chell, link, samus). 75% value determined based on user feedback. TEST: boot google/lulu,gandof boards, observe keyboard backlight enabled in pre-OS environment. Change-Id: I7ed59289419af21764b1b5bd0a534d3b630c6c6b Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/21330 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
* google/reks: add new board as variant of cyan baseboardMatt DeVillier2017-09-1616-0/+925
| | | | | | | | | | | | | | | | | | Add support for google/reks (Lenovo Chromebook N22/N42) as a variant of the cyan Braswell basebaseboard. - Add board-specific code as the new reks variant - Add new I2C touchscreen device and SPD files to the baseboard for potential reuse by other variants Sourced from Chromium branch firmware-reks-7287.133.B, commit 7d812d4: Revert "Revert "soc/intel/braswell: Populate NVS SCC BAR1"" Change-Id: Iac9e2b5661aa33e12927f4cb84ebaee36522a385 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/21128 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
* google/edgar: add new board as variant of cyan baseboardMatt DeVillier2017-09-1619-7/+865
| | | | | | | | | | | | | | | | | | Add support for google/edgar (Acer Chromebook 14 CB3-431) as a variant of the cyan Braswell basebaseboard. - Add board-specific code as the new edgar variant - Add common code to the baseboard which will apply to all variants other than cyan Sourced from Chromium branch firmware-edgar-7287.167.B, commit 2319742: Edgar: Add Micron MT52L256M32D1PF-107 SPD data Change-Id: I58548cbbc85828f37c0023e8aa9e09bdca612659 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/21127 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
* mainboard/intel/glkrvp: Add support for audioHannah Williams2017-09-164-20/+63
| | | | | | | | | | | | | | | | | | | This patch adds the below: 1) Add correct SSP endpoint config for spk and headset 2) Update GPIO config for jack detection 3) Update GPIO config for I2S pins TEST=sound card binds TEST=cross checked SSDT entries from /sys/firmware/acpi/tables/ TEST=Jack interrupt works Change-Id: I32022ddacd79917730080889c040f842e0c9e6b9 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Reviewed-on: https://review.coreboot.org/19799 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* mainboard/intel/cannonlake: Add ec entry into flashmapLijian Zhao2017-09-151-6/+7
| | | | | | | | | | | | | | | | Add EC entries into chromeos.fmd file. BRANCH=None BUG=None TEST=Flash image and confirm system can get out of reset successfully. System will not be able to reach reset vector if flash map described in coreboot does not match intel flash map generated from fit. Change-Id: Ic18ce59941b4ff8171fe661d332e3e521d988341 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/21526 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/poppy: enable AER for PCIe root port 0Rizwan Qureshi2017-09-151-0/+2
| | | | | | | | | | | | | | Enable PCIe Advanced Error Reporting for PCIe root port 0. BUG=b:64798078 TEST="lspci" shows that AER is enabled in the capabilities list. Change-Id: I8a818a9539b8d4f103d551ffd59713c9bbbc13ce Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/21425 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
* google/cyan: convert to variant configurationMatt DeVillier2017-09-1527-343/+492
| | | | | | | | | | | | | | | | | | | | | | | | | | | Setup cyan to be the baseboard for other Google Braswell boards, to be added in subsequent commits: - Keep code common to all Google Braswell boards in the baseboard, and separate out the board-specific bits into the new cyan variant. - Define the I2C ACPI devices such that they can be easily reused for other variants. - Switch the trackpad/touchscreen interrupts from edge to level, for better performance/compatibility, as was done with all previous Google boards. - Add code to the baseboard to allow optional variant-specific parameters to be used for both memory and silicon init. - Remove superfluous includes, replace some hardcoded values with variables, and correct typos/formatting errors. Change-Id: Iabbbad16efa9cfa79338f4e94d0771779900d8d9 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/21126 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* mainboard/intel/cannonlake_rvp-u: Configure USB portsPratik Prajapati2017-09-141-0/+18
| | | | | | | | | | Configure USB2, USB3 and Type-C ports for CannonLake-U RVP Change-Id: Id875063721ccb62ad4b5187c81f6abf44bf93f74 Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/21482 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* mainboard/intel/cannonlake_rvp-y: Configure USB portsPratik Prajapati2017-09-141-0/+18
| | | | | | | | | | Configure USB2, USB3 and Type-C ports for CannonLake-Y RVP Change-Id: Ic3b6b481cb33bfefb267910a5e649877d900d109 Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/21481 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* siemens/mc_apl1: Add delay to wait for legacy devicesWerner Zeh2017-09-141-0/+31
| | | | | | | | | | | | | | | | | There are old legacy onboard devices which are too slow for a coreboot boot with log level BIOS_ERR. In this case coreboot is so fast that these devices do not have enough time to become visible on the PCI bus and this in turn leads to missing resource allocation for this devices. The most generic way to work around this problem on existing hardware is to introduce a delay right before the PCI enumeration starts. The needed delay time depends on the hardware and will therefore be get from hwinfo. Change-Id: Ia91babc81e3a347bbc498c3def97b2ea70e10922 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/21518 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
* AGESA vendorcode: Move PlatformInstall.hKyösti Mälkki2017-09-1325-25/+25
| | | | | | | | | | | | | | All thse Option.*Install.h files are about configuring what eventually is referenced in the final libagesa build. It's self-contained so isolate these together with PlatformInstall.h to hide them from rest of the build. Change-Id: Id9d90a3366bafc1ad01434599d2ae1302887d88c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21298 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-07 12:37:15 +0000