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* nb/amd/mct_ddr3: Restart system on training failure instead of using die()Timothy Pearson2016-04-281-1/+4
* nb/amd/mct_ddr3: Report correct DIMM in MRS setup routinesTimothy Pearson2016-04-261-3/+3
* nb/amd/mct_ddr3: Fix a number of minor errors in RDIMM setupTimothy Pearson2016-04-261-17/+72
* nb/amd/mct_ddr3: Scale lane delays for each DIMM after MEMCLK changeTimothy Pearson2016-04-252-3/+3
* Revert "nb/amd/mct_ddr3: Disable MCE framework during DRAM training"Timothy Pearson2016-04-223-27/+27
* nb/amd/mct_ddr3: Enhance debugging around MEMCLK frequency changeTimothy Pearson2016-04-221-1/+7
* nb/amd/mct_ddr3: Fix RDIMM training on certain DIMMsTimothy Pearson2016-04-221-44/+39
* nb/amd/mct_ddr3: Run fence training on each node after memory clock changeTimothy Pearson2016-04-221-2/+2
* AMD CIMX: Drop unused codeKyösti Mälkki2016-04-201-7/+0
* northbridge/amd/{lx,gx2}: remove immediate accesses of 0Patrick Georgi2016-04-164-8/+6
* amd/agesa/family12/dimmSpd.c: Indent (tab) fixEdward O'Callaghan2016-04-131-21/+23
* and/nb/mct_ddr3: Pack all structures passed to ramstage and set alignmentTimothy Pearson2016-04-112-9/+9
* nb/amd/amdfam10: Write MCT variables to flash after PCI configurationTimothy Pearson2016-04-112-12/+7
* Revert "nb/amd/mct_ddr3: Enable DIMM parity when RDIMMs installed"Timothy Pearson2016-04-081-1/+3
* nb/amd/mct_ddr3: Reenable sync flood after ECC initTimothy Pearson2016-04-082-8/+9
* nb/amd/mct_ddr3: Add MCE reporting logicTimothy Pearson2016-04-083-1/+25
* nb/amd/amdfam10: Only flag machine check exception if valid bit is setTimothy Pearson2016-04-081-1/+1
* nb/amd/mct_ddr3: Cache whether ECC is allowed at the platform levelTimothy Pearson2016-04-082-3/+9
* nb/amd/mct_ddr3: Fix revision mask for DR processorsTimothy Pearson2016-04-011-1/+1
* nb/amd_mct_ddr3: Move DRAM MCE sync flood enable to ramstageTimothy Pearson2016-03-314-10/+49
* nb/amd/mct_ddr3: Clear early MCEs and report DRAM MCEsTimothy Pearson2016-03-312-10/+28
* nb/amd/mct_ddr3: Disable MCE framework during DRAM trainingTimothy Pearson2016-03-313-17/+29
* nb/amd/mct_ddr3: Enable DIMM parity when RDIMMs installedTimothy Pearson2016-03-301-3/+1
* northbridge/amd/amdfam10: Add family15h model10h-1fh (Trinity)Damien Zammit2016-03-309-10/+67
* nb/amd/mct_ddr3: Use standard C function calls in mct_ResetDataStruct_D()Timothy Pearson2016-03-281-21/+8
* nb/amd/amdmct: Select max_lanes based on ECC presence or absenceDamien Zammit2016-03-264-88/+151
* nb/amd/mct_ddr3: Set the NBP0 read latency from P0 trained valuesTimothy Pearson2016-03-245-20/+21
* nb/amd/mct_ddr3: Remove spurious Addl_Index variable in dqsTrainMaxRdLatency_...Timothy Pearson2016-03-231-3/+1
* nb/amd/amdmct/mct_ddr3: Ensure BlockRxDqsLock does not remain setTimothy Pearson2016-03-211-0/+6
* nb/amd/mct_ddr3: Use correct initial UI setting during DRAM trainingTimothy Pearson2016-03-131-1/+1
* nb/amd/mct_ddr3: Consolidate duplicated codeTimothy Pearson2016-03-122-110/+87
* nb/amd/mct_ddr3: Train correct receiver in TrainDQSRdWrPos_D_Fam15Timothy Pearson2016-03-111-4/+1
* nb/amd/mct_ddr3: Consolidate calls to MCT minimum clock setting fetchTimothy Pearson2016-03-111-2/+5
* nb/amd/mct_ddr3: Require minumum training quality for both read and writeTimothy Pearson2016-03-111-2/+10
* nb/amd/mct_ddr3: Set read DQS delay to 1UI before calculating read latencyTimothy Pearson2016-03-111-0/+7
* nb/amd/mct_ddr3: Properly initialize arrays and add bounds checksTimothy Pearson2016-03-111-5/+10
* nb/amd/mct_ddr3: Restore previous DQS delay values on failed loopTimothy Pearson2016-03-111-0/+6
* nb/amd/amdmct: Add socket specific configuration for FM2Damien Zammit2016-02-196-21/+291
* nb/amd/mct_ddr3: Fix RDIMM training failure on Fam15hTimothy Pearson2016-02-051-0/+3
* nb/amd/mct_ddr3: Work around RDIMM training failureTimothy Pearson2016-02-054-6/+113
* src: Fix various spelling and whitespace issues.Martin Roth2016-02-023-42/+42
* nb/amd/amdmct/mct_ddr3: Save and restore SkewMemClk for S3 resumeTimothy Pearson2016-02-012-2/+9
* nb/amdmct/mct_ddr3: Enable mainboard voltage setTimothy Pearson2016-01-291-1/+21
* cpu/amd/fam10h-fam15h: Correctly create APIC ID on single node systemsTimothy Pearson2016-01-291-1/+3
* nb/amd/mct_ddr3: Properly set MR0 WR valueTimothy Pearson2016-01-241-1/+1
* nb/amd/mct_ddr3: Add additional verbose-level debug statementsTimothy Pearson2016-01-242-2/+10
* nb/amd/mct_ddr3: Update drive strength configurationTimothy Pearson2016-01-241-17/+32
* northbridge/amd/amdmct/mct_ddr3: Enable fast refresh on ETR devicesTimothy Pearson2016-01-242-3/+14
* northbridge/amd/amdmct: Add termination and timing values for C32 socketsTimothy Pearson2016-01-243-1/+848
* northbridge/amd/amdfam10: Update DRAM speed limits for C32 socketsTimothy Pearson2016-01-241-87/+259
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