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* treewide: Remove "this file is part of" linesPatrick Georgi2020-05-111-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Stefan thinks they don't add value. Command used: sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool) The exceptions are for: - crossgcc (patch file) - gcov (imported from gcc) - elf.h (imported from GNU's libc) - nvramtool (more complicated header) The removed lines are: - fmt.Fprintln(f, "/* This file is part of the coreboot project. */") -# This file is part of a set of unofficial pre-commit hooks available -/* This file is part of coreboot */ -# This file is part of msrtool. -/* This file is part of msrtool. */ - * This file is part of ncurses, designed to be appended after curses.h.in -/* This file is part of pgtblgen. */ - * This file is part of the coreboot project. - /* This file is part of the coreboot project. */ -# This file is part of the coreboot project. -# This file is part of the coreboot project. -## This file is part of the coreboot project. --- This file is part of the coreboot project. -/* This file is part of the coreboot project */ -/* This file is part of the coreboot project. */ -;## This file is part of the coreboot project. -# This file is part of the coreboot project. It originated in the - * This file is part of the coreinfo project. -## This file is part of the coreinfo project. - * This file is part of the depthcharge project. -/* This file is part of the depthcharge project. */ -/* This file is part of the ectool project. */ - * This file is part of the GNU C Library. - * This file is part of the libpayload project. -## This file is part of the libpayload project. -/* This file is part of the Linux kernel. */ -## This file is part of the superiotool project. -/* This file is part of the superiotool project */ -/* This file is part of uio_usbdebug */ Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* nb/i945: Improve code formattingElyes HAOUAS2020-04-111-19/+18
| | | | | | | | Change-Id: I8a1eadcdc51dedd1e17eb6ae7847d9209b2bd598 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39934 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* nb/intel/i945: Use 'const' to set pci_devfn_t staticallyElyes HAOUAS2020-04-091-3/+3
| | | | | | | | | Change-Id: I879dd2fc61bc385486b506e2123f32629a67f518 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40227 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* src/northbridge: Use SPDX for GPL-2.0-only filesAngel Pons2020-04-051-13/+2
| | | | | | | | | | Done with sed and God Lines. Only done for C-like code for now. Change-Id: Id2cb642baa764fd69543460ba869cd822ab5acad Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40056 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
* src (minus soc and mainboard): Remove copyright noticesPatrick Georgi2020-03-171-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | They're listed in AUTHORS and often incorrect anyway, for example: - What's a "Copyright $year-present"? - Which incarnation of Google (Inc, LLC, ...) is the current copyright holder? - People sometimes have their editor auto-add themselves to files even though they only deleted stuff - Or they let the editor automatically update the copyright year, because why not? - Who is the copyright holder "The coreboot project Authors"? - Or "Generated Code"? Sidestep all these issues by simply not putting these notices in individual files, let's list all copyright holders in AUTHORS instead and use the git history to deal with the rest. Change-Id: I89b10076e0f4a4b3acd59160fb7abe349b228321 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39611 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* treewide: Capitalize 'CMOS'Elyes HAOUAS2020-02-241-1/+1
| | | | | | | | | Change-Id: I1d36e554618498d70f33f6c425b0abc91d4fb952 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38928 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Peter Lemenkov <lemenkov@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* drivers/pc80/rtc: Separate {get|set}_option() prototypesKyösti Mälkki2020-01-091-1/+1
| | | | | | | | | | | | Long-term plan is to support loading runtime configuration from SPI flash as an alternative, so move these prototypes outside pc80/. Change-Id: Iad7b03dc985550da903d56b3deb5bd736013f8f1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38192 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* src/northbridge: Remove unused <stdlib.h>Elyes HAOUAS2019-12-191-1/+0
| | | | | | | | Change-Id: I7a214196b05d3af06c8cd742a6154b0627a0d82f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33685 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mainboard/(i945,ich7): Remove commented RCBA32(0x341c) codeElyes HAOUAS2019-12-101-0/+1
| | | | | | | | | | | PCIe root port clock gate is already enabled at i945/early_init.c Also fix comments when only PCIe root port is enabled. Change-Id: Ica38529dbdd5cc51b19b426999a1d9f0b678b4f5 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37576 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* sb/intel/i82801gx: Add common early codeArthur Heymans2019-11-141-16/+0
| | | | | | | | | | | | | | | | | Remove some of the code duplication on i82801gx. x4x boards are left untouched for now since that northbridge also supports i82801jx. The order of some things has changed: - on i945 early_ich7_init is now done before the raminit - enabling the IOAPIC is done before the raminit Change-Id: Ie39549938891e17667a8819b49a78b9c71c8ec9e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36754 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* sb/intel/i82801gx: Add a function to set up BARArthur Heymans2019-11-131-4/+1
| | | | | | | | | | This removes some of the sb code in the nb. Change-Id: I2ab894be93f210220fa55ddd10cd48889f308e5b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36753 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
* kontron/986lcd-m,roda/rk886ex: Drop secondary PCI resetKyösti Mälkki2019-10-051-9/+0
| | | | | | | | | | | The extra PCI bus RST# and 200ms delay there was workaround for custom add-on hardware. Change-Id: I38c4677cfb41d620498be8e0c257b517995bad5c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35765 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* intel/i945,i82801gx: Refactor early PCI bridge resetKyösti Mälkki2019-10-051-23/+20
| | | | | | | | Change-Id: Ibd5cd2afc8e41cc50abdda0fb7d063073c3acdc1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35678 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* intel/i945: Define peg_plugin for potential add-on PCIe cardKyösti Mälkki2019-10-011-7/+10
| | | | | | | | Change-Id: I06f6a7ed7a1ce935d154b8c7b11dcb81608329b9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35677 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* intel/i945: Delay bridge VGA IO enable to ramstageKyösti Mälkki2019-10-011-5/+0
| | | | | | | | Change-Id: Ifc54ecc96b6d9d79d5a16b2d7baeae70b59275c9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35676 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* intel/i945: Define p2peg for PCIe x16 slotKyösti Mälkki2019-10-011-80/+82
| | | | | | | | Change-Id: I0e9dd06376c1076be4a4c41ff87dfd3cf820d7bc Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35675 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* intel/pci: Utilise pci_def.h for PCI_BRIDGE_CONTROLKyösti Mälkki2019-10-011-21/+20
| | | | | | | | | | | This is a PCI standard register, no need to alias its definitions under different names. Change-Id: Iea6b198dd70fe1e49b5dc0824dba62628dedc69a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35521 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* src/northbridge: Add missing 'include <types.h>'Elyes HAOUAS2019-05-291-2/+3
| | | | | | | | | | | <types.h> is supposed to provide <stdint.h> and <stddef.h>. When <types.h> is included, <stdint.h> and/or <stddef.h> is removed. Change-Id: Iad5367bed844b866b2ad87639eee29a16d9a99ed Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32808 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
* nb/intel/i945: Use macro instead of magic numberElyes HAOUAS2019-05-101-2/+2
| | | | | | | | Change-Id: I028013bd7511b5b9fc80e5f744fcad584cb25fd3 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31027 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* src: Remove unused include <halt.h>Elyes HAOUAS2019-05-061-1/+0
| | | | | | | | Change-Id: I2f142cc80692e60eb0f81f57339a247f6ef4a524 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32611 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* ich7/i945: Use system_reset()Elyes HAOUAS2019-04-291-2/+2
| | | | | | | | | | Use already defined system_reset() function. Change-Id: Ieff4271c4a09d564d5f3415d8bc2c3843c8460f2 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32378 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* nb/intel/i945: Fix ich7_setup_root_complex_topologyElyes HAOUAS2019-04-111-25/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Element Self Description register (ESD) [23:16] is R/WO, so let write the ESD.CID when we start ich7_setup_root_complex_topology. This value is also used to program the R/WO 'Target Component ID' registers of RPxD and HHD. Once it is done, no need to rewrite on them as they become RO. (For more information, please see ICH7 datasheet page 271.) Tested done on 945G-M4 using printk before and after writing. Before this change, writing on those registers had no effect: ESD: 0x0104: 0x00000802 ULD: 0x0110: 0x00000001 ULBA: 0x0118: 0x00000000 RP1D: 0x0120: 0x01000003 RP2D: 0x0130: 0x02000003 RP3D: 0x0140: 0x03000002 RP4D: 0x0150: 0x04000002 HDD: 0x0160: 0x0f000002 RP5D: 0x0170: 0x05000002 RP6D: 0x0180: 0x06000002 Using this patche, those R/WO get the "right" values. i.e., We can see RCBA32(ULBA) is now equal to (uintptr_t)DEFAULT_DMIBAR. ESD: 0x0104: 0x00020802 ULD: 0x0110: 0x01010001 ULBA: 0x0118: 0xfed18000 RP1D: 0x0120: 0x01020003 RP2D: 0x0130: 0x02020003 RP3D: 0x0140: 0x03020002 RP4D: 0x0150: 0x04020002 HDD: 0x0160: 0x0f020002 RP5D: 0x0170: 0x05020002 RP6D: 0x0180: 0x06020002 Change-Id: I3f2199d6da22ce9995496c2a81363710edde81f3 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30993 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* nb/intel/i945: Use DEBUG_RAM_SETUPKyösti Mälkki2019-03-241-16/+2
| | | | | | | | | | | | | | | | Avoid preprocessor here, also we never set loglevel to value of >8 so the call would not be made. The calls to ram_check() were removed, for a long time that function has not tested start..stop region. Change-Id: Ib952b8905c29a5c5c289027071eb6ff59aaa330b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32032 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* src: Use 'include <string.h>' when appropriateElyes HAOUAS2019-03-201-1/+0
| | | | | | | | | | | | | Drop 'include <string.h>' when it is not used and add it when it is missing. Also extra lines removed, or added just before local includes. Change-Id: Iccac4dbaa2dd4144fc347af36ecfc9747da3de20 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31966 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
* nb/intel/i945: Remove 2nd write on SLOTCAP (R/WO)Elyes HAOUAS2019-03-181-5/+0
| | | | | | | | | | | | | SLOTCAP is R/WO, it becomes RO after the first write. Write already done on line #583. Tested using kprint before and after on 945G-M4 board. Change-Id: I27579bc634e357490defabb041457aaa010fb1c8 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31036 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)Julius Werner2019-03-081-7/+7
| | | | | | | | | | | | This patch is a raw application of find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g' Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* src: Drop unused include <arch/acpi.h>Elyes HAOUAS2019-03-061-1/+0
| | | | | | | | Change-Id: I1f44ffeb54955ed660162a791c6281f292b1116a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31715 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
* device/pci: Fix PCI accessor headersKyösti Mälkki2019-03-011-0/+1
| | | | | | | | | | | | | | PCI config accessors are no longer indirectly included from <arch/io.h> use <device/pci_ops.h> instead. Change-Id: I2adf46430a33bc52ef69d1bf7dca4655fc8475bd Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31675 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* nb/intel/i945: Fix typo on DMIBAR32(0x334)Elyes HAOUAS2019-01-271-1/+1
| | | | | | | | | Change-Id: Ib894c24bc787c6c211da26dca78bcd330ded6681 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/31063 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
* nb/intel/i945: Remove initialization already done at bootblockElyes HAOUAS2019-01-271-4/+0
| | | | | | | | | | | Upper 128bytes of CMOS and RCBA are already enabled at bootblock. Tested on 945g-MA. Resuming from suspend is working fine Change-Id: I3f34380b0e700cf60688ad58465f9cb0aeda0928 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/31107 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* i945,ICH7: Write on RPFN only onceElyes HAOUAS2019-01-231-2/+0
| | | | | | | | | | | | RPFN is a R/WO register we write on it in i945/early_init.c and i82801gx/pcie.c Drop the romstage write. Change-Id: If9a131ad12530876a650b7a38daa9c9fc52aefb7 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/31005 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
* nb/intel/i945: Add and use defines for registers of device 0:01.0Elyes HAOUAS2018-11-251-40/+40
| | | | | | | | | | | | | Some registers are not documented in "Mobile Intel 945 Express Chipset Family" datasheet but they are in "Intel 945G/945GZ/ 945GC/945P/945PL Express Chipset Family" datasheet. Change-Id: I81f68a5b16e195626d4d271f8c7036032611bea3 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/29824 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
* nb/intel/i945/early_init.c: Correct the PEG_LC address of DEV(0:01.0)Elyes HAOUAS2018-11-251-1/+1
| | | | | | | | | | | | | | | | This bug/typo was spoted by Felix Held. As documented in the datasheet, to enable PMEGPE, HPGPE, GENGPE, we need to write 0x7 into DEV(0:01.0) register "PCI Express-G Legacy Control" located at 0xec. Used address at 0x114 to enable GPEs is likely a typo. Patch not tested. Change-Id: Iee1c1e4b7fef21608f2678a1d4104b668a66a7e5 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/27307 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* nb/intel/*: Use 2M TSEG instead of 8M on pre-arrandale hardwareArthur Heymans2018-10-241-2/+3
| | | | | | | | | | | | | | 8M was set in the assumption that at least 4M was needed for IED (Intel Enhanced Debug) , but this is not true. The SMRR MTRR's need to have TSEG aligned to its size which is easier when TSEG is only 2M. Also at most 6M of RAM more becomes available for use. Change-Id: I4b114c8dc13699b3c034f0a7060181d9d590737b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/27873 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* nb/intel/{gm45,i945,pineview}: Use macro instead of GGC addressElyes HAOUAS2018-10-081-1/+1
| | | | | | | | Change-Id: I233e835180fd445961b6deb74ea7afc2821c236e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/28909 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* nb/intel/i945: Enable and allocate 8M for TSEGArthur Heymans2018-06-071-0/+5
| | | | | | | | | | | | TSEG can be used as a stage cache and SMM can be relocated here. Tested on Intel D945GCLF, still boots. Change-Id: I0da5a00c98c4c4fb309b2691dc1d4645eb35b4fd Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/25592 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* nb/intel/i945/early_init.c: Replace numbers with macrosElyes HAOUAS2017-09-201-1/+1
| | | | | | | | | | Change-Id: I270d17a2eff2c6664bf936425a6ed344be3feabe Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/21524 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
* nb/intel/i945: Clear timeout bits after disabling watchdogNico Huber2017-09-101-0/+2
| | | | | | | | | | | | | Even with the watchdog disabled, these bits influence other hardware blocks (e.g. SECOND_TO_STS stops SMBus block transfers, possibly yet before they started). Change-Id: If9f93fcc96827bb192148a80b4476796c9358a7a Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/21471 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
* nb/intel: add IS_ENABLED() around Kconfig symbol referencesMartin Roth2017-06-271-2/+2
| | | | | | | | | | | Some of these can be changed from #if to if(), but that will happen in a follow-on commmit. Change-Id: Id5bc8b75b1fa372f31982b8636f1efa4975b61a5 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20346 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* nb/intel/i945: Fix PEG port on 945gcArthur Heymans2017-04-141-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | Vendor BIOS leaves UPMC1 untouched (on 945gc the default is 0x0203). Not running PCIEx16 init which is valid for 945gm seems to fix all issues and instabilities related to the PEG port. According to lspci the link width is at the desired x16. It is unknown if devices requesting a lower width work automatically or need more configuration. What happens is that IGD gets disabled by the disable function in gma.c when an external GPU is found unless CONFIG_ONBOARD_VGA_IS_PRIMARY is set. Setting IGD as secondary makes Linux (4.10) hang, so this behavior is a requirement for now. TESTED on P5GC-MX with a discrete GPU and both CONFIG_ONBOARD_VGA_IS_PRIMARY set and unset. Change-Id: I6da8aa7714073f4b34df5ae3c1eb4c19e27ddc97 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/18549 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
* nb/intel/i945: Fix errors found by checkpatch.plArthur Heymans2017-03-221-26/+30
| | | | | | | | Change-Id: Ic2dd40e73d4a4c091c5ce1f49bbf9ab4d013d7af Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/18704 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
* sb/ich7: Use common/gpio.h to set up GPIOsArthur Heymans2017-01-061-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | This is more consistent with newer Intel targets. This a static struct so it is initialized to 0 by default. To make it more readable: * only setting to GPIO mode is made explicit; * only pins in GPIO mode are either set to input or output since this is ignored in native mode; * only output pins are set high or low, since this is read-only on input; * blink is only operational on output pins, non-blink is not set explicitly; * invert is only operational on input pins, non-invert is not set explicitly. Change-Id: I05f9c52dee78b7120b225982c040e3dcc8ee3e4e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/17639 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
* nb/i945/early_init.c: Add FSB800 and 1067 to Egress Port Virtual ChannelElyes HAOUAS2016-12-211-0/+18
| | | | | | | | | | | | | | | | Values based on vendor bios and suggested by Arthur Heymans for FSB1067. FSB1067: The ratio 1067/800 is proportional to the ratio of EPBAR32(0x2c) bits: 0x1a / 0x14 ~ 1067/800 EPVC1IST: The ratio is also proportional to FSB ratios: 0x9c / 0xf0 ~ 533/800. Change-Id: Ib90e8ea1b82f2fcc3b5c199cace32a7f0aff4b5c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/17198 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* intel/i945: Use romstage_handoff for S3Kyösti Mälkki2016-12-111-10/+2
| | | | | | | | | | | | | | | | | | | Don't use scratchpad registers when we have romstage_handoff to pass S3 resume flag. Scratchpad register was read too late in ramstage so acpi_is_wakeup_s3() did not evaluate correctly. This fixes low memory corruption at 0x1000-0x102c and the lack of coreboot tables (util/cbmem not working) after S3 resume. This also fixes console log from reporting early in ramstage "Normal boot" while on "S3 resume" path. Change-Id: I2922a15a90d2f8272c3482579bdd96f8f33e9705 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17675 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* intel i945 gm45 x4x post-car: Use postcar_frame for MTRR setupKyösti Mälkki2016-12-111-1/+0
| | | | | | | | | | | | | Adapt implementation from skylake to prepare for removal of HIGH_MEMORY_SAVE and moving on to RELOCATABLE_RAMSTAGE. With this change, CBMEM region is set early-on as WRBACK with MTRRs and romstage ram stack is moved to CBMEM. Change-Id: Idee5072fd499aa3815b0d78f54308c273e756fd1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15791 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* nb/intel: Fix some spelling mistakes in comments and stringsMartin Roth2016-11-211-1/+1
| | | | | | | | Change-Id: I4a8297397d878e38516c8df19dd311c7ef19ec06 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/17478 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
* nb/intel/i945/early_init.c: Add DDR2-667 detection for 945GCElyes HAOUAS2016-11-091-0/+1
| | | | | | | | | | | | | | 945G-M4 returns : "unknown max. RAM clock (2)", however, it supports up to DDR2-667MHz. i945/raminit.c sdram_capabilities_max_supported_memory_frequency() function returns 667 for case 2. Change-Id: I3d54c88af897a71db757d00288f3968ed2c19151 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/17191 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
* nb/intel/i945/early_init.c: Use "IS_ENABLED(CONFIG_ ....)"Elyes HAOUAS2016-11-021-6/+6
| | | | | | | | | | Change-Id: I230b5425ac9e916a5ee10a49eeaf5d6d44fd49e6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/17192 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
* src/northbridge: Remove unnecessary whitespaceElyes HAOUAS2016-10-041-7/+7
| | | | | | | | Change-Id: Ib06ecd083f00c74f1d227368811729d2944dd1ef Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16851 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
* northbridge/intel/i945: Add space around operatorsElyes HAOUAS2016-09-201-1/+1
| | | | | | | | Change-Id: I24505af163544a03e3eab72c24f25fcdc4b1b16c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16624 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-26 13:03:36 +0000