| Commit message (Collapse) | Author | Age | Files | Lines |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Shorten define names containing PCI_{DEVICE,VENDOR}_ID_ with
PCI_{DID,VID}_ using the commands below, which also take care of some
spacing issues. An additional clean up of pci_ids.h is done in
CB:61531.
Used commands:
* find -type f -exec sed -i 's/PCI_\([DV]\)\(EVICE\|ENDOR\)_ID_\([_0-9A-Za-z]\{2\}\([_0-9A-Za-z]\{8\}\)*[_0-9A-Za-z]\{0,5\}\)\t/PCI_\1ID_\3\t\t/g'
* find -type f -exec sed -i 's/PCI_\([DV]\)\(EVICE\|ENDOR\)_ID_\([_0-9A-Za-z]*\)/PCI_\1ID_\3/g'
Change-Id: If9027700f53b6d0d3964c26a41a1f9b8f62be178
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39331
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
All x86 chipsets and SoCs have the HPET MMIO base address at 0xfed00000,
so define this once in arch/x86 and include this wherever needed. The
old AMD AGESA code in vendorcode that has its own definition is left
unchanged, but sb/amd/cimx/sb800/cfg.c is changed to use the new common
definition.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ifc624051cc6c0f125fa154e826cfbeaf41b4de83
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62304
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Now that the console system itself will clearly differentiate loglevels,
it is no longer necessary to explicitly add "ERROR: " in front of every
BIOS_ERR message to help it stand out more (and allow automated tooling
to grep for it). Removing all these extra .rodata characters should save
us a nice little amount of binary size.
This patch was created by running
find src/ -type f -exec perl -0777 -pi -e 's/printk\(\s*BIOS_ERR,\s*"ERROR: /printk\(BIOS_ERR, "/gi' '{}' ';'
and doing some cursory review/cleanup on the result. Then doing the same
thing for BIOS_WARN with
's/printk\(\s*BIOS_WARNING,\s*"WARN(ING)?: /printk\(BIOS_WARNING, "/gi'
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I3d0573acb23d2df53db6813cb1a5fc31b5357db8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61309
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Lance Zhao
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
| |
Adding the DP_ prefix to the defines for MMIO_NP, MMIO_WE and MMIO_RE
clarifies the scope of those definitions. For consistency also add this
prefix to MMIO_DST_FABRIC_ID_SHIFT.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I3a509ccc071aa51a67552fb9e7195358a76fe4dc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59627
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
| |
Note that there are assumptions about LAPIC MMIO location
in both AMD and Intel sources in coreboot proper.
Change-Id: I2c668f5f9b93d170351c00d77d003c230900e0b4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55194
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Additionally to the PCI IDs of Cezanne it also handles the Renoir ones.
The main difference between those two is that Renoir has two core
complexes while Cezanne only has one core complex. I haven't seen
incompatible changes between those two though, so for example the fabric
IDs are the same and the one that's only present in Renoir is just not
used in Cezanne. Also adding the ACPI parts for those don't have
anything to do with those differences.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I3b2517bc15d872f41183a33857333f1972ff2cb9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50706
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
|
|
I'm not 100% sure yet if this code will be common for all AMD SoCs, so
I'll add a copy for Cezanne for now. This part of the code should
probably be reworked after the initial bringup of Cezanne anyway.
DF MMIO register configuration at the beginning of
data_fabric_set_mmio_np:
=== Data Fabric MMIO configuration registers ===
Addresses are shifted to the right by 16 bits.
idx control base limit
0 a3 fc00 febf
1 a3 1000000 fffcffff
2 a3 d000 f7ff
3 a0 0 0
4 a3 fed0 fed0
5 a0 0 0
6 a0 0 0
7 a0 0 0
DF MMIO register configuration at the end of data_fabric_set_mmio_np:
=== Data Fabric MMIO configuration registers ===
Addresses are shifted to the right by 16 bits.
idx control base limit
0 a3 fc00 febf
1 a3 1000000 fffcffff
2 a3 d000 f7ff
3 10a3 fed0 fedf
4 a0 0 0
5 a0 0 0
6 a0 0 0
7 a0 0 0
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia243a0cad311eb210d14d6242c52f599db22515c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50624
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|