| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | soc/amd/common/blk/pcie: Program LTR max latencies | Matt DeVillier | 2023-04-10 | 1 | -0/+15 |
| * | soc/amd/*: Hook up GPP bridges ops to devicetree | Arthur Heymans | 2022-10-13 | 1 | -31/+2 |
| * | src: Make PCI ID define names shorter | Felix Singer | 2022-03-07 | 1 | -10/+10 |
| * | soc/amd/common/block: add new PCI IDs to common code | Felix Held | 2022-01-12 | 1 | -0/+2 |
| * | src/soc/amd: Remove unused <console/console.h> | Elyes HAOUAS | 2022-01-10 | 1 | -1/+0 |
| * | soc/amd/{common,picasso}: Use common PCIE_GPP_DRIVER driver | Raul E Rangel | 2021-05-12 | 1 | -1/+9 |
| * | soc/amd/common/block/pci: Capitalize PCI ACPI names | Raul E Rangel | 2021-05-12 | 1 | -1/+1 |
| * | soc/amd{common,cezanne}: Move pcie_gpp.c to common | Raul E Rangel | 2021-05-12 | 1 | -0/+88 |
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index : coreboot.git | |
| Coreboot firmware sources | coreboot |
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