| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | soc/amd/mendocino: Add low/no battery VRM limit registers | Tim Van Patten | 2022-09-19 | 1 | -0/+4 |
| * | soc/amd/mendocino: Add VRM limit DPTC registers | Tim Van Patten | 2022-09-19 | 1 | -0/+4 |
| * | amd/mendocino: Control DPTC with only Kconfig | Tim Van Patten | 2022-09-15 | 1 | -2/+0 |
| * | soc/amd: Remove unsupported DPTC tablet mode settings | Tim Van Patten | 2022-09-12 | 1 | -8/+1 |
| * | soc/amd: Refactor DPTC Tablet Mode | Tim Van Patten | 2022-09-12 | 1 | -3/+3 |
| * | amd: Convert dptc_enable to bool | Tim Van Patten | 2022-09-07 | 1 | -2/+2 |
| * | soc/amd/mendocino: enable CPPC feature | Felix Held | 2022-08-18 | 1 | -0/+7 |
| * | treewide: Rename Sabrina to Mendocino | Jon Murphy | 2022-08-11 | 1 | -0/+107 |
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index : coreboot.git | |
| Coreboot firmware sources | coreboot |
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