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* src: Make PCI ID define names shorterFelix Singer2022-03-071-17/+17
| | | | | | | | | | | | | | | | | | Shorten define names containing PCI_{DEVICE,VENDOR}_ID_ with PCI_{DID,VID}_ using the commands below, which also take care of some spacing issues. An additional clean up of pci_ids.h is done in CB:61531. Used commands: * find -type f -exec sed -i 's/PCI_\([DV]\)\(EVICE\|ENDOR\)_ID_\([_0-9A-Za-z]\{2\}\([_0-9A-Za-z]\{8\}\)*[_0-9A-Za-z]\{0,5\}\)\t/PCI_\1ID_\3\t\t/g' * find -type f -exec sed -i 's/PCI_\([DV]\)\(EVICE\|ENDOR\)_ID_\([_0-9A-Za-z]*\)/PCI_\1ID_\3/g' Change-Id: If9027700f53b6d0d3964c26a41a1f9b8f62be178 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39331 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
* arch/x86: factor out and commonize HPET_BASE_ADDRESS definitionFelix Held2022-02-251-0/+1
| | | | | | | | | | | | | | | | All x86 chipsets and SoCs have the HPET MMIO base address at 0xfed00000, so define this once in arch/x86 and include this wherever needed. The old AMD AGESA code in vendorcode that has its own definition is left unchanged, but sb/amd/cimx/sb800/cfg.c is changed to use the new common definition. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ifc624051cc6c0f125fa154e826cfbeaf41b4de83 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62304 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
* treewide: Remove "ERROR: "/"WARN: " prefixes from log messagesJulius Werner2022-02-071-3/+2
| | | | | | | | | | | | | | | | | | | | | | | | | Now that the console system itself will clearly differentiate loglevels, it is no longer necessary to explicitly add "ERROR: " in front of every BIOS_ERR message to help it stand out more (and allow automated tooling to grep for it). Removing all these extra .rodata characters should save us a nice little amount of binary size. This patch was created by running find src/ -type f -exec perl -0777 -pi -e 's/printk\(\s*BIOS_ERR,\s*"ERROR: /printk\(BIOS_ERR, "/gi' '{}' ';' and doing some cursory review/cleanup on the result. Then doing the same thing for BIOS_WARN with 's/printk\(\s*BIOS_WARNING,\s*"WARN(ING)?: /printk\(BIOS_WARNING, "/gi' Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I3d0573acb23d2df53db6813cb1a5fc31b5357db8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61309 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Lance Zhao Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
* soc/amd/*/data_fabric: use DF_ prefix for bit and shift definesFelix Held2021-11-251-3/+3
| | | | | | | | | | | | Adding the DP_ prefix to the defines for MMIO_NP, MMIO_WE and MMIO_RE clarifies the scope of those definitions. For consistency also add this prefix to MMIO_DST_FABRIC_ID_SHIFT. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I3a509ccc071aa51a67552fb9e7195358a76fe4dc Reviewed-on: https://review.coreboot.org/c/coreboot/+/59627 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
* cpu/x86/lapic: Replace LOCAL_APIC_ADDR referencesKyösti Mälkki2021-06-111-1/+1
| | | | | | | | | | | | Note that there are assumptions about LAPIC MMIO location in both AMD and Intel sources in coreboot proper. Change-Id: I2c668f5f9b93d170351c00d77d003c230900e0b4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55194 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/picasso/data_fabric: add missing data fabric device function 7Felix Held2021-02-241-0/+3
| | | | | | | | | | | | The device function is missing in the PCI device table in the PPR, but is present in the hardware. Verified on a Mandolin board with PCO APU. The corresponding ticket for the PPR is DESPCSOC-6667. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie91438bc905691d443ca4e7841549d1e3bca39ca Reviewed-on: https://review.coreboot.org/c/coreboot/+/51041 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
* soc/amd/common/block/data_fabric: add data_fabric_print_mmio_confFelix Held2021-02-141-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Output on Picasso at the beginning of data_fabric_set_mmio_np: === Data Fabric MMIO configuration registers === Addresses are shifted to the right by 16 bits. idx control base limit 0 93 fc00 febf 1 93 1000000 ffffffff 2 93 d000 f7ff 3 90 0 0 4 93 fed0 fed0 5 90 0 0 6 90 0 0 7 90 0 0 Output on Picasso at the end of data_fabric_set_mmio_np: === Data Fabric MMIO configuration registers === Addresses are shifted to the right by 16 bits. idx control base limit 0 93 fc00 febf 1 93 1000000 ffffffff 2 93 d000 f7ff 3 1093 fed0 fedf 4 90 0 0 5 90 0 0 6 90 0 0 7 90 0 0 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I74617dfc6099489f3c81d0e385b502f1bbecea78 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50640 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/picasso/data_fabric: move more helper functions to common codeFelix Held2021-02-141-28/+3
| | | | | | | | | | | | | The number of data fabric MMIO registers is SoC-specific, so we need to keep that in the SoC code. This also removes a redundant pair of brackets and moves a loop counter declaration into the head of the loop. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8499f1c1f7bf6849b5955a463de2e06962d5de68 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50638 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/picasso/data_fabric: use common access functionsFelix Held2021-02-141-18/+16
| | | | | | | | | Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib8cda860ca0ff81d7703c3277aeec629d89eab45 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50622 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/picasso: move data_fabric_read32 to common codeFelix Held2021-02-141-23/+1
| | | | | | | | | | | The exact same mechanism is used on Cezanne. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I3179d8ec35efa29f9bc66854c3690b389d980bba Reviewed-on: https://review.coreboot.org/c/coreboot/+/50619 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/piasso/data_fabric: rename data_fabric_read_reg32Felix Held2021-01-301-1/+1
| | | | | | | | Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib1b4da8f5daac2bae5e54f213accda03e121297d Reviewed-on: https://review.coreboot.org/c/coreboot/+/50098 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* soc/amd/picasso/data_fabric: factor out indirect address/index writeFelix Held2021-01-301-9/+12
| | | | | | | | Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id7bda8843a5ed0775424a056a05a6c4cb8269e49 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50097 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* soc/amd/picasso: Add data fabric read helper functionJason Glenesk2020-12-111-0/+20
| | | | | | | | | | | | | | | | Add new helper function to support reading a register from the data fabric. BUG=b:155307433 TEST=Boot trembyle with If64fd624597b2ced014ba7f0332a6a48143c0e8c and confirm read values match expected values. BRANCH=Zork Change-Id: If0dc72063fbb99efaeea3fccef16cc1b5b8526f1 Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47726 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* include/device/pci_ids: add model number to data fabric devicesFelix Held2020-11-181-14/+14
| | | | | | | | | | | Different models within family 17h have different PCI IDs for their data fabric PCI devices. Change-Id: I44f8d32c950710e962dc519495b08c92f357ed20 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47676 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
* soc/amd/picasso/data_fabric: make register number parameter unsignedFelix Held2020-09-161-2/+2
| | | | | | | | | | | | The register number is always non-negative, so it should be an unsigned type. Change-Id: I6b6df5a41fe58efc53eaa87c01b88426ea8daa6e Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45430 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
* soc/amd/picasso/data_fabric: include types.hFelix Held2020-09-161-1/+1
| | | | | | | | | | | | | | | | data_fabric.c uses types from stdint.h, but doesn't include stdint.h directly, so replace the inclusion of stdbool.h with types.h which includes both stdbool.h and stdint.h. Change-Id: I4c1ea444e50218cf19fc8fff499929336265bd03 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45429 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
* soc/amd/picasso: Add PCI driver for data fabric devicesFurquan Shaikh2020-07-101-0/+169
Data fabric devices are PCI devices which support PCI configuration space but do not require any MMIO/IO resources. This change adds a PCI driver for the data fabric devices which only provides device operations for adding node to SSDT and returning the ACPI name for the device. Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I3da9287db5febf1a1d7eb1dfbed9f1348f80a588 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43314 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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