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* Revert "UPSTREAM: soc/amd/sabrina,vc/amd/fsp/sabrina: Add UART support for ↵Karthikeyan Ramasubramanian2022-08-011-17/+2
| | | | | | | | | | | | | | | | | | | Sabrina" This reverts commit 78261e308de5361b2ff045091e8fb18cad2a5035. Reason for revert: Now that PSP supports a soft fuse flag to toggle the verstage serial logs, prevent PSP verstage from writing to the UART. BUG=None TEST=Build and boot to OS in Skyrim with PSP verstage. Ensure that PSP verstage logs are not seen twice in the console. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I7ef2d585c320ea5903197939136dd2049a71af95 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66248 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* soc/amd/sabrina: Enable HW Modexp engineKarthikeyan Ramasubramanian2022-08-011-2/+7
| | | | | | | | | | | | | | | | | | HW Modexp engine is verified to be working fine. Any verification failures during PSP verstage are because the firmware body is not read correctly. This might be because of the incorrect SPI ROM mapping. Hence enable the HW modexp engine for keyblock, preamble and firmware body verification. BUG=b:240175446 TEST=Build and boot to OS in Skyrim with PSP verstage using one of the FW slots. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I8f6742630a7049354a24053fce28c477e53259e6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66247 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* soc/amd/sabrina: Disable CCP DMA and HW MODEXPKarthikeyan Ramasubramanian2022-07-271-6/+2
| | | | | | | | | | | | | | | Enabling them causes firmware keyblock/preamble and/or body verification failure. Hence disabling them to use software based verification. Re-enable them once the issue is root-caused. BUG=b:217414563 TEST=Build and boot to OS in Skyrim with PSP and x86 verstage. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I7e259ae5d790977d08afcb0a77f8d4f38c85f39e Reviewed-on: https://review.coreboot.org/c/coreboot/+/66134 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/sabrina: Do not pass SHA operation modeKarthikeyan Ramasubramanian2022-07-272-2/+1
| | | | | | | | | | | | | Currently only SHA_GENERIC is used and does not need to be passed. BUG=b:217414563 TEST=Build and boot to OS in Skyrim with PSP and x86 verstage. Change-Id: Id705b1361fffaf940c51515e7f77d7fb0677fc4a Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66133 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* soc/amd/sabrina: Fix boot region address passed to PSPKarthikeyan Ramasubramanian2022-07-201-1/+1
| | | | | | | | | | | | | | | | | PSP expects PSP L2 directory address relative to the start of the SPI ROM. Also PSP does not expect BIOS L2 directory address since it is an entry in PSP L2 directory. Update the configuration such that PSP verstage passes the right address to PSP. BUG=b:217414563 TEST=Build Skyrim BIOS image. Ensure that PSP verstage passes the address as expected by PSP. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I8dc3aa4cb401d16a68da446f83eb9e68ee290fea Reviewed-on: https://review.coreboot.org/c/coreboot/+/65866 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* soc/amd/sabrina,vc/amd/fsp/sabrina: Add UART support for SabrinaJon Murphy2022-07-061-2/+17
| | | | | | | | | | | | | | Sabrina previously didn't support UART mapping in psp verstage. Now that it has been enabled, add the relevant uart code here. BUG=b:218709292 TEST=Set serial soft fuse, boot to kernel, check logs Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: I591fa69b6e722929839babfff62e9d56c68e1112 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65532 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/sabrina/psp_verstage: Add platform_report_boot_mode APIKarthikeyan Ramasubramanian2022-04-241-0/+11
| | | | | | | | | | | | | | | PSP verstage uses this API to report PSP regarding the platform boot mode. PSP in turn uses the boot mode to either maintain or clean DRM credentials. BUG=None TEST=Build Skyrim BIOS image with PSP verstage enabled. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: Ie13b42b349f5c77322d904b68d5f53a3aed58fc5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63730 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* soc/amd/sabrina/psp_verstage: Unify SVC IDKarthikeyan Ramasubramanian2022-04-242-22/+176
| | | | | | | | | | | | | | | In Sabrina, PSP verstage uses a unified SVC call ID with sub-commands. Update the SVC calls for Sabrina to pass the SVC_VERSTAGE_CMD (command ID) with individual subcommands and the corresponding parameters. BUG=b:220848545, b:217414563 TEST=Build the Skyrim BIOS image with PSP verstage enabled. Change-Id: I56be51aa1dfb00e5f0945014600de2bbbec289db Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63729 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* soc/amd/sabrina/psp_verstage: Implement get_uart_baseRaul E Rangel2022-02-082-0/+12
| | | | | | | | | | | | | | The Sabrina PSP doesn't support mapping the UART, so add a dummy function to return NULL. BUG=b:215599230 TEST=None Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Idad8e4874e78bb96730feecb5a7b17334d12217c Reviewed-on: https://review.coreboot.org/c/coreboot/+/61609 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* soc/amd/sabrina: add new SoC as copy of soc/amd/cezanneFelix Held2022-01-254-0/+258
The Cezanne SoC code was initially started as a copy of example/min86 which only provides enough code to make the SoC code build. Then the different parts of the real SoC support was brought in patch by patch which also helped cleaning up and untangling the code. Since the Cezanne SoC code is now in a rather good shape and the Sabrina SoC is similar to the Cezanne SoC from the coreboot side, the new SoC support is started with a copy of the Cezanne code and all the needed changes will be applied on top of that. In order for the build not to fail due to duplicate files, this patch does not only copy the directory, but also replaces most instances of the Cezanne name with Sabrina. Since the needed blobs aren't available in the 3rdparty/amd_blobs repository yet, the Cezanne blobs are used for now so that the build will succeed. As soon as the proper blobs will be available in that repository, the code will be switched over to use them. As suggested by Nico, I added a "TODO: Check if this is still correct" comment to the beginning of every copied file and all SOC_AMD_COMMON_* Kconfig option selects which will be removed after re-verifying that each file and each selected common code block is still correct for the new SoC. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I978ddbdbfd70863acac17d98732936ec2be8fe3c Reviewed-on: https://review.coreboot.org/c/coreboot/+/61077 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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