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* soc/amd/common/block/apob/apob_cache.c: Add assert for APOB DRAM sizeFred Reitberger2022-08-011-2/+2
| | | | | | | | | | | | | | | | Add static check to ensure the reserved APOB DRAM space is the same size as the MRC_CACHE region specified in the fmap. Update sabrina APOB DRAM size to match the fmap. TEST: Timeless builds identical. Test build with a larger MRC_CACHE than APOB DRAM failed the assert as expected. Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: Ia14f6ef94b9062df0612fe96098b1012085ccf9c Reviewed-on: https://review.coreboot.org/c/coreboot/+/65878 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/[cezanne,picasso,sabrina]/Kconfig: Add PSP_APOB_DRAM_SIZE config optionFred Reitberger2022-07-161-1/+1
| | | | | | | | | | | | | | | | | | | | The APOB in sabrina is larger than in cezanne/picasso and no longer fits in the previously allocated 64K space for it. Other symbols are placed immediately after the APOB region and end up corrupting the APOB data on sabrina. Add a Kconfig option to specify the APOB size in DRAM to reserve enough memory and increase the size for sabrina to 128K TEST=Timeless builds are identical for mandolin/majolica for PCO/CZN. Build chausie and verify symbols do not overlap _apob region BUG=b:224056176 Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: Ia5dbacae67ff02fc8a6ec84b9007110ca254daa3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65852 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* device/resource: Add _kb postfix for resource allocatorsKyösti Mälkki2022-06-221-8/+8
| | | | | | | | | | | | There is a lot of going back-and-forth with the KiB arguments, start the work to migrate away from this. Change-Id: I329864d36137e9a99b5640f4f504c45a02060a40 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64658 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* src: Make PCI ID define names shorterFelix Singer2022-03-071-2/+2
| | | | | | | | | | | | | | | | | | Shorten define names containing PCI_{DEVICE,VENDOR}_ID_ with PCI_{DID,VID}_ using the commands below, which also take care of some spacing issues. An additional clean up of pci_ids.h is done in CB:61531. Used commands: * find -type f -exec sed -i 's/PCI_\([DV]\)\(EVICE\|ENDOR\)_ID_\([_0-9A-Za-z]\{2\}\([_0-9A-Za-z]\{8\}\)*[_0-9A-Za-z]\{0,5\}\)\t/PCI_\1ID_\3\t\t/g' * find -type f -exec sed -i 's/PCI_\([DV]\)\(EVICE\|ENDOR\)_ID_\([_0-9A-Za-z]*\)/PCI_\1ID_\3/g' Change-Id: If9027700f53b6d0d3964c26a41a1f9b8f62be178 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39331 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
* soc/amd/*/northbridge,root_complex: add comment about PCI BARsFelix Held2022-03-031-0/+3
| | | | | | | | | | | | Add a comment to point out that the read_resources functions aren't missing a pci_dev_read_resources call that would add the resources for the BARs of the PC device. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie480832e0d7954135d2171dda986e477ef7b6c09 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62547 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* soc/amd/*/northbridge,root_complex: simplify GNB IOAPIC resource indexFelix Held2022-03-031-1/+1
| | | | | | | | | | | | | | | | | | | | | In the northbridge's and root complex' read_resources function, the GNB IOAPIC resource used MMIO base address of the GNB IOAPIC as index which might be misleading. Instead use idx++ as a unique index for this resource. TEST=Resource allocator doesn't complain and no related warnings or errors in dmesg. The update_constraints console output changes like expected: Before: PCI: 00:00.0 fec01000 base fec01000 limit fec01fff mem (fixed) After: PCI: 00:00.0 0d base fec01000 limit fec01fff mem (fixed) Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8061364879d772469882fc060f92676de6f600a9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62546 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* soc/amd/*/northbridge,root_complex: simplify mmconf_resource indexFelix Held2022-03-031-1/+1
| | | | | | | | | | | | | | | | | | | | In the northbridge's and root complex' read_resources function, the mmconf resource used the number of the MMIO_CONF_BASE MSR as index which might be misleading. Instead use idx++ as a unique index for this resource. TEST=Resource allocator doesn't complain and no related warnings or errors in dmesg. The update_constraints console output changes like expected: Before: PCI: 00:00.0 c0010058 base f8000000 limit fbffffff mem (fixed) After: PCI: 00:00.0 06 base f8000000 limit fbffffff mem (fixed) Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id66c6153fad86bed36db7bd2455075f4a0850750 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62545 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* soc/amd/sabrina: use correct PCI IDsFelix Held2022-01-251-1/+1
| | | | | | | | | | | | Replace the Renoir/Cezanne PCI IDs with the Sabrina ones that were added in commit 27b02c2eee68f4b6c8520c4737224aaaf81f137d (include/device/ pci_ids.h: add PCI IDs for AMD Family 17h Model A0h SoC). Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I427df6f8e8c08fb47ae8513b6cf1085d4294e28f Reviewed-on: https://review.coreboot.org/c/coreboot/+/61080 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
* soc/amd/sabrina: add new SoC as copy of soc/amd/cezanneFelix Held2022-01-251-0/+229
The Cezanne SoC code was initially started as a copy of example/min86 which only provides enough code to make the SoC code build. Then the different parts of the real SoC support was brought in patch by patch which also helped cleaning up and untangling the code. Since the Cezanne SoC code is now in a rather good shape and the Sabrina SoC is similar to the Cezanne SoC from the coreboot side, the new SoC support is started with a copy of the Cezanne code and all the needed changes will be applied on top of that. In order for the build not to fail due to duplicate files, this patch does not only copy the directory, but also replaces most instances of the Cezanne name with Sabrina. Since the needed blobs aren't available in the 3rdparty/amd_blobs repository yet, the Cezanne blobs are used for now so that the build will succeed. As soon as the proper blobs will be available in that repository, the code will be switched over to use them. As suggested by Nico, I added a "TODO: Check if this is still correct" comment to the beginning of every copied file and all SOC_AMD_COMMON_* Kconfig option selects which will be removed after re-verifying that each file and each selected common code block is still correct for the new SoC. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I978ddbdbfd70863acac17d98732936ec2be8fe3c Reviewed-on: https://review.coreboot.org/c/coreboot/+/61077 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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