| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | amd/stoneyridge: Fix SPD files and functions camel case | Marc Jones | 2017-11-20 | 1 | -47/+0 |
| * | soc/amd/stoneyridge: Remove direct AGESA header includes | Martin Roth | 2017-11-14 | 1 | -4/+1 |
| * | soc/amd/stoneyridge: Use uint8_t as type for SPD address | Richard Spiegel | 2017-11-10 | 1 | -1/+1 |
| * | soc/amd/stoneyridge: Use macros for PCI_DEVFN calls | Chris Ching | 2017-10-19 | 1 | -1/+2 |
| * | soc/amd/stoneyridge: Drop some amdlib.h includes | Kyösti Mälkki | 2017-10-04 | 1 | -1/+0 |
| * | stoneyridge: Rename hudson to southbridge | Marc Jones | 2017-08-14 | 1 | -1/+1 |
| * | soc/amd/stoneyridge: Fix most checkpatch errors | Marshall Dawson | 2017-06-27 | 1 | -9/+10 |
| * | vendorcode/amd: Unify Porting.h across all targets | Stefan Reinauer | 2017-06-27 | 1 | -1/+1 |
| * | soc/amd/stoneyridge: Add northbridge support | Marc Jones | 2017-06-26 | 1 | -0/+49 |
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index : coreboot.git | |
| Coreboot firmware sources | coreboot |
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