| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | soc/amd/*: Hook up LPC ops in devicetree | Arthur Heymans | 2022-10-14 | 8 | -22/+8 |
| * | soc/amd/*: Hook up SMBus ops to devicetree | Arthur Heymans | 2022-10-14 | 8 | -16/+8 |
| * | soc/amd: factor out common eMMC code | Felix Held | 2022-10-14 | 15 | -54/+13 |
| * | soc/amd/stoneyridge: move northbridge ops to northbridge device | Felix Held | 2022-10-14 | 2 | -4/+4 |
| * | soc/amd/stoneyridge: use devicetree ops over pci driver | Felix Held | 2022-10-14 | 4 | -35/+8 |
| * | soc/amd/stoneyridge: Hook up device_operations in chipset.cb | Felix Held | 2022-10-14 | 3 | -44/+14 |
| * | soc/amd/stoneyridge: add chipset devicetrees | Felix Held | 2022-10-13 | 3 | -0/+88 |
| * | soc/amd/*: Hook up GPU ops in devicetree | Arthur Heymans | 2022-10-13 | 6 | -23/+6 |
| * | soc/amd/*: Hook up GPP bridges ops to devicetree | Arthur Heymans | 2022-10-13 | 6 | -66/+48 |
| * | soc/amd/acp: Hook up ops in devicetree | Arthur Heymans | 2022-10-13 | 6 | -13/+6 |
| * | soc/amd/morgana: Use devicetree ops over pci driver | Felix Held | 2022-10-13 | 3 | -36/+11 |
| * | soc/amd/mendocino: Use devicetree ops over pci driver | Arthur Heymans | 2022-10-13 | 4 | -45/+20 |
| * | soc/amd/cezanne: Use devicetree ops over pci driver | Arthur Heymans | 2022-10-13 | 3 | -46/+11 |
| * | soc/amd/picasso: Use devicetree ops over pci driver | Arthur Heymans | 2022-10-13 | 3 | -36/+11 |
| * | soc/amd/*: Hook up device_operations in chipset.cb | Arthur Heymans | 2022-10-13 | 9 | -234/+61 |
| * | soc/amd/*: Move emmc disabling to device ops | Arthur Heymans | 2022-10-13 | 9 | -12/+82 |
| * | payloads,src: Replace ALIGN(x, a) by ALIGN_UP(x, a) for clarity | Elyes Haouas | 2022-10-13 | 4 | -10/+10 |
| * | soc/amd/*/psp_verstage/svc: Make svc.h macros common | Fred Reitberger | 2022-10-13 | 8 | -166/+7 |
| * | soc/amd/cezanne: enable LPC decodes if platform uses LPC | Jeremy Soller | 2022-10-13 | 1 | -0/+9 |
| * | treewide: Use 'fadt->x_pm1a_cnt_blk.addrl = fadt->pm1a_cnt_blk' | Elyes Haouas | 2022-10-12 | 5 | -5/+5 |
| * | treewide: Use 'fadt->x_pm_tmr_blk.addrl = fadt->pm_tmr_blk' | Elyes Haouas | 2022-10-12 | 5 | -5/+5 |
| * | treewide: Use 'gpe0_blk' for 'x_gpe0_blk.addrl' | Elyes Haouas | 2022-10-12 | 5 | -5/+5 |
| * | treewide: Use 'gpe0_blk_len' for 'x_gpe0_blk.bit_width' | Elyes Haouas | 2022-10-12 | 5 | -5/+5 |
| * | treewide: Use 'fadt->pm_tmr_len' for 'x_pm_tmr_blk.bit_width' | Elyes Haouas | 2022-10-12 | 5 | -5/+5 |
| * | treewide: Use 'fadt->pm1_cnt_len' for 'x_pm1a_cnt_blk.bit_width' | Elyes Haouas | 2022-10-12 | 5 | -5/+5 |
| * | treewide: Use 'fadt->pm1_evt_len' for 'x_pm1a_evt_blk.bit_width' | Elyes Haouas | 2022-10-12 | 5 | -5/+5 |
| * | soc/amd/common: Remove buildtime error for unknown cpu | Martin Roth | 2022-10-10 | 2 | -3/+7 |
| * | soc/amd/morgana: Add initial commit for new SoC | Martin Roth | 2022-10-10 | 59 | -0/+5728 |
| * | soc/amd/mendocino/psp_verstage: Remove TODO comment | Karthikeyan Ramasubramanian | 2022-10-08 | 1 | -2/+0 |
| * | soc/amd/{CZN,MDN,PCO}: Fix building with only single RW region | Matt DeVillier | 2022-10-07 | 6 | -8/+26 |
| * | soc/amd/{stoney,picasso}/Kconfig: Fix guarding of amdfw | Matt DeVillier | 2022-10-07 | 2 | -2/+2 |
| * | soc/amd/(common,mendocino)/psp_verstage: Pass PSP FW hash table | Kangheui Won | 2022-10-02 | 3 | -0/+66 |
| * | soc/amd/mendocino: Add build rules to separate signed PSP/AMDFW | Karthikeyan Ramasubramanian | 2022-10-02 | 1 | -0/+31 |
| * | soc/amd/common: Add a config to keep signed AMD/PSP FW separately | Karthikeyan Ramasubramanian | 2022-10-02 | 1 | -0/+6 |
| * | soc/amd/common/psp_verstage/fch: use [read,write]8p to avoid typecasts | Felix Held | 2022-09-30 | 1 | -2/+3 |
| * | soc/amd/common/block/smbus/smbus: use [read,write]8p to avoid typecasts | Felix Held | 2022-09-30 | 1 | -2/+3 |
| * | soc/amd/common/block/spi/fch_spi_util: use [read,write][8,16,32]p | Felix Held | 2022-09-30 | 1 | -7/+7 |
| * | soc/amd/common/block/lpc/espi_util: use [read,write][8,16,32]p | Felix Held | 2022-09-30 | 1 | -7/+7 |
| * | soc/amd/cezanne,mendocino,picasso/uart: use write16p to avoid typecasts | Felix Held | 2022-09-30 | 3 | -3/+3 |
| * | soc/amd/picasso/fch: use [read,write]8p to avoid typecasts | Felix Held | 2022-09-30 | 1 | -4/+4 |
| * | soc/amd/stoneyridge/fch: use read[16,32]p to avoid typecasts | Felix Held | 2022-09-30 | 1 | -5/+3 |
| * | acpi/acpi_pm.c: refactor acpi_pm_state_for_* functions | Fabio Aiuto | 2022-09-27 | 3 | -3/+3 |
| * | soc/amd/mendocino: Add svc_set_fw_hash_table | Karthikeyan Ramasubramanian | 2022-09-23 | 2 | -0/+14 |
| * | soc/amd/picasso: Add support for PSP NVRAM base addr and size | Ritul Guru | 2022-09-22 | 1 | -0/+10 |
| * | amd/mendocino/root_complex: Throttle SOC during low/no battery | Tim Van Patten | 2022-09-19 | 1 | -0/+12 |
| * | amd/mendocino/acpi/soc: Add DPTC Support | Tim Van Patten | 2022-09-19 | 1 | -0/+7 |
| * | soc/amd/mendocino: Add low/no battery VRM limit registers | Tim Van Patten | 2022-09-19 | 1 | -0/+4 |
| * | amd/mendocino/root_complex: Set DPTC VRM limit values | Tim Van Patten | 2022-09-19 | 1 | -3/+19 |
| * | soc/amd/mendocino: Add VRM limit DPTC registers | Tim Van Patten | 2022-09-19 | 1 | -0/+4 |
| * | soc/amd/acpi: Add low/no battery mode to DPTC | Tim Van Patten | 2022-09-19 | 3 | -0/+42 |
