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* soc/amd/cezanne/cppc: drop duplicate newlineFelix Held2022-08-041-1/+0
| | | | | | | | | | Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I774be6d80e0aae725ecb1027501c8d66e0bf5a08 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66399 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
* soc/amd/cezanne/cppc: reduce visibility of cpu_init_cppc_configFelix Held2022-08-042-2/+1
| | | | | | | | | | | | | This function is only called from the same compilation unit, so turn it into a static function. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I5c2deaa46f69c763df9612e39415b37c60d631be Reviewed-on: https://review.coreboot.org/c/coreboot/+/66398 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
* soc/amd/sabrina/fch: enable XTAL pad disabling in S0i3Felix Held2022-08-032-0/+2
| | | | | | | | | | | | | | | | | | Switching off the pads of the internal crystal oscillator that connect to the crystal on the board in S0i3 saves a little power, so enable it. No measurements to quantify the power savings have been made. PPR #57243 revision 1.59 was used as a reference. BUG=b:237647468 TEST=None Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I52f14ae5c614ad8ff0479b619de7164afa1e7648 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66336 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
* soc/amd/common/block/apob/apob_cache.c: Add assert for APOB DRAM sizeFred Reitberger2022-08-013-4/+7
| | | | | | | | | | | | | | | | Add static check to ensure the reserved APOB DRAM space is the same size as the MRC_CACHE region specified in the fmap. Update sabrina APOB DRAM size to match the fmap. TEST: Timeless builds identical. Test build with a larger MRC_CACHE than APOB DRAM failed the assert as expected. Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: Ia14f6ef94b9062df0612fe96098b1012085ccf9c Reviewed-on: https://review.coreboot.org/c/coreboot/+/65878 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Revert "UPSTREAM: soc/amd/sabrina,vc/amd/fsp/sabrina: Add UART support for ↵Karthikeyan Ramasubramanian2022-08-011-17/+2
| | | | | | | | | | | | | | | | | | | Sabrina" This reverts commit 78261e308de5361b2ff045091e8fb18cad2a5035. Reason for revert: Now that PSP supports a soft fuse flag to toggle the verstage serial logs, prevent PSP verstage from writing to the UART. BUG=None TEST=Build and boot to OS in Skyrim with PSP verstage. Ensure that PSP verstage logs are not seen twice in the console. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I7ef2d585c320ea5903197939136dd2049a71af95 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66248 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* soc/amd/sabrina: Enable HW Modexp engineKarthikeyan Ramasubramanian2022-08-012-2/+8
| | | | | | | | | | | | | | | | | | HW Modexp engine is verified to be working fine. Any verification failures during PSP verstage are because the firmware body is not read correctly. This might be because of the incorrect SPI ROM mapping. Hence enable the HW modexp engine for keyblock, preamble and firmware body verification. BUG=b:240175446 TEST=Build and boot to OS in Skyrim with PSP verstage using one of the FW slots. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I8f6742630a7049354a24053fce28c477e53259e6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66247 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* soc/amd/sabrina: Disable CCP DMA and HW MODEXPKarthikeyan Ramasubramanian2022-07-272-7/+2
| | | | | | | | | | | | | | | Enabling them causes firmware keyblock/preamble and/or body verification failure. Hence disabling them to use software based verification. Re-enable them once the issue is root-caused. BUG=b:217414563 TEST=Build and boot to OS in Skyrim with PSP and x86 verstage. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I7e259ae5d790977d08afcb0a77f8d4f38c85f39e Reviewed-on: https://review.coreboot.org/c/coreboot/+/66134 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/sabrina: Do not pass SHA operation modeKarthikeyan Ramasubramanian2022-07-272-2/+1
| | | | | | | | | | | | | Currently only SHA_GENERIC is used and does not need to be passed. BUG=b:217414563 TEST=Build and boot to OS in Skyrim with PSP and x86 verstage. Change-Id: Id705b1361fffaf940c51515e7f77d7fb0677fc4a Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66133 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* soc/amd/common/block/spi/fch_spi_ctrl: Fix restricted command writeFred Reitberger2022-07-201-1/+1
| | | | | | | | | | | | | | | | The SPI_RESTRICTED_CMD register is not a PCI configuration register. It is memory mapped from the SPI bar. Verified against PPR 55570 rev 3.16, PPR 56569 rev 3.03, and PPR 57243 rev 1.50 TEST=Compile tested only Change-Id: I7c88aaea9ddac200644bb368be3bd4e9be47fd7b Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63305 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/sabrina: Fix boot region address passed to PSPKarthikeyan Ramasubramanian2022-07-202-1/+2
| | | | | | | | | | | | | | | | | PSP expects PSP L2 directory address relative to the start of the SPI ROM. Also PSP does not expect BIOS L2 directory address since it is an entry in PSP L2 directory. Update the configuration such that PSP verstage passes the right address to PSP. BUG=b:217414563 TEST=Build Skyrim BIOS image. Ensure that PSP verstage passes the address as expected by PSP. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I8dc3aa4cb401d16a68da446f83eb9e68ee290fea Reviewed-on: https://review.coreboot.org/c/coreboot/+/65866 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* soc/amd/common/psp_verstage: Fix update_boot_regionKarthikeyan Ramasubramanian2022-07-202-6/+18
| | | | | | | | | | | | | | | | | | | | | | | On SoCs where PSP use A/B recovery layout, PSP expects PSP L2 directory address relative to the start of the SPI ROM. Unfortunately there is nothing in the EFS2 header to help identify such SoCs. Hence add a config item to statically identify such SoCs. Also when PSP uses A/B recovery layout, BIOS L2 directory is an entry in the PSP L2 directory. Hence the address of BIOS L2 directory is not part of EFS2 header. Thankfully PSP is able to identify the BIOS L2 directory itself and does not expect PSP verstage to pass the address. Modify PSP verstage to handle these updates. BUG=b:217414563 TEST=Build Skyrim BIOS image. Ensure that PSP verstage returned the PSP L2 directory as expected. Change-Id: I2f856a62055c80b8e2db91c983832611a5f0389c Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65865 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* soc/amd/sabrina: Do not dump CBMEM pre-bootblock contents to consoleKarthikeyan Ramasubramanian2022-07-201-1/+0
| | | | | | | | | | | | | | | | PSP supports mapping FCH UART and verstage logs are visible in console. Hence pre-bootblock cbmem contents do not have to be dumped to console. BUG=b:238937687 TEST=Build Skyrim BIOS image. Ensure that PSP verstage logs in CBMEM are not dumped to console again during bootblock. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I8336e372b894d8b2f9bbfb21ab15a78527dcc4c4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65863 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* soc/amd/sabrina, mb/google/skyrim: Call espi_switch_to_spi1_padsKarthikeyan Ramasubramanian2022-07-201-0/+1
| | | | | | | | | | | | | | | | | Skyrim uses second SPI pads for ESPI. Switch to it initialize ESPI in verstage. BUG=b:217414563 TEST=Build Skyrim BIOS image. Ensure that ESPI init is successful in PSP verstage. Change-Id: I6e3462e95c50d256b6c159ae1d854dd69a538bb0 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65862 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
* treewide: Remove unused <cpu/x86/msr.h>Elyes Haouas2022-07-202-2/+0
| | | | | | | | Change-Id: I187c2482dd82c6c6d1fe1cbda71710ae1a2f54ad Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64890 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* soc/amd/sabrina/fsp_m_params: add UPD pointer parameter to mb callbackFelix Held2022-07-192-3/+3
| | | | | | | | | | | This allows the mainboard code to change FSP-M parameters depending on parameters that are only known at run time and not at build time. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I3e0e196a5d861acd7635c59db44ecf1970b73ce2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65855 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
* treewide: Don't add bitsElyes Haouas2022-07-181-1/+1
| | | | | | | | Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: Id56310bd616cd19fee5dc934676006b2dc34b1ff Reviewed-on: https://review.coreboot.org/c/coreboot/+/65929 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd: Fix some white spaces issuesElyes Haouas2022-07-176-7/+7
| | | | | | | | Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: Ibe20d48bdd8c776f9658620a13814f96e564dabc Reviewed-on: https://review.coreboot.org/c/coreboot/+/65907 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* soc/amd/common: Fix some white spaces issuesElyes Haouas2022-07-179-16/+16
| | | | | | | | Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I54438978db13ba00188e53239f7034d1b258e912 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65900 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* soc/amd/*/include/soc/iomap.h: Fix some white spaces issuesElyes Haouas2022-07-172-2/+2
| | | | | | | | Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I7b6e41fa3b7cd8c8f7327c690212ec4990e8baf5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65895 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* soc/amd/[cezanne,picasso,sabrina]/Kconfig: Add PSP_APOB_DRAM_SIZE config optionFred Reitberger2022-07-165-4/+16
| | | | | | | | | | | | | | | | | | | | The APOB in sabrina is larger than in cezanne/picasso and no longer fits in the previously allocated 64K space for it. Other symbols are placed immediately after the APOB region and end up corrupting the APOB data on sabrina. Add a Kconfig option to specify the APOB size in DRAM to reserve enough memory and increase the size for sabrina to 128K TEST=Timeless builds are identical for mandolin/majolica for PCO/CZN. Build chausie and verify symbols do not overlap _apob region BUG=b:224056176 Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: Ia5dbacae67ff02fc8a6ec84b9007110ca254daa3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65852 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* soc/amd/picasso: Add MP2 I2C0 and I2C1 controller ACPI devicesRitul Guru2022-07-162-0/+76
| | | | | | | | | | | This change is to allow AMD MP2 I2C OS driver to access I2C0/1 devices when MP2 firmware is loaded. Change-Id: Iaf25eb4dcf949e4b512ec0e86dbe5ccbc91c3d24 Signed-off-by: Ritul Guru <ritul.bits@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65673 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* arch/x86: Mark prepare_and_run_postcar noreturnArthur Heymans2022-07-141-1/+0
| | | | | | | | | | | This moves the die() statement to a common place. Change-Id: I24c9f00bfee169b4ca57b469c089188ec62ddada Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65812 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Julius Werner <jwerner@chromium.org>
* lib/program_loaders.c: Mark run_ramstage with __noreturnArthur Heymans2022-07-143-5/+0
| | | | | | | | | | | | | | This allows the compiler to optimize out code called after run_ramstage. Also remove some die() statements in soc code as run_ramstage already has a die_with_postcode statement. Change-Id: Id8b841712661d3257b0dc67b509f97bdc31fcf6f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65811 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Julius Werner <jwerner@chromium.org>
* commonlib: Substitude macro "__unused" in compiler.hBill XIE2022-07-142-4/+8
| | | | | | | | | | | | | | | | | | | | | | | | Since there are many identifiers whose name contain "__unused" in headers of musl libc, introducing a macro which expands "__unused" to the source of a util may have disastrous effect during its compiling under a musl-based platform. However, it is hard to detect musl at build time as musl is notorious for having explicitly been refusing to add a macro like "__MUSL__" to announce its own presence. Using __always_unused and __maybe_unused for everything may be a good idea. This is how it works in the Linux kernel, so that would at least make us match some other standard rather than doing our own thing (especially since the other compiler.h shorthand macros are also inspired by Linux). Signed-off-by: Bill XIE <persmule@hardenedlinux.org> Change-Id: I547ae3371d7568f5aed732ceefe0130a339716a9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65717 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Julius Werner <jwerner@chromium.org>
* soc/amd/*: Move apm call out of MP init codeArthur Heymans2022-07-143-30/+17
| | | | | | | | | | This makes it easier to have common code for MP init on AMD systems. Change-Id: Icb6808edf96a17ec0b3073ba2486b3345a4a66ea Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64867 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* soc/amd/fsp: Cache smm_region() resultsArthur Heymans2022-07-141-5/+11
| | | | | | | | | | | This avoids searching the HOB output multiple times when calling smm_region(). Change-Id: Iad09c3aa3298745ba3ba7012e6bb8cfb8785d525 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65787 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* cpu/amd: Add common helpers for TSEG and SMMArthur Heymans2022-07-133-17/+38
| | | | | | | | Change-Id: I73174766980e0405e7b8efd4f059bb400c0c0a25 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64866 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* soc/amd/common/block/lpc/lpc.c: Remove duplicated includeElyes Haouas2022-07-081-1/+0
| | | | | | | | Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: Idd214893f304ce767633ffbf905f47a5092c2ee4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65697 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* soc/amd/sabrina,vc/amd/fsp/sabrina: Add UART support for SabrinaJon Murphy2022-07-061-2/+17
| | | | | | | | | | | | | | Sabrina previously didn't support UART mapping in psp verstage. Now that it has been enabled, add the relevant uart code here. BUG=b:218709292 TEST=Set serial soft fuse, boot to kernel, check logs Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: I591fa69b6e722929839babfff62e9d56c68e1112 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65532 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* treewide: Unify Google brandingJon Murphy2022-07-043-3/+3
| | | | | | | | | | | | | | | | | Branding changes to unify and update Chrome OS to ChromeOS (removing the space). This CL also includes changing Chromium OS to ChromiumOS as well. BUG=None TEST=N/A Change-Id: I39af9f1069b62747dbfeebdd62d85fabfa655dcd Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65479 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* soc/amd/sabrina: Add support for Rembrandt SoC as base SoCRitul Guru2022-07-043-4/+110
| | | | | | | | | | | | | This change adds new Rembrandt SoC support by defining it as base SoC of sabrina as sabrina is derived from Rembrandt SoC. All the needed changes for Rembrandt SoC will be applied under SOC_AMD_REMBRANDT config. Change-Id: I1c9392918cc2c6b511d467f99aceefc725750ce6 Signed-off-by: Ritul Guru <ritul.bits@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63353 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* soc/amd/common/psp: Revert AMD_SOC_SEPARATE_EFS_SECTIONFred Reitberger2022-06-303-22/+0
| | | | | | | | | | | | | | | | Reverting commit 1e25fd426ad8 ("soc/amd/common/block/psp: introduce AMD_SOC_SEPARATE_EFS_SECTION"). A better solution was used in commit c17330c1dddb ("mb/amd/chausie: Add EC blob into CBFS"), and this is no longer necessary. TEST: Boot chausie Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I27a8622a1f0d871690b181a79adca225a20996ea Reviewed-on: https://review.coreboot.org/c/coreboot/+/65492 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* soc,sb/amd: Change SPI controller resourceKyösti Mälkki2022-06-281-2/+1
| | | | | | | | | | This replaces IORESOURCE_SUBTRACTIVE with IORESOURCE_RESERVE. Change-Id: Ib3d934ca704273daacbeb3c52412bf04e2be7217 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64695 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/common/block/noncar/cpu: Provide correct smbios processor familyFred Reitberger2022-06-241-0/+6
| | | | | | | | | | | | | | | | Return the correct processor family code for smbios per System Management BIOS (SMBIOS) Reference Specification DSP0134 revision 3.5.0. BUG=b:234409052 TEST=Boot chausie to chromeos and verify "dmidecode -t processor" outputs the correct processor family. Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I617ce3e23f4b28a197034756d285339595d3b53b Reviewed-on: https://review.coreboot.org/c/coreboot/+/65364 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* src/soc: Get rid of most src/soc/Kconfig filesMartin Roth2022-06-241-5/+0
| | | | | | | | | | | | | | | Most of the src/soc/Kconfig files are only there for AMD and Intel to load the main SoC Kconfig files before any common files. That can be done in src/Kconfig instead. Moving the loads to the lower level allows the removal of all but the Intel soc/Kconfig file, which can be removed in a follow-on patch. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I5061191fe23e0b7c745e90874bd7b390806bbcfa Reviewed-on: https://review.coreboot.org/c/coreboot/+/65327 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
* soc/amd/sabrina/Kconfig: remove TODO from SOC_AMD_COMMON_BLOCK_ACPI_GPIOFelix Held2022-06-231-1/+1
| | | | | | | | | | | | | The common AMD ACPI GPIO access code is verified to be correct for Sabrina. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I834076c0a1d1784a272896f2d8f082ebfb86a383 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65317 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
* soc/amd/sabrina: remove TODOs from MCA code/configFelix Held2022-06-232-3/+1
| | | | | | | | | | | | | The MCA banks were updated in commit 736d68c0b36e ("soc/amd/sabrina/mca: update MCA bank names to match the hardware"), but seems that I forgot to remove the TODO about checking if this is still correct for Sabrina. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ifd86113ccb9eeab704679afab0b985f9febed13b Reviewed-on: https://review.coreboot.org/c/coreboot/+/65314 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
* soc/amd/sabrina/Kconfig: remove TODO from SOC_AMD_COMMON_BLOCK_UCODEFelix Held2022-06-231-1/+1
| | | | | | | | | | | | | The common microcode update mechanism is verified to be correct and work on Sabrina. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I5c41674299a829507438beb3ea597a71a0c5a972 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65313 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
* soc/amd/sabrina/Kconfig: set soft fuse bit 34Felix Held2022-06-231-1/+1
| | | | | | | | | | | | | | The bits are documented in NDA document #55758. BUG=b:228458221 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ibc27f617ca9c9620b3b2cb0837b661fa0cd36c2b Reviewed-on: https://review.coreboot.org/c/coreboot/+/65312 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
* soc/amd/picasso/acpi: Add missing UART resourcesMatt DeVillier2022-06-221-0/+8
| | | | | | | | | | | | | | | | | Both UART and DMA MMIO regions for each UART are mapped by the UEFI reference code, so do the same here. Without these defined, UART-attached devices fail to correctly initialize under Windows. Change-Id: I0e1af9028c7c1746407e923cebe824a15aeb565e Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65233 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* device/resource: Add _kb postfix for resource allocatorsKyösti Mälkki2022-06-229-36/+36
| | | | | | | | | | | | There is a lot of going back-and-forth with the KiB arguments, start the work to migrate away from this. Change-Id: I329864d36137e9a99b5640f4f504c45a02060a40 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64658 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/*/Kconfig: drop unused SOC_AMD_COMMON_BLOCK_UCODE_SIZE optionFelix Held2022-06-214-15/+0
| | | | | | | | | | | | | | | | Commit 96f7b96866b0bce7a1323c4da478f838f884383f (soc/amd/common/block/ cpu/: Make ucode update more generic) removed the code that used the SOC_AMD_COMMON_BLOCK_UCODE_SIZE Kconfig value. Drop the now unused Kconfig option. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I079f229678452ff20d8bb282804cd2e49555a6fb Reviewed-on: https://review.coreboot.org/c/coreboot/+/65255 Reviewed-by: ritul guru <ritul.bits@gmail.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
* soc/amd/common/i2c: Add i2c bus ops handlerMatt DeVillier2022-06-211-0/+1
| | | | | | | | | | | | | | Without this, calls to i2c_link() and runtime i2c detection fails on AMD common platform boards. Test: Runtime i2c detection of correct touchpad model succeeds on google/zork. Change-Id: I238b680b2afb4b9d3e5ac75fe9e630b2adc74860 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65232 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* soc/amd/*: Move selection of DRIVERS_I2C_DESIGNWARE to common blockMatt DeVillier2022-06-215-4/+1
| | | | | | | | | | | | | | All AMD SoCs which select SOC_AMD_COMMON_BLOCK_I2C also select DRIVERS_I2C_DESIGNWARE, so make the pairing explicit by moving the selection into SOC_AMD_COMMON_BLOCK_I2C. This will facilitating adding the Designware I2C bus ops handler in a subsequent commit. Change-Id: Ice30c8806766deb9a6ba617c3e633ab069af3b46 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65231 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
* soc/amd/stoneyridge: Align get_cpu_count to other targetsArthur Heymans2022-06-201-1/+1
| | | | | | | | | | | | The CPUID function to get the number of cores on a package is common across multiple generations of AMD cpus. Change-Id: I28bff875ea2df7837e4495787cf8a4c2d522d43d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64869 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
* soc/amd/*: Make mtrr decision based on syscfgArthur Heymans2022-06-204-14/+34
| | | | | | | | | | | | The syscfg has to option to automatically mark the range between 4G and TOM2, which contains DRAM, as WB. Making it generally not necessary to allocate MTRRs for memory above 4G if no PCI BARs are placed up there. Change-Id: Ifbacae28e272ab2f39f268ad034354a9c590d035 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64868 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
* soc/amd/smm_relocate.c: Improve TSEG programmingArthur Heymans2022-06-172-23/+26
| | | | | | | | | | | | | | TSEG does not need to be aligned to 128KiB but to its size, as the MSR works like an MTRR. 128KiB is a minimum TSEG size however. TESTED on google/vilboz. Change-Id: I30854111bb47f0cb14b07f71cedacd629432e0f4 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64865 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
* soc/amd/sabrina: only make the available clock outputs configurableFelix Held2022-06-133-3/+6
| | | | | | | | | | | | | | | Sabrina only has 4 PCIe clock outputs with corresponding clock request pins available, so only make those 4 configurable in devicetree and disable the rest unconditionally. TEST=None Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I5d34fa680dd20a6eec86cc278c1c901b3231df83 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65089 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* soc/amd/sabrina: Update fw.cfg for new names and blobsMarshall Dawson2022-06-101-25/+21
| | | | | | | | | | | | | | Make the config file reflect reality instead of using the old cezanne copy. TEST=Build chausie BUG=b:220848549 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: I8362bc19875ae152e0deab7f64d5b1c50929b95b Reviewed-on: https://review.coreboot.org/c/coreboot/+/65075 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* soc/amd/sabrina: Adjust whitespace in fw.cfgMarshall Dawson2022-06-101-35/+35
| | | | | | | | Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: I591c6a69f0971c3f4fdb8bb54a7f54c948caa648 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65076 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-18 17:08:13 +0000